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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. dra71 sprs960e ? june 2016 ? revised july 2018 dra71x infotainment applications processor 1 device overview 1 1.1 features 1 ? architecture designed for infotainment applications ? video, image, and graphics processing support ? full-hd video (1920 1080p, 60 fps) ? multiple video input and video output ? 2d and 3d graphics ? arm ? cortex ? -a15 microprocessor subsystem ? c66x floating-point vliw dsp ? fully object-code compatible with c67x and c64x+ ? up to thirty-two 16 16-bit fixed-point multiplies per cycle ? up to 512kb of on-chip l3 ram ? level 3 (l3) and level 4 (l4) interconnects ? ddr3/ddr3l memory interface (emif) module ? supports up to ddr-1333 (667 mhz) ? up to 2gb across single chip select ? dual arm ? cortex ? -m4 image processing units (ipu) ? iva-hd subsystem ? display subsystem ? display controller with dma engine and up to three pipelines ? hdmi ? encoder: hdmi 1.4a and dvi 1.0 compliant ? 2d-graphics accelerator (bb2d) subsystem ? vivante ? gc320 core ? video processing engine (vpe) ? single-core powervr ? sgx544 3d gpu ? one video input port (vip) module ? support for up to four multiplexed input ports ? general-purpose memory controller (gpmc) ? enhanced direct memory access (edma) controller ? 2-port gigabit ethernet (gmac) ? up to two external ports ? sixteen 32-bit general-purpose timers ? 32-bit mpu watchdog timer ? six high-speed inter-integrated circuit (i 2 c) ports ? hdq ? / 1-wire ? interface ? ten configurable uart/irda/cir modules ? four multichannel serial peripheral interfaces (mcspi) ? quad spi interface (qspi) ? media local bus subsystem (mlbss) ? eight multichannel audio serial port (mcasp) modules ? superspeed usb 3.0 dual-role device ? high-speed usb 2.0 dual-role device ? high-speed usb 2.0 on-the-go ? four multimedia card/secure digital/secure digital input output interfaces ( mmc ? / sd ? /sdio) ? pci express ? 3.0 subsystems with two 5-gbps lanes ? one 2-lane gen2-compliant port ? or two 1-lane gen2-compliant ports ? dual controller area network (dcan) modules ? can 2.0b protocol ? mipi ? csi-2 camera serial interface ? up to 186 general-purpose i/o (gpio) pins ? device security features ? hardware crypto accelerators and dma ? firewalls ? jtag lock ? secure keys ? secure rom and boot ? customer programmable keys ? power, reset, and clock management ? on-chip debug with ctools technology ? 28-nm cmos technology ? 17 mm 17 mm, 0.65-mm pitch, 538-pin bga (cbd) ordernow productfolder support &community tools & software technical documents
2 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 device overview copyright ? 2016 ? 2018, texas instruments incorporated 1.2 applications ? human-machine interface (hmi) ? navigation ? digital and analog radio ? multimedia playback ? automotive display audio systems ? automotive entry navigation and multimedia systems ? automotive digital cluster systems 1.3 description the dra71x processor is offered in a 538-ball, 17 17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with via channel ? array (vca) technology, ball grid array (bga) package. the architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the dra75x ("jacinto 6 ep" and "jacinto 6 ex"), dra74x "jacinto 6" and dra72x "jacinto 6 eco" family of infotainment processors, including graphics, voice, hmi, multimedia and smartphone projection mode capabilities. programmability is provided by a single-core arm cortex-a15 risc cpu with neon ? extensions and a ti c66x vliw floating-point dsp core. the arm processor lets developers keep control functions separate from other algorithms programmed on the dsp and coprocessors, thus reducing the complexity of the system software. additionally, ti provides a complete set of development tools for the arm, and dsp, including c compilers and a debugging interface for visibility into source code execution. cryptographic acceleration is available in all devices. all other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on high-security (hs) devices. for more information about hs devices, contact your ti representative. the dra71x jacinto 6 entry processor family is qualified according to the aec-q100 standard. the device features a simplified power supply rail mapping which enables lower cost pmic solutions. device information part number package body size dra71x fcbga (538) 17.0 mm 17.0 mm 3 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 device overview copyright ? 2016 ? 2018, texas instruments incorporated 1.4 functional block diagram figure 1-1 is functional block diagram for the device. figure 1-1. dra71x block diagram (1x c66x co-processor) mailbox x13 edma high-speed interconnect program/data storage connectivity system (1x arm cortexCa15) iva hd 1080p video co-processor dsp pcie ss x2 medialb (nand/nor/ async) (1x sgx544 3d) vip x1 (dual cortexCm4) intro-001 gpmc / elm 256-kb rom ocmc dra71x gpu mpu ipu1 serial interfaces i2c x6 uart x10 mcspi x4 dcan x2 spinlock gpio x8 timers x16 wdt qspi emif x1 1x 32-bit ddr3/ddr3l sdma vpe mcasp x8 mmu x2 cal csi2 x1 bb2d (gc320 2d) (dual cortexCm4) ipu2 pwm ss x3 hdq kbd gmac avb most150 1x usb 3.0 dual mode fs/hs/ss w/ phy 2x usb 2.0 dual mode fs/hs 1x phy, 1x ulpi radio accelerators vcp x2 hd atl 512-kb ram with ecc dmm mmc / sd x4 pru-icss x2 copyright ? 2016, texas instruments incorporated display subsystem 1xgfx / 3xvid blend / scale hdmi 1.4a lcd3 secure boot debug security tee (hs devices) lcd2 4 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 table of contents copyright ? 2016 ? 2018, texas instruments incorporated table of contents 1 device overview ......................................... 1 1.1 features .............................................. 1 1.2 applications ........................................... 2 1.3 description ............................................ 2 1.4 functional block diagram ........................... 3 2 revision history ......................................... 5 3 device comparison ..................................... 6 3.1 device comparison table ............................ 6 3.2 related products ..................................... 8 4 terminal configuration and functions .............. 9 4.1 pin diagram .......................................... 9 4.2 pin attributes ......................................... 9 4.3 signal descriptions .................................. 68 4.4 pin multiplexing .................................... 106 4.5 connections for unused pins ...................... 120 5 specifications ......................................... 121 5.1 absolute maximum ratings ........................ 122 5.2 esd ratings ....................................... 123 5.3 power on hours (poh) limits ..................... 123 5.4 recommended operating conditions ............. 123 5.5 operating performance points ..................... 126 5.6 power consumption summary .................... 146 5.7 electrical characteristics ........................... 146 5.8 vpp specifications for one-time programmable (otp) efuses ...................................... 154 5.9 thermal resistance characteristics for cbd package ............................................ 155 5.10 timing requirements and switching characteristics ..................................... 157 6 detailed description .................................. 331 6.1 description ......................................... 331 6.2 functional block diagram ......................... 331 6.3 mpu ................................................ 333 6.4 dsp subsystem ................................... 336 6.5 iva ................................................. 340 6.6 ipu ................................................. 340 6.7 gpu ................................................ 341 6.8 bb2d ............................................... 343 6.9 pru-icss .......................................... 344 6.10 memory subsystem ................................ 345 6.11 interprocessor communication .................... 348 6.12 interrupt controller ................................. 349 6.13 edma .............................................. 350 6.14 peripherals ......................................... 351 6.15 on-chip debug ..................................... 368 7 applications, implementation, and layout ...... 371 7.1 introduction ........................................ 371 7.2 power optimizations ............................... 372 7.3 core power domains .............................. 383 7.4 single-ended interfaces ........................... 394 7.5 differential interfaces .............................. 396 7.6 clock routing guidelines .......................... 415 7.7 ddr3 board design and layout guidelines ....... 415 8 device and documentation support .............. 439 8.1 device nomenclature .............................. 439 8.2 tools and software ................................ 441 8.3 documentation support ............................ 441 8.4 related links ...................................... 442 8.5 receiving notification of documentation updates . 442 8.6 community resources ............................. 442 8.7 trademarks ........................................ 442 8.8 electrostatic discharge caution ................... 443 8.9 export control notice .............................. 443 8.10 glossary ............................................ 443 9 mechanical packaging and orderable information ............................................. 444 9.1 mechanical data ................................... 444 5 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 revision history copyright ? 2016 ? 2018, texas instruments incorporated 2 revision history changes from may 6, 2018 to july 15, 2018 (from d revision (may 2018) to e revision) page ? removed a part of secure boot support information ........................................................................... 1 ? added ipu1 and ipu2 support for dra710 in table 3-1 , device comparison .............................................. 6 ? updated porz, resetn and rstoutn signal descriptions in table 4-28 , prcm signal descriptions ...................... 102 ? updated vpp supply voltage range for normal operation in table 5-14 , recommended operating conditions for otp efuse programming ........................................................................................................ 154 ? updated figure 5-5 , power-up sequencing ................................................................................... 159 ? updated system clock names in section 5.10.4 , clock specifications .................................................... 166 ? updated phase polarity in all qspi timing figures ............................................................................. 239 ? updated note for cosmetic marks on package ................................................................................. 440 6 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 device comparison copyright ? 2016 ? 2018, texas instruments incorporated 3 device comparison 3.1 device comparison table table 3-1 shows a comparison between devices, highlighting the differences. table 3-1. device comparison features device dra710 dra712 dra714 dra716 dra718 features ctrl_wkup_std_fuse_die_id_2 [31:24] base pn register bitfield value (1) 64 (0x40) 66 (0x42) 68 (0x44) 70 (0x46) 72 (0x48) processors/accelerators speed grades e e e , f g , h i , j arm single cortex-a15 microprocessor (mpu) subsystem mpu core 0 yes c66x vliw dsp dsp1 no no yes yes yes bitblt 2d hardware acceleration engine (bb2d) bb2d yes display subsystem vout1 no vout2 yes vout3 yes hdmi yes dual arm cortex-m4 image processing unit (ipu) ipu1 yes yes yes yes yes ipu2 yes yes yes yes yes image video accelarator (iva) iva yes yes yes yes yes sgx544 single-core 3d graphics processing unit (gpu) gpu no yes yes yes yes video input port (vip) vip1 vin1a yes vin1b yes vin2a yes vin2b yes video processing engine (vpe) vpe yes program/data storage on-chip shared memory (ram) ocmc_ram1 512kb 512kb 512kb 512kb 512kb general-purpose memory controller (gpmc) gpmc yes ddr3/ddr3l memory controller emif1 up to 2gb dynamic memory manager (dmm) dmm yes radio support audio tracking logic (atl) atl yes viterbi coprocessor (vcp) vcp1 yes vcp2 yes peripherals controller area network (dcan) interface dcan1 yes dcan2 yes enhanced dma (edma) edma yes system dma (dma_system) dma_system yes ethernet subsystem (ethernet ss) gmac_sw[0] mii, rmii, or rgmii gmac_sw[1] mii, rmii, or rgmii general-purpose i/o (gpio) gpio up to 186 7 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 device comparison copyright ? 2016 ? 2018, texas instruments incorporated table 3-1. device comparison (continued) features device dra710 dra712 dra714 dra716 dra718 inter-integrated circuit interface (i 2 c) i2c 6 system mailbox module mailbox 13 media local bus subsystem (mlbss) mlb yes camera adaptation layer (cal) camera serial interface 2 (csi2) csi2_0 1 clk + 2 data csi2_1 no multichannel audio serial port (mcasp) mcasp1 16 serializers mcasp2 16 serializers mcasp3 4 serializers mcasp4 4 serializers mcasp5 4 serializers mcasp6 4 serializers mcasp7 4 serializers mcasp8 2 serializers multimedia card/secure digital/secure digital input output interface (mmc/sd/sdio) mmc1 1x uhsi 4b mmc2 1x emmc 8b mmc3 1x sdio 8b mmc4 1x sdio 4b pci express 3.0 port with integrated phy pcie_ss1 up to two lanes (second lane shared with pcie_ss2 and usb1) pcie_ss2 single lane (shared with pcie_ss1 and usb1) serial advanced technology attachment (sata) sata no real-time clock subsystem (rtcss) rtcss no programmable real-time unit subsystem and industrial communication subsystem (pru- icss) pru-icss1 no no yes yes yes pru-icss2 no no yes yes yes multichannel serial peripheral interface (mcspi) mcspi 4 hdq1w hdq1w yes quad spi (qspi) qspi yes spinlock module spinlock yes keyboard controller (kbd) kbd yes timers, general-purpose timers gp 16 timer, watchdog wd timer yes pulse-width modulation subsystem (pwmss) pwmss1 yes pwmss2 yes pwmss3 yes universal asynchronous receiver/transmitter (uart) uart 10 universal serial bus (usb3.0) usb1 (super- speed, dual-role- device [drd]) yes universal serial bus (usb2.0) usb2 (high- speed, dual-role- device [drd], with embedded hs phy) yes usb3 (high- speed, otg2.0, with ulpi) yes usb4 (high- speed, otg2.0, with ulpi) no 8 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 device comparison copyright ? 2016 ? 2018, texas instruments incorporated (1) for more details about the ctrl_wkup_std_fuse_die_id_2 register and base pn bitfield, see the dra71x technical reference manual. 3.2 related products automotive processors drax infotainment socs the "jacinto 6" family of infotainment processors (dra7xx), paired with robust software and ecosystem offering bring unprecedented feature-rich, in-vehicle infotainment, instrument cluster and telematics features to the next generation automobiles. 9 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4 terminal configuration and functions 4.1 pin diagram figure 4-1 shows the ball locations for the 538 plastic ball grid array (pbga) package and isused in conjunction with table 4-1 through table 4-31 to locate signal names and ball grid numbers. figure 4-1. cbd s-pbga-n538 package (bottom view) note the following bottom balls are not pinned out: ae4 / ae7 / ae10 / ae13 / ad5 / ad8 / ad11 / ad14 / ac7 / ac9 / ac12 / ac14 / ac17 / ab3 / ab4 / ab5 / ab13 / ab14 / ab17 / ab20 / ab21 / ab22 / aa14 / aa17 / aa22 / y22 / w3 / w4 / w5 / w6 / v6 / v21 / v22 / v23 / r3 / r4 / r5 / r6 / r21 / r22 / r23 / p6 / m3 / m4 / m5 / m6 / m21 / m22 / m23 / j3 / j4 / j5 / j6 / j21 / j22 / j23 / f4 / f5 / f9 / f12 / f15 / f18 / f21 / f22 / e3 / e4 / e5 / e6 / e9 / e12 / e15 / e18 / e21 / e22 / e23 / d4 / d5 / d9 / d12 / d15 / d18 / d21 / d22 / c9 / c12 / c15 / c18. these balls do not exist on the package. 4.2 pin attributes table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. the following list describes the table column headers: 1. ball number: this column lists ball numbers on the bottom side associated with each signal on the bottom. 2. ball name: this column lists mechanical name from package device (name is taken from muxmode 0). 3. signal name: this column lists names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0). note table 4-1 does not take into account the subsystem multiplexing signals. subsystem multiplexing signals are described in section 4.3 , signal descriptions . note in driver off mode, the buffer is configured in high-impedance. 10 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated note in some cases table 4-1 may present more than one signal name per muxmode for the same ball. first signal in the list is the dominant function as selected via ctrl_core_pad_* register. all other signals are virtual functions that present alternate multiplexing options. this virtual functions are controlled via ctrl_core_alt_select_mux or ctrl_core_vip_mux_select register. for more information on how to use this options, please refer to device trm, chapter control module , section pad configuration registers. 4. support: this column shows if the functionality is applicable for dra710 / dra712 devices. note that the pin attributes table presents the functionality of dra718 device. an empty box means "yes". 5. muxmode: multiplexing mode number: a. muxmode 0 is the primary mode; this means that when muxmode=0 is set, the function mapped on the pin corresponds to the name of the pin. the primary muxmode is not necessarily the default muxmode. note the default mode is the mode at the release of the reset; also see the reset rel. muxmode column. b. muxmode 1 through 15 are possible muxmodes for alternate functions. on each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. only muxmode values which correspond to defined functions should be used. c. an empty box means not applicable. 6. type: signal type and direction: ? i = input ? o = output ? io = input or output ? d = open drain ? ds = differential signaling ? a = analog ? pwr = power ? gnd = ground ? cap = ldo capacitor 7. ball reset state: the state of the terminal at power-on reset: ? drive 0 (off): the buffer drives v ol (pulldown or pullup resistor not activated) ? drive 1 (off): the buffer drives v oh (pulldown or pullup resistor not activated) ? off: high-impedance ? pd: high-impedance with an active pulldown resistor ? pu: high-impedance with an active pullup resistor ? an empty box means not applicable 8. ball reset rel. state: the state of the terminal at the deactivation of the rstoutn signal (also mapped to the prcm sys_warm_out_rst signal) ? drive 0 (off): the buffer drives v ol (pulldown or pullup resistor not activated) ? drive clk (off): the buffer drives a toggling clock (pulldown or pullup resistor not activated) ? drive 1 (off): the buffer drives v oh (pulldown or pullup resistor not activated) ? off: high-impedance ? pd: high-impedance with an active pulldown resistor ? pu: high-impedance with an active pullup resistor ? an empty box means not applicable 11 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated note for more information on the core_pwron_ret_rst reset signal and its reset sources, see the power, reset, and clock management / prcm reset management functional description section of the device trm. 9. ball reset rel. muxmode: this muxmode is automatically configured at the release of the rstoutn signal (also mapped to the prcm sys_warm_out_rst signal). an empty box means not applicable. 10. io voltage value : this column describes the io voltage value (the corresponding power supply). an empty box means not applicable. 11. power: the voltage supply that powers the terminal io buffers. an empty box means not applicable. 12. hys: indicates if the input buffer is with hysteresis: ? yes: with hysteresis ? no: without hysteresis ? an empty box: not applicable note for more information, see the hysteresis values in section 5.7 , electrical characteristics . 13. buffer type: drive strength of the associated output buffer. an empty box means not applicable. note for programmable buffer strength: ? the default value is given in table 4-1 . ? a note describes all possible values according to the selected muxmode. 14. pullup / pulldown type: denotes the presence of an internal pullup or pulldown resistor. pullup and pulldown resistors can be enabled or disabled via software. ? pu: internal pullup ? pd: internal pulldown ? pu/pd: internal pullup and pulldown ? pux/pdy: programmable internal pullup and pulldown ? pdy: programmable internal pulldown ? an empty box means no pull 15. dsis: the deselected input state (dsis) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the pincntlx registers. ? 0: logic 0 driven on the peripheral's input signal port. ? 1: logic 1 driven on the peripheral's input signal port. ? blank: pin state driven on the peripheral's input signal port. note configuring two pins to the same input signal is not supported as it can yield unexpected results. this can be easily prevented with the proper software configuration (hi-z mode is not an input signal). note when a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad ? s behavior is undefined. this should be avoided. 12 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated note some of the emif1 signals have an additional state change at the release of porz. the state that the signals change to at the release of porz is as follows: drive 0 (off) for: ddr1_ck, ddr1_odt[0], ddr1_rst. drive 1 (off) for: ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_nck, ddr1_ba[2:0], ddr1_a[15:0], ddr1_csn[0], ddr1_cke, ddr1_dqm[3:0]. note dual rank support is not available on this device, but signal names are retained for consistency with the dra7xx family of devices. copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 13 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] f8 cap_vbbldo_dsp cap_vbbldo_dsp cap t7 cap_vbbldo_gpu cap_vbbldo_gpu cap g14 cap_vbbldo_iva cap_vbbldo_iva cap f17 cap_vbbldo_mpu cap_vbbldo_mpu cap u20 cap_vddram_core1 cap_vddram_core1 cap k7 cap_vddram_core3 cap_vddram_core3 cap g19 cap_vddram_core4 cap_vddram_core4 cap l7 cap_vddram_dsp cap_vddram_dsp cap v7 cap_vddram_gpu cap_vddram_gpu cap g12 cap_vddram_iva cap_vddram_iva cap g18 cap_vddram_mpu cap_vddram_mpu cap ac1 csi2_0_dx0 csi2_0_dx0 0 i 1.8 yes lvcmos csi2 pu/pd ad1 csi2_0_dx1 csi2_0_dx1 0 i 1.8 yes lvcmos csi2 pu/pd ae2 csi2_0_dx2 csi2_0_dx2 0 i 1.8 yes lvcmos csi2 pu/pd ab2 csi2_0_dy0 csi2_0_dy0 0 i 1.8 yes lvcmos csi2 pu/pd ac2 csi2_0_dy1 csi2_0_dy1 0 i 1.8 yes lvcmos csi2 pu/pd ad2 csi2_0_dy2 csi2_0_dy2 0 i 1.8 yes lvcmos csi2 pu/pd h23 dcan1_rx dcan1_rx 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 uart8_txd 2 o mmc2_sdwp 3 i 0 hdmi1_cec 6 io gpio1_15 14 io driver off 15 i h22 dcan1_tx dcan1_tx 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 uart8_rxd 2 i 1 mmc2_sdcd 3 i 1 hdmi1_hpd 6 io gpio1_14 14 io driver off 15 i ac18 ddr1_a0 ddr1_a0 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae19 ddr1_a1 ddr1_a1 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 14 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] ad19 ddr1_a2 ddr1_a2 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab19 ddr1_a3 ddr1_a3 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad20 ddr1_a4 ddr1_a4 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae20 ddr1_a5 ddr1_a5 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa18 ddr1_a6 ddr1_a6 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa20 ddr1_a7 ddr1_a7 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy y21 ddr1_a8 ddr1_a8 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac20 ddr1_a9 ddr1_a9 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa21 ddr1_a10 ddr1_a10 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac21 ddr1_a11 ddr1_a11 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac22 ddr1_a12 ddr1_a12 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac15 ddr1_a13 ddr1_a13 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab15 ddr1_a14 ddr1_a14 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac16 ddr1_a15 ddr1_a15 0 o pd drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae16 ddr1_ba0 ddr1_ba0 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa16 ddr1_ba1 ddr1_ba1 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab16 ddr1_ba2 ddr1_ba2 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad16 ddr1_casn ddr1_casn 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad21 ddr1_ck ddr1_ck 0 o pd drive 0 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab18 ddr1_cke ddr1_cke 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac19 ddr1_csn0 ddr1_csn0 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa23 ddr1_d0 ddr1_d0 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac24 ddr1_d1 ddr1_d1 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 15 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] ab24 ddr1_d2 ddr1_d2 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad24 ddr1_d3 ddr1_d3 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab23 ddr1_d4 ddr1_d4 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac23 ddr1_d5 ddr1_d5 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad23 ddr1_d6 ddr1_d6 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae24 ddr1_d7 ddr1_d7 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa24 ddr1_d8 ddr1_d8 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy w25 ddr1_d9 ddr1_d9 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy y23 ddr1_d10 ddr1_d10 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad25 ddr1_d11 ddr1_d11 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ac25 ddr1_d12 ddr1_d12 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ab25 ddr1_d13 ddr1_d13 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy aa25 ddr1_d14 ddr1_d14 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy w24 ddr1_d15 ddr1_d15 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy w23 ddr1_d16 ddr1_d16 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy u25 ddr1_d17 ddr1_d17 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy u24 ddr1_d18 ddr1_d18 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy w21 ddr1_d19 ddr1_d19 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy t22 ddr1_d20 ddr1_d20 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy u22 ddr1_d21 ddr1_d21 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy u23 ddr1_d22 ddr1_d22 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy t21 ddr1_d23 ddr1_d23 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy t23 ddr1_d24 ddr1_d24 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 16 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] t25 ddr1_d25 ddr1_d25 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy t24 ddr1_d26 ddr1_d26 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy p21 ddr1_d27 ddr1_d27 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy n21 ddr1_d28 ddr1_d28 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy p22 ddr1_d29 ddr1_d29 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy p23 ddr1_d30 ddr1_d30 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy p24 ddr1_d31 ddr1_d31 0 io pd pd 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae23 ddr1_dqm0 ddr1_dqm0 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy w22 ddr1_dqm1 ddr1_dqm1 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy u21 ddr1_dqm2 ddr1_dqm2 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy p25 ddr1_dqm3 ddr1_dqm3 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad22 ddr1_dqs0 ddr1_dqs0 0 io pd pd 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy y24 ddr1_dqs1 ddr1_dqs1 0 io pd pd 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy v24 ddr1_dqs2 ddr1_dqs2 0 io pd pd 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy r24 ddr1_dqs3 ddr1_dqs3 0 io pd pd 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy ae22 ddr1_dqsn0 ddr1_dqsn0 0 io pu pu 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy y25 ddr1_dqsn1 ddr1_dqsn1 0 io pu pu 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy v25 ddr1_dqsn2 ddr1_dqsn2 0 io pu pu 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy r25 ddr1_dqsn3 ddr1_dqsn3 0 io pu pu 1.35/1.5 vdds_ddr1 lvcmos ddr pux/pdy ae21 ddr1_nck ddr1_nck 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad18 ddr1_odt0 ddr1_odt0 0 o pd drive 0 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ad17 ddr1_rasn ddr1_rasn 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy ae17 ddr1_rst ddr1_rst 0 o pd drive 0 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 17 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] y20 ddr1_vref0 ddr1_vref0 0 pwr off drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr ae18 ddr1_wen ddr1_wen 0 o pu drive 1 (off) 1.35/1.5 vdds_ddr1 no lvcmos ddr pux/pdy c21 emu0 emu0 0 io pu pu 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd gpio8_30 14 io c22 emu1 emu1 0 io pu pu 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd gpio8_31 14 io e14 emu2 emu2 2 o pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd f14 emu3 emu3 2 o pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd f13 emu4 emu4 2 o pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd y5 gpio6_10 gpio6_10 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd mdio_mclk 1 o 1 i2c3_sda 2 io 1 usb3_ulpi_d7 3 io 0 vin2b_hsync1 4 i vin1a_clk0 9 i 0 ehrpwm2a 10 o pr2_mii_mt1_clk no 11 i 0 pr2_pru0_gpi0 no 12 i pr2_pru0_gpo0 no 13 o gpio6_10 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 18 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] y6 gpio6_11 gpio6_11 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd mdio_d 1 io 1 i2c3_scl 2 io 1 usb3_ulpi_d6 3 io 0 vin2b_vsync1 4 i vin1a_de0 9 i 0 ehrpwm2b 10 o pr2_mii1_txen no 11 o pr2_pru0_gpi1 no 12 i pr2_pru0_gpo1 no 13 o gpio6_11 14 io driver off 15 i h21 gpio6_14 gpio6_14 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp1_axr8 1 io 0 dcan2_tx 2 io 1 uart10_rxd 3 i 1 i2c3_sda 9 io 1 timer1 10 io gpio6_14 14 io driver off 15 i k22 gpio6_15 gpio6_15 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp1_axr9 1 io 0 dcan2_rx 2 io 1 uart10_txd 3 o i2c3_scl 9 io 1 timer2 10 io gpio6_15 14 io driver off 15 i k23 gpio6_16 gpio6_16 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp1_axr10 1 io 0 clkout1 9 o timer3 10 io gpio6_16 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 19 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] m1 gpmc_a0 gpmc_a0 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d16 2 i 0 vout3_d16 3 o vin1b_d0 6 i 0 i2c4_scl 7 io 1 uart5_rxd 8 i 1 gpio7_3 gpmc_a26 gpmc_a16 14 io driver off 15 i m2 gpmc_a1 gpmc_a1 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d17 2 i 0 vout3_d17 3 o vin1b_d1 6 i 0 i2c4_sda 7 io 1 uart5_txd 8 o gpio7_4 14 io driver off 15 i l2 gpmc_a2 gpmc_a2 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d18 2 i 0 vout3_d18 3 o vin1b_d2 6 i 0 uart7_rxd 7 i 1 uart5_ctsn 8 i 1 gpio7_5 14 io driver off 15 i l1 gpmc_a3 gpmc_a3 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_cs2 1 o 1 vin1a_d19 2 i 0 vout3_d19 3 o vin1b_d3 6 i 0 uart7_txd 7 o uart5_rtsn 8 o gpio7_6 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 20 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] k3 gpmc_a4 gpmc_a4 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_cs3 1 o 1 vin1a_d20 2 i 0 vout3_d20 3 o vin1b_d4 6 i 0 i2c5_scl 7 io 1 uart6_rxd 8 i 1 gpio1_26 14 io driver off 15 i k2 gpmc_a5 gpmc_a5 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d21 2 i 0 vout3_d21 3 o vin1b_d5 6 i 0 i2c5_sda 7 io 1 uart6_txd 8 o gpio1_27 14 io driver off 15 i j1 gpmc_a6 gpmc_a6 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d22 2 i 0 vout3_d22 3 o vin1b_d6 6 i 0 uart8_rxd 7 i 1 uart6_ctsn 8 i 1 gpio1_28 14 io driver off 15 i k1 gpmc_a7 gpmc_a7 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_d23 2 i 0 vout3_d23 3 o vin1b_d7 6 i 0 uart8_txd 7 o uart6_rtsn 8 o gpio1_29 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 21 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] k4 gpmc_a8 gpmc_a8 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_hsync0 2 i 0 vout3_hsync 3 o vin1b_hsync1 6 i 0 timer12 7 io spi4_sclk 8 io 0 gpio1_30 14 io driver off 15 i h1 gpmc_a9 gpmc_a9 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_vsync0 2 i 0 vout3_vsync 3 o vin1b_vsync1 6 i 0 timer11 7 io spi4_d1 8 io 0 gpio1_31 14 io driver off 15 i j2 gpmc_a10 gpmc_a10 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_de0 2 i 0 vout3_de 3 o vin1b_clk1 6 i 0 timer10 7 io spi4_d0 8 io 0 gpio2_0 14 io driver off 15 i l3 gpmc_a11 gpmc_a11 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd vin1a_fld0 2 i 0 vout3_fld 3 o vin1b_de1 6 i 0 timer9 7 io spi4_cs0 8 io 1 gpio2_1 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 22 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] g1 gpmc_a12 gpmc_a12 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpmc_a0 5 o vin1b_fld1 6 i 0 timer8 7 io spi4_cs1 8 io 1 dma_evt1 9 i 0 gpio2_2 14 io driver off 15 i h3 gpmc_a13 gpmc_a13 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_rtclk 1 i 0 timer7 7 io spi4_cs2 8 io 1 dma_evt2 9 i 0 gpio2_3 14 io driver off 15 i h4 gpmc_a14 gpmc_a14 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_d3 1 io 0 timer6 7 io spi4_cs3 8 io 1 gpio2_4 14 io driver off 15 i k6 gpmc_a15 gpmc_a15 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_d2 1 io 0 timer5 7 io gpio2_5 14 io driver off 15 i k5 gpmc_a16 gpmc_a16 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_d0 1 io 0 gpio2_6 14 io driver off 15 i g2 gpmc_a17 gpmc_a17 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_d1 1 io 0 gpio2_7 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 23 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] f2 gpmc_a18 gpmc_a18 0 o pd pd 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_sclk 1 io gpio2_8 14 io driver off 15 i a4 (9) gpmc_a19 gpmc_a19 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat4 1 io 1 gpmc_a13 2 o vin2b_d0 6 i 0 gpio2_9 14 io driver off 15 i e7 (9) gpmc_a20 gpmc_a20 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat5 1 io 1 gpmc_a14 2 o vin2b_d1 6 i 0 gpio2_10 14 io driver off 15 i d6 (9) gpmc_a21 gpmc_a21 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat6 1 io 1 gpmc_a15 2 o vin2b_d2 6 i 0 gpio2_11 14 io driver off 15 i c5 (9) gpmc_a22 gpmc_a22 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat7 1 io 1 gpmc_a16 2 o vin2b_d3 6 i 0 gpio2_12 14 io driver off 15 i b5 gpmc_a23 gpmc_a23 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_clk 1 io 1 gpmc_a17 2 o vin2b_d4 6 i 0 gpio2_13 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 24 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] d7 (9) gpmc_a24 gpmc_a24 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat0 1 io 1 gpmc_a18 2 o vin2b_d5 6 i 0 gpio2_14 14 io driver off 15 i c6 (9) gpmc_a25 gpmc_a25 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat1 1 io 1 gpmc_a19 2 o vin2b_d6 6 i 0 gpio2_15 14 io driver off 15 i a5 (9) gpmc_a26 gpmc_a26 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat2 1 io 1 gpmc_a20 2 o vin2b_d7 6 i 0 gpio2_16 14 io driver off 15 i b6 (9) gpmc_a27 gpmc_a27 0 o pd pd 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_dat3 1 io 1 gpmc_a21 2 o vin2b_hsync1 6 i gpio2_17 14 io driver off 15 i f1 gpmc_ad0 gpmc_ad0 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d0 2 i 0 vout3_d0 3 o gpio1_6 14 io sysboot0 15 i e2 gpmc_ad1 gpmc_ad1 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d1 2 i 0 vout3_d1 3 o gpio1_7 14 io sysboot1 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 25 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] e1 gpmc_ad2 gpmc_ad2 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d2 2 i 0 vout3_d2 3 o gpio1_8 14 io sysboot2 15 i c1 gpmc_ad3 gpmc_ad3 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d3 2 i 0 vout3_d3 3 o gpio1_9 14 io sysboot3 15 i d1 gpmc_ad4 gpmc_ad4 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d4 2 i 0 vout3_d4 3 o gpio1_10 14 io sysboot4 15 i d2 gpmc_ad5 gpmc_ad5 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d5 2 i 0 vout3_d5 3 o gpio1_11 14 io sysboot5 15 i b1 gpmc_ad6 gpmc_ad6 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d6 2 i 0 vout3_d6 3 o gpio1_12 14 io sysboot6 15 i b2 gpmc_ad7 gpmc_ad7 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d7 2 i 0 vout3_d7 3 o gpio1_13 14 io sysboot7 15 i c2 gpmc_ad8 gpmc_ad8 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d8 2 i 0 vout3_d8 3 o gpio7_18 14 io sysboot8 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 26 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] d3 gpmc_ad9 gpmc_ad9 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d9 2 i 0 vout3_d9 3 o gpio7_19 14 io sysboot9 15 i a2 gpmc_ad10 gpmc_ad10 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d10 2 i 0 vout3_d10 3 o gpio7_28 14 io sysboot10 15 i b3 gpmc_ad11 gpmc_ad11 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d11 2 i 0 vout3_d11 3 o gpio7_29 14 io sysboot11 15 i c3 gpmc_ad12 gpmc_ad12 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d12 2 i 0 vout3_d12 3 o gpio1_18 14 io sysboot12 15 i c4 gpmc_ad13 gpmc_ad13 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d13 2 i 0 vout3_d13 3 o gpio1_19 14 io sysboot13 15 i a3 gpmc_ad14 gpmc_ad14 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d14 2 i 0 vout3_d14 3 o gpio1_20 14 io sysboot14 15 i b4 gpmc_ad15 gpmc_ad15 0 io off off 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 vin1a_d15 2 i 0 vout3_d15 3 o gpio1_21 14 io sysboot15 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 27 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] h5 gpmc_advn_ale gpmc_advn_ale 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpmc_cs6 1 o clkout2 2 o gpmc_wait1 3 i 1 gpmc_a2 5 o gpmc_a23 6 o timer3 7 io i2c3_sda 8 io 1 dma_evt2 9 i 0 gpio2_23 gpmc_a19 14 io driver off 15 i h2 gpmc_ben0 gpmc_ben0 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpmc_cs4 1 o vin2b_de1 6 i timer2 7 io dma_evt3 9 i 0 gpio2_26 gpmc_a21 14 io driver off 15 i h6 gpmc_ben1 gpmc_ben1 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpmc_cs5 1 o vin2b_clk1 4 i gpmc_a3 5 o vin2b_fld1 6 i timer1 7 io dma_evt4 9 i 0 gpio2_27 gpmc_a22 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 28 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] l4 gpmc_clk gpmc_clk 0 io pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 0 gpmc_cs7 1 o clkout1 2 o gpmc_wait1 3 i 1 vin2b_clk1 6 i timer4 7 io i2c3_scl 8 io 1 dma_evt1 9 i 0 gpio2_22 gpmc_a20 14 io driver off 15 i f3 gpmc_cs0 gpmc_cs0 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpio2_19 14 io driver off 15 i a6 gpmc_cs1 gpmc_cs1 0 o pu pu 15 1.8/3.3 vddshv11 yes dual voltage lvcmos pu/pd mmc2_cmd 1 io 1 gpmc_a22 2 o vin2b_vsync1 6 i gpio2_18 14 io driver off 15 i g4 gpmc_cs2 gpmc_cs2 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_cs0 1 io 1 gpio2_20 gpmc_a23 gpmc_a13 14 io driver off 15 i g3 gpmc_cs3 gpmc_cs3 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd qspi1_cs1 1 o 1 vin1a_clk0 2 i 0 vout3_clk 3 o gpmc_a1 5 o gpio2_21 gpmc_a24 gpmc_a14 14 io driver off 15 i g5 gpmc_oen_ren gpmc_oen_ren 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpio2_24 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 29 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] f6 gpmc_wait0 gpmc_wait0 0 i pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd 1 gpio2_28 gpmc_a25 gpmc_a15 14 io driver off 15 i g6 gpmc_wen gpmc_wen 0 o pu pu 15 1.8/3.3 vddshv10 yes dual voltage lvcmos pu/pd gpio2_25 14 io driver off 15 i ae9 hdmi1_clockx hdmi1_clockx 0 o 1.8 vdda_hdmi hdmiphy pdy ad10 hdmi1_clocky hdmi1_clocky 0 o 1.8 vdda_hdmi hdmiphy pdy ae11 hdmi1_data0x hdmi1_data0x 0 o 1.8 vdda_hdmi hdmiphy pdy ad12 hdmi1_data0y hdmi1_data0y 0 o 1.8 vdda_hdmi hdmiphy pdy ae12 hdmi1_data1x hdmi1_data1x 0 o 1.8 vdda_hdmi hdmiphy pdy ad13 hdmi1_data1y hdmi1_data1y 0 o 1.8 vdda_hdmi hdmiphy pdy ae14 hdmi1_data2x hdmi1_data2x 0 o 1.8 vdda_hdmi hdmiphy pdy ad15 hdmi1_data2y hdmi1_data2y 0 o 1.8 vdda_hdmi hdmiphy pdy g22 i2c1_scl i2c1_scl 0 io 1.8/3.3 vddshv3 yes dual voltage lvcmos i2c pu/pd driver off 15 i g23 i2c1_sda i2c1_sda 0 io 1.8/3.3 vddshv3 yes dual voltage lvcmos i2c pu/pd driver off 15 i g21 i2c2_scl i2c2_scl 0 io 15 1.8/3.3 vddshv3 yes dual voltage lvcmos i2c pu/pd 1 hdmi1_ddc_sda 1 io driver off 15 i f23 i2c2_sda i2c2_sda 0 io 15 1.8/3.3 vddshv3 yes dual voltage lvcmos i2c pu/pd 1 hdmi1_ddc_scl 1 io driver off 15 i ab9 ljcb_clkn ljcb_clkn 0 io 1.8 vdda_pcie ljcb ac8 ljcb_clkp ljcb_clkp 0 io 1.8 vdda_pcie ljcb d16 mcasp1_aclkr mcasp1_aclkr 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_axr2 1 io 0 i2c4_sda 10 io 1 gpio5_0 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 30 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] c16 mcasp1_aclkx mcasp1_aclkx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 vin1a_fld0 7 i 0 i2c3_sda 10 io 1 pr2_mdio_mdclk no 11 o pr2_pru1_gpi7 no 12 i pr2_pru1_gpo7 no 13 o gpio7_31 14 io driver off 15 i d14 mcasp1_axr0 mcasp1_axr0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 uart6_rxd 3 i 1 vin1a_vsync0 7 i 0 i2c5_sda 10 io 1 pr2_mii0_rxer no 11 i 0 pr2_pru1_gpi8 no 12 i pr2_pru1_gpo8 no 13 o gpio5_2 14 io driver off 15 i b14 mcasp1_axr1 mcasp1_axr1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 uart6_txd 3 o vin1a_hsync0 7 i 0 i2c5_scl 10 io 1 pr2_mii_mt0_clk no 11 i 0 pr2_pru1_gpi9 no 12 i pr2_pru1_gpo9 no 13 o gpio5_3 14 io driver off 15 i c14 mcasp1_axr2 mcasp1_axr2 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_axr2 1 io 0 uart6_ctsn 3 i 1 gpio5_4 14 io driver off 15 i b15 mcasp1_axr3 mcasp1_axr3 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_axr3 1 io 0 uart6_rtsn 3 o gpio5_5 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 31 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] a15 mcasp1_axr4 mcasp1_axr4 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp4_axr2 1 io 0 gpio5_6 14 io driver off 15 i a14 mcasp1_axr5 mcasp1_axr5 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp4_axr3 1 io 0 gpio5_7 14 io driver off 15 i a17 mcasp1_axr6 mcasp1_axr6 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp5_axr2 1 io 0 gpio5_8 14 io driver off 15 i a16 mcasp1_axr7 mcasp1_axr7 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp5_axr3 1 io 0 timer4 10 io gpio5_9 14 io driver off 15 i a18 mcasp1_axr8 mcasp1_axr8 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_axr0 1 io 0 spi3_sclk 3 io 0 vin1a_d15 7 i 0 timer5 10 io pr2_mii0_txen no 11 o pr2_pru1_gpi10 no 12 i pr2_pru1_gpo10 no 13 o gpio5_10 14 io driver off 15 i b17 mcasp1_axr9 mcasp1_axr9 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_axr1 1 io 0 spi3_d1 3 io 0 vin1a_d14 7 i 0 timer6 10 io pr2_mii0_txd3 no 11 o pr2_pru1_gpi11 no 12 i pr2_pru1_gpo11 no 13 o gpio5_11 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 32 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b16 mcasp1_axr10 mcasp1_axr10 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_aclkx 1 io 0 mcasp6_aclkr 2 io spi3_d0 3 io 0 vin1a_d13 7 i 0 timer7 10 io pr2_mii0_txd2 no 11 o pr2_pru1_gpi12 no 12 i pr2_pru1_gpo12 no 13 o gpio5_12 14 io driver off 15 i b18 mcasp1_axr11 mcasp1_axr11 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp6_fsx 1 io 0 mcasp6_fsr 2 io spi3_cs0 3 io 1 vin1a_d12 7 i 0 timer8 10 io pr2_mii0_txd1 no 11 o pr2_pru1_gpi13 no 12 i pr2_pru1_gpo13 no 13 o gpio4_17 14 io driver off 15 i a19 mcasp1_axr12 mcasp1_axr12 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_axr0 1 io 0 spi3_cs1 3 io 1 vin1a_d11 7 i 0 timer9 10 io pr2_mii0_txd0 no 11 o pr2_pru1_gpi14 no 12 i pr2_pru1_gpo14 no 13 o gpio4_18 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 33 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] e17 mcasp1_axr13 mcasp1_axr13 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_axr1 1 io 0 vin1a_d10 7 i 0 timer10 10 io pr2_mii_mr0_clk no 11 i 0 pr2_pru1_gpi15 no 12 i pr2_pru1_gpo15 no 13 o gpio6_4 14 io driver off 15 i e16 mcasp1_axr14 mcasp1_axr14 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_aclkx 1 io 0 mcasp7_aclkr 2 io vin1a_d9 7 i 0 timer11 10 io pr2_mii0_rxdv no 11 i 0 pr2_pru1_gpi16 no 12 i pr2_pru1_gpo16 no 13 o gpio6_5 14 io driver off 15 i f16 mcasp1_axr15 mcasp1_axr15 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_fsx 1 io 0 mcasp7_fsr 2 io vin1a_d8 7 i 0 timer12 10 io pr2_mii0_rxd3 no 11 i 0 pr2_pru0_gpi20 no 12 i pr2_pru0_gpo20 no 13 o gpio6_6 14 io driver off 15 i d17 mcasp1_fsr mcasp1_fsr 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp7_axr3 1 io 0 i2c4_scl 10 io 1 gpio5_1 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 34 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] c17 mcasp1_fsx mcasp1_fsx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 vin1a_de0 7 i 0 i2c3_scl 10 io 1 pr2_mdio_data no 11 io 1 gpio7_30 14 io driver off 15 i e19 mcasp2_aclkx mcasp2_aclkx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 vin1a_d7 7 i 0 pr2_mii0_rxd2 no 11 i 0 pr2_pru0_gpi18 no 12 i pr2_pru0_gpo18 no 13 o driver off 15 i a20 mcasp2_axr0 mcasp2_axr0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 driver off 15 i b19 mcasp2_axr1 mcasp2_axr1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 driver off 15 i a21 mcasp2_axr2 mcasp2_axr2 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp3_axr2 1 io 0 vin1a_d5 7 i 0 pr2_mii0_rxd0 no 11 i 0 pr2_pru0_gpi16 no 12 i pr2_pru0_gpo16 no 13 o gpio6_8 14 io driver off 15 i b21 mcasp2_axr3 mcasp2_axr3 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp3_axr3 1 io 0 vin1a_d4 7 i 0 pr2_mii0_rxlink no 11 i 0 pr2_pru0_gpi17 no 12 i pr2_pru0_gpo17 no 13 o gpio6_9 14 io driver off 15 i b20 mcasp2_axr4 mcasp2_axr4 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp8_axr0 1 io 0 gpio1_4 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 35 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] c19 mcasp2_axr5 mcasp2_axr5 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp8_axr1 1 io 0 gpio6_7 14 io driver off 15 i d20 mcasp2_axr6 mcasp2_axr6 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp8_aclkx 1 io 0 mcasp8_aclkr 2 io gpio2_29 14 io driver off 15 i c20 mcasp2_axr7 mcasp2_axr7 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp8_fsx 1 io 0 mcasp8_fsr 2 io gpio1_5 14 io driver off 15 i d19 mcasp2_fsx mcasp2_fsx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 vin1a_d6 7 i 0 pr2_mii0_rxd1 no 11 i 0 pr2_pru0_gpi19 no 12 i pr2_pru0_gpo19 no 13 o driver off 15 i a22 mcasp3_aclkx mcasp3_aclkx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp3_aclkr 1 io mcasp2_axr12 2 io 0 uart7_rxd 3 i 1 vin1a_d3 7 i 0 pr2_mii0_crs no 11 i 0 pr2_pru0_gpi12 no 12 i pr2_pru0_gpo12 no 13 o gpio5_13 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 36 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b22 mcasp3_axr0 mcasp3_axr0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp2_axr14 2 io 0 uart7_ctsn 3 i 1 uart5_rxd 4 i 1 vin1a_d1 7 i 0 pr2_mii1_rxer no 11 i 0 pr2_pru0_gpi14 no 12 i pr2_pru0_gpo14 no 13 o driver off 15 i b23 mcasp3_axr1 mcasp3_axr1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp2_axr15 2 io 0 uart7_rtsn 3 o uart5_txd 4 o vin1a_d0 7 i 0 pr2_mii1_rxlink no 11 i 0 pr2_pru0_gpi15 no 12 i pr2_pru0_gpo15 no 13 o driver off 15 i a23 mcasp3_fsx mcasp3_fsx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp3_fsr 1 io mcasp2_axr13 2 io 0 uart7_txd 3 o vin1a_d2 7 i 0 pr2_mii0_col no 11 i 0 pr2_pru0_gpi13 no 12 i pr2_pru0_gpo13 no 13 o gpio5_14 14 io driver off 15 i c23 mcasp4_aclkx mcasp4_aclkx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp4_aclkr 1 io spi3_sclk 2 io 0 uart8_rxd 3 i 1 i2c4_sda 4 io 1 driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 37 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] a24 mcasp4_axr0 mcasp4_axr0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 spi3_d0 2 io 0 uart8_ctsn 3 i 1 uart4_rxd 4 i 1 i2c6_scl (10) 14 io driver off 15 i d23 mcasp4_axr1 mcasp4_axr1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 spi3_cs0 2 io 1 uart8_rtsn 3 o uart4_txd 4 o pr2_pru1_gpi0 no 12 i pr2_pru1_gpo0 no 13 o i2c6_sda (10) 14 io driver off 15 i b25 mcasp4_fsx mcasp4_fsx 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 mcasp4_fsr 1 io spi3_d1 2 io 0 uart8_txd 3 o i2c4_scl 4 io 1 driver off 15 i ac3 mcasp5_aclkx mcasp5_aclkx 0 io pd pd 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 0 mcasp5_aclkr 1 io spi4_sclk 2 io 0 uart9_rxd 3 i 1 i2c5_sda 4 io 1 mlb_clk 5 i 1 pr2_pru1_gpi1 no 12 i pr2_pru1_gpo1 no 13 o driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 38 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] aa5 mcasp5_axr0 mcasp5_axr0 0 io pd pd 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 0 spi4_d0 2 io 0 uart9_ctsn 3 i 1 uart3_rxd 4 i 1 mlb_sig 5 io 1 pr2_mdio_mdclk no 11 o pr2_pru1_gpi3 no 12 i pr2_pru1_gpo3 no 13 o driver off 15 i ac4 mcasp5_axr1 mcasp5_axr1 0 io pd pd 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 0 spi4_cs0 2 io 1 uart9_rtsn 3 o uart3_txd 4 o mlb_dat 5 io 1 pr2_mdio_data no 11 io 1 pr2_pru1_gpi4 no 12 i pr2_pru1_gpo4 no 13 o driver off 15 i u6 mcasp5_fsx mcasp5_fsx 0 io pd pd 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 0 mcasp5_fsr 1 io spi4_d1 2 io 0 uart9_txd 3 o i2c5_scl 4 io 1 pr2_pru1_gpi2 no 12 i pr2_pru1_gpo2 no 13 o driver off 15 i l6 mdio_d mdio_d 0 io pu pu 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 1 uart3_ctsn 1 i 1 mii0_txer 3 o 0 vin2a_d0 4 i 0 vin1b_d0 5 i 0 pr1_mii0_rxlink no 11 i 0 pr2_pru1_gpi1 no 12 i pr2_pru1_gpo1 no 13 o gpio5_16 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 39 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] l5 mdio_mclk mdio_mclk 0 o pu pu 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 1 uart3_rtsn 1 o mii0_col 3 i 0 vin2a_clk0 4 i vin1b_clk1 5 i 0 pr1_mii0_col no 11 i 0 pr2_pru1_gpi0 no 12 i pr2_pru1_gpo0 no 13 o gpio5_15 14 io driver off 15 i u1 mlbp_clk_n mlbp_clk_n 0 i vdds_mlbp no bmlb18 u2 mlbp_clk_p mlbp_clk_p 0 i vdds_mlbp no bmlb18 t1 mlbp_dat_n mlbp_dat_n 0 io off off vdds_mlbp no bmlb18 t2 mlbp_dat_p mlbp_dat_p 0 io off off vdds_mlbp no bmlb18 u4 mlbp_sig_n mlbp_sig_n 0 io off off vdds_mlbp no bmlb18 t3 mlbp_sig_p mlbp_sig_p 0 io off off vdds_mlbp no bmlb18 u3 mmc1_clk mmc1_clk 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_21 14 io driver off 15 i v4 mmc1_cmd mmc1_cmd 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_22 14 io driver off 15 i v3 mmc1_dat0 mmc1_dat0 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_23 14 io driver off 15 i v2 mmc1_dat1 mmc1_dat1 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_24 14 io driver off 15 i w1 mmc1_dat2 mmc1_dat2 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_25 14 io driver off 15 i v1 mmc1_dat3 mmc1_dat3 0 io pu pu 15 1.8/3.3 vddshv8 yes sdio2kv1 833 pux/pdy 1 gpio6_26 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 40 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] u5 mmc1_sdcd mmc1_sdcd 0 i pu pu 15 1.8/3.3 vddshv8 yes dual voltage lvcmos pu/pd 1 uart6_rxd 3 i 1 i2c4_sda 4 io 1 gpio6_27 14 io driver off 15 i v5 mmc1_sdwp mmc1_sdwp 0 i pd pd 15 1.8/3.3 vddshv8 yes dual voltage lvcmos pu/pd 0 uart6_txd 3 o i2c4_scl 4 io 1 gpio6_28 14 io driver off 15 i y2 mmc3_clk mmc3_clk 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 usb3_ulpi_d5 3 io 0 vin2b_d7 4 i 0 vin1a_d7 9 i 0 ehrpwm2_tripzone_input 10 io 0 pr2_mii1_txd3 no 11 o pr2_pru0_gpi2 no 12 i pr2_pru0_gpo2 no 13 o gpio6_29 14 io driver off 15 i y1 mmc3_cmd mmc3_cmd 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi3_sclk 1 io 0 usb3_ulpi_d4 3 io 0 vin2b_d6 4 i 0 vin1a_d6 9 i 0 ecap2_in_pwm2_out 10 io 0 pr2_mii1_txd2 no 11 o pr2_pru0_gpi3 no 12 i pr2_pru0_gpo3 no 13 o gpio6_30 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 41 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] y4 mmc3_dat0 mmc3_dat0 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi3_d1 1 io 0 uart5_rxd 2 i 1 usb3_ulpi_d3 3 io 0 vin2b_d5 4 i 0 vin1a_d5 9 i 0 eqep3a_in 10 i 0 pr2_mii1_txd1 no 11 o pr2_pru0_gpi4 no 12 i pr2_pru0_gpo4 no 13 o gpio6_31 14 io driver off 15 i aa2 mmc3_dat1 mmc3_dat1 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi3_d0 1 io 0 uart5_txd 2 o usb3_ulpi_d2 3 io 0 vin2b_d4 4 i 0 vin1a_d4 9 i 0 eqep3b_in 10 i 0 pr2_mii1_txd0 no 11 o pr2_pru0_gpi5 no 12 i pr2_pru0_gpo5 no 13 o gpio7_0 14 io driver off 15 i aa3 mmc3_dat2 mmc3_dat2 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi3_cs0 1 io 1 uart5_ctsn 2 i 1 usb3_ulpi_d1 3 io 0 vin2b_d3 4 i 0 vin1a_d3 9 i 0 eqep3_index 10 io 0 pr2_mii_mr1_clk no 11 i 0 pr2_pru0_gpi6 no 12 i pr2_pru0_gpo6 no 13 o gpio7_1 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 42 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] w2 mmc3_dat3 mmc3_dat3 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi3_cs1 1 io 1 uart5_rtsn 2 o usb3_ulpi_d0 3 io 0 vin2b_d2 4 i 0 vin1a_d2 9 i 0 eqep3_strobe 10 io 0 pr2_mii1_rxdv no 11 i 0 pr2_pru0_gpi7 no 12 i pr2_pru0_gpo7 no 13 o gpio7_2 14 io driver off 15 i y3 mmc3_dat4 mmc3_dat4 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi4_sclk 1 io 0 uart10_rxd 2 i 1 usb3_ulpi_nxt 3 i 0 vin2b_d1 4 i 0 vin1a_d1 9 i 0 ehrpwm3a 10 o pr2_mii1_rxd3 no 11 i 0 pr2_pru0_gpi8 no 12 i pr2_pru0_gpo8 no 13 o gpio1_22 14 io driver off 15 i aa1 mmc3_dat5 mmc3_dat5 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi4_d1 1 io 0 uart10_txd 2 o usb3_ulpi_dir 3 i 0 vin2b_d0 4 i 0 vin1a_d0 9 i 0 ehrpwm3b 10 o pr2_mii1_rxd2 no 11 i 0 pr2_pru0_gpi9 no 12 i pr2_pru0_gpo9 no 13 o gpio1_23 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 43 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] aa4 mmc3_dat6 mmc3_dat6 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi4_d0 1 io 0 uart10_ctsn 2 i 1 usb3_ulpi_stp 3 o vin2b_de1 4 i vin1a_hsync0 9 i 0 ehrpwm3_tripzone_input 10 io 0 pr2_mii1_rxd1 no 11 i 0 pr2_pru0_gpi10 no 12 i pr2_pru0_gpo10 no 13 o gpio1_24 14 io driver off 15 i ab1 mmc3_dat7 mmc3_dat7 0 io pu pu 15 1.8/3.3 vddshv7 yes dual voltage lvcmos pu/pd 1 spi4_cs0 1 io 1 uart10_rtsn 2 o usb3_ulpi_clk 3 i 0 vin2b_clk1 4 i vin1a_vsync0 9 i 0 ecap3_in_pwm3_out 10 io 0 pr2_mii1_rxd0 no 11 i 0 pr2_pru0_gpi11 no 12 i pr2_pru0_gpo11 no 13 o gpio1_25 14 io driver off 15 i l24 nmin_dsp nmin_dsp 0 i pd pd 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd ae6 pcie_rxn0 pcie_rxn0 0 i off off 1.8 vdda_pcie serdes ad7 pcie_rxp0 pcie_rxp0 0 i off off 1.8 vdda_pcie serdes ae8 pcie_txn0 pcie_txn0 0 o 1.8 vdda_pcie serdes ad9 pcie_txp0 pcie_txp0 0 o 1.8 vdda_pcie serdes f19 porz porz 0 i 1.8/3.3 vddshv3 yes ihhv1833 pu/pd k24 resetn resetn 0 i pu pu 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 44 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] n2 rgmii0_rxc rgmii0_rxc 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii1_txen 2 o mii0_txclk 3 i 0 vin2a_d5 4 i 0 vin1b_d5 5 i 0 usb3_ulpi_d2 6 io 0 pr1_mii_mt0_clk no 11 i 0 pr2_pru1_gpi11 no 12 i pr2_pru1_gpo11 no 13 o gpio5_26 14 io driver off 15 i p2 rgmii0_rxctl rgmii0_rxctl 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii1_txd1 2 o mii0_txd3 3 o vin2a_d6 4 i 0 vin1b_d6 5 i 0 usb3_ulpi_d3 6 io 0 pr1_mii0_txd3 no 11 o pr2_pru1_gpi12 no 12 i pr2_pru1_gpo12 no 13 o gpio5_27 14 io driver off 15 i n4 rgmii0_rxd0 rgmii0_rxd0 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii0_txd0 1 o mii0_txd0 3 o vin2a_fld0 4 i vin1b_fld1 5 i 0 usb3_ulpi_d7 6 io 0 pr1_mii0_txd0 no 11 o pr2_pru1_gpi16 no 12 i pr2_pru1_gpo16 no 13 o gpio5_31 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 45 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] n3 rgmii0_rxd1 rgmii0_rxd1 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii0_txd1 1 o mii0_txd1 3 o vin2a_d9 4 i 0 usb3_ulpi_d6 6 io 0 pr1_mii0_txd1 no 11 o pr2_pru1_gpi15 no 12 i pr2_pru1_gpo15 no 13 o gpio5_30 14 io driver off 15 i p1 rgmii0_rxd2 rgmii0_rxd2 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii0_txen 1 o mii0_txen 3 o vin2a_d8 4 i 0 usb3_ulpi_d5 6 io 0 pr1_mii0_txen no 11 o pr2_pru1_gpi14 no 12 i pr2_pru1_gpo14 no 13 o gpio5_29 14 io driver off 15 i n1 rgmii0_rxd3 rgmii0_rxd3 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 rmii1_txd0 2 o mii0_txd2 3 o vin2a_d7 4 i 0 vin1b_d7 5 i 0 usb3_ulpi_d4 6 io 0 pr1_mii0_txd2 no 11 o pr2_pru1_gpi13 no 12 i pr2_pru1_gpo13 no 13 o gpio5_28 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 46 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] t4 rgmii0_txc rgmii0_txc 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd uart3_ctsn 1 i 1 rmii1_rxd1 2 i 0 mii0_rxd3 3 i 0 vin2a_d3 4 i 0 vin1b_d3 5 i 0 usb3_ulpi_clk 6 i 0 spi3_d0 7 io 0 spi4_cs2 8 io 1 pr1_mii0_rxd3 no 11 i 0 pr2_pru1_gpi5 no 12 i pr2_pru1_gpo5 no 13 o gpio5_20 14 io driver off 15 i t5 rgmii0_txctl rgmii0_txctl 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd uart3_rtsn 1 o rmii1_rxd0 2 i 0 mii0_rxd2 3 i 0 vin2a_d4 4 i 0 vin1b_d4 5 i 0 usb3_ulpi_stp 6 o spi3_cs0 7 io 1 spi4_cs3 8 io 1 pr1_mii0_rxd2 no 11 i 0 pr2_pru1_gpi6 no 12 i pr2_pru1_gpo6 no 13 o gpio5_21 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 47 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] r1 rgmii0_txd0 rgmii0_txd0 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd rmii0_rxd0 1 i 0 mii0_rxd0 3 i 0 vin2a_d10 4 i 0 usb3_ulpi_d1 6 io 0 spi4_cs0 7 io 1 uart4_rtsn 8 o pr1_mii0_rxd0 no 11 i 0 pr2_pru1_gpi10 no 12 i pr2_pru1_gpo10 no 13 o gpio5_25 14 io driver off 15 i r2 rgmii0_txd1 rgmii0_txd1 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd rmii0_rxd1 1 i 0 mii0_rxd1 3 i 0 vin2a_vsync0 4 i vin1b_vsync1 5 i 0 usb3_ulpi_d0 6 io 0 spi4_d0 7 io 0 uart4_ctsn 8 io 1 pr1_mii0_rxd1 no 11 i 0 pr2_pru1_gpi9 no 12 i pr2_pru1_gpo9 no 13 o gpio5_24 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 48 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] p3 rgmii0_txd2 rgmii0_txd2 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd rmii0_rxer 1 i 0 mii0_rxer 3 i 0 vin2a_hsync0 4 i vin1b_hsync1 5 i 0 usb3_ulpi_nxt 6 i 0 spi4_d1 7 io 0 uart4_txd 8 o pr1_mii0_rxer no 11 i 0 pr2_pru1_gpi8 no 12 i pr2_pru1_gpo8 no 13 o gpio5_23 14 io driver off 15 i p4 rgmii0_txd3 rgmii0_txd3 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd rmii0_crs 1 i 0 mii0_crs 3 i 0 vin2a_de0 4 i vin1b_de1 5 i 0 usb3_ulpi_dir 6 i 0 spi4_sclk 7 io 0 uart4_rxd 8 i 1 pr1_mii0_crs no 11 i 0 pr2_pru1_gpi7 no 12 i pr2_pru1_gpo7 no 13 o gpio5_22 14 io driver off 15 i p5 rmii_mhz_50_clk rmii_mhz_50_clk 0 io pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 0 vin2a_d11 4 i 0 pr2_pru1_gpi2 no 12 i pr2_pru1_gpo2 no 13 o gpio5_17 14 io driver off 15 i e20 rstoutn rstoutn 0 o pd pd 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd k25 rtck rtck 0 o pu off 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd gpio8_29 14 io copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 49 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b24 spi1_cs0 spi1_cs0 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 gpio7_10 14 io driver off 15 i c25 spi1_cs1 spi1_cs1 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 spi2_cs1 3 io 1 gpio7_11 14 io driver off 15 i e24 spi1_cs2 spi1_cs2 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 uart4_rxd 1 i 1 mmc3_sdcd 2 i 1 spi2_cs2 3 io 1 dcan2_tx 4 io 1 mdio_mclk 5 o 1 hdmi1_hpd 6 io gpio7_12 14 io driver off 15 i e25 spi1_cs3 spi1_cs3 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 uart4_txd 1 o mmc3_sdwp 2 i 0 spi2_cs3 3 io 1 dcan2_rx 4 io 1 mdio_d 5 io 1 hdmi1_cec 6 io gpio7_13 14 io driver off 15 i d25 spi1_d0 spi1_d0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 gpio7_9 14 io driver off 15 i d24 spi1_d1 spi1_d1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 gpio7_8 14 io driver off 15 i c24 spi1_sclk spi1_sclk 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 gpio7_7 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 50 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] f24 spi2_cs0 spi2_cs0 0 io pu pu 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 1 uart3_rtsn 1 o uart5_txd 2 o gpio7_17 14 io driver off 15 i g24 spi2_d0 spi2_d0 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 uart3_ctsn 1 i 1 uart5_rxd 2 i 1 gpio7_16 14 io driver off 15 i f25 spi2_d1 spi2_d1 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 uart3_txd 1 o gpio7_15 14 io driver off 15 i g25 spi2_sclk spi2_sclk 0 io pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd 0 uart3_rxd 1 i 1 gpio7_14 14 io driver off 15 i k21 tclk tclk 0 i pu pu 0 1.8/3.3 vddshv3 yes iq1833 pu/pd l23 tdi tdi 0 i pu pu 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd gpio8_27 14 i j20 tdo tdo 0 o pu pu 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd gpio8_28 14 io l21 tms tms 0 i pu pu 0 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd l22 trstn trstn 0 i pd pd 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd l20 uart1_ctsn uart1_ctsn 0 i pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd 1 uart9_rxd 2 i 1 mmc4_clk 3 io 1 gpio7_24 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 51 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] m24 uart1_rtsn uart1_rtsn 0 o pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd uart9_txd 2 o mmc4_cmd 3 io 1 gpio7_25 14 io driver off 15 i l25 uart1_rxd uart1_rxd 0 i pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd 1 mmc4_sdcd 3 i 1 gpio7_22 14 io driver off 15 i m25 uart1_txd uart1_txd 0 o pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd mmc4_sdwp 3 i 0 gpio7_23 14 io driver off 15 i n22 uart2_ctsn uart2_ctsn 0 i pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd 1 uart3_rxd 2 i 1 mmc4_dat2 3 io 1 uart10_rxd 4 i 1 uart1_dtrn 5 o gpio1_16 14 io driver off 15 i n24 uart2_rtsn uart2_rtsn 0 o pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd uart3_txd 1 o uart3_irtx 2 o mmc4_dat3 3 io 1 uart10_txd 4 o uart1_rin 5 i 1 gpio1_17 14 io driver off 15 i n23 uart2_rxd uart2_rxd 0 i pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd 1 uart3_ctsn 1 i 1 uart3_rctx 2 o mmc4_dat0 3 io 1 uart2_rxd 4 i 1 uart1_dcdn 5 i 1 gpio7_26 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 52 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] n25 uart2_txd uart2_txd 0 o pu pu 15 1.8/3.3 vddshv4 yes dual voltage lvcmos pu/pd uart3_rtsn 1 o uart3_sd 2 o mmc4_dat1 3 io 1 uart2_txd 4 o uart1_dsrn 5 i 0 gpio7_27 14 io driver off 15 i n5 uart3_rxd uart3_rxd 0 i pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd 1 rmii1_crs 2 i 0 mii0_rxdv 3 i 0 vin2a_d1 4 i 0 vin1b_d1 5 i 0 spi3_sclk 7 io 0 pr1_mii0_rxdv no 11 i 0 pr2_pru1_gpi3 no 12 i pr2_pru1_gpo3 no 13 o gpio5_18 14 io driver off 15 i n6 uart3_txd uart3_txd 0 o pd pd 15 1.8/3.3 vddshv9 yes dual voltage lvcmos pu/pd rmii1_rxer 2 i 0 mii0_rxclk 3 i 0 vin2a_d2 4 i 0 vin1b_d2 5 i 0 spi3_d1 7 io 0 spi4_cs1 8 io 1 pr1_mii_mr0_clk no 11 i 0 pr2_pru1_gpi4 no 12 i pr2_pru1_gpo4 no 13 o gpio5_19 14 io driver off 15 i ab7 usb1_dm usb1_dm 0 io off off 3.3 vdda33v_u sb1 usbphy ac6 usb1_dp usb1_dp 0 io off off 3.3 vdda33v_u sb1 usbphy copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 53 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] ad3 usb1_drvvbus usb1_drvvbus 0 o pd pd 15 1.8/3.3 vdda33v_u sb2 yes dual voltage lvcmos pu/pd timer16 7 io gpio6_12 14 io driver off 15 i ac5 usb2_dm usb2_dm 0 io 3.3 vdda33v_u sb2 no usbphy ab6 usb2_dp usb2_dp 0 io 3.3 vdda33v_u sb2 no usbphy aa6 usb2_drvvbus usb2_drvvbus 0 o pd pd 15 1.8/3.3 vdda33v_u sb2 yes dual voltage lvcmos pu/pd timer15 7 io gpio6_13 14 io driver off 15 i ae5 usb_rxn0 usb_rxn0 0 i off off 1.8 vdda_usb1 serdes pcie_rxn1 1 i ad6 usb_rxp0 usb_rxp0 0 i off off 1.8 vdda_usb1 serdes pcie_rxp1 1 i ae3 usb_txn0 usb_txn0 0 o 1.8 vdda_usb1 serdes pcie_txn1 1 o ad4 usb_txp0 usb_txp0 0 o 1.8 vdda_usb1 serdes pcie_txp1 1 o j15, j16, j18, k12, k18, l12, l17, m11, m13, m15, m17, n11, n13, n15, n18, p10, p12, p14, p16, p18, r10, r12, r14, r16, r17, t11, t13, t15, t17, t9, u11, u13, u15, u18, u9, v10, v12, v14, v16, v18, w10, w12, w14, w16 vdd vdd pwr f20 vpp vpp (11) pwr aa10 vdda33v_usb1 vdda33v_usb1 pwr y10 vdda33v_usb2 vdda33v_usb2 pwr l9 vdda_core_gmac vdda_core_gmac pwr t6 vdda_csi vdda_csi pwr r20 vdda_ddr vdda_ddr pwr n10 vdda_debug vdda_debug pwr k10, l10 vdda_dsp_iva vdda_dsp_iva pwr n9 vdda_gpu vdda_gpu pwr copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 54 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] w15, y15 vdda_hdmi vdda_hdmi pwr k16, l16 vdda_mpu_abe vdda_mpu_abe pwr w13, y13 vdda_osc vdda_osc pwr w11, y11 vdda_pcie vdda_pcie pwr m10 vdda_per vdda_per pwr w8 vdda_usb1 vdda_usb1 pwr y8 vdda_usb2 vdda_usb2 pwr y9 vdda_usb3 vdda_usb3 pwr k14, l14 vdda_video vdda_video pwr g11, h20, w7, y18 vdds18v vdds18v pwr aa19, p20, y19 vdds18v_ddr1 vdds18v_ddr1 pwr g10, g9 vddshv1 vddshv1 pwr g15, g17, h15, h17, j19, k19 vddshv3 vddshv3 pwr m19, n19 vddshv4 vddshv4 pwr u7, u8 vddshv7 vddshv7 pwr n8, p8 vddshv8 vddshv8 pwr m7, n7 vddshv9 vddshv9 pwr j7, j8, k8 vddshv10 vddshv10 pwr f7, g7, h7 vddshv11 vddshv11 pwr t19, t20, v20, w17, w18, w20 vdds_ddr1 vdds_ddr1 pwr p7, r7 vdds_mlbp vdds_mlbp pwr h11, h13, h9, j11, j13, j9 vdd_dsp vdd_dsp pwr d8 vin2a_clk0 vin2a_clk0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd vout2_fld 4 o emu5 5 o kbd_row0 9 i 0 eqep1a_in 10 i 0 pr1_edio_data_in0 no 12 i 0 pr1_edio_data_out0 no 13 o gpio3_28 gpmc_a27 gpmc_a17 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 55 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] c8 vin2a_d0 vin2a_d0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d23 4 o emu10 5 o uart9_ctsn 7 i 1 spi4_d0 8 io 0 kbd_row4 9 i 0 ehrpwm1b 10 o pr1_uart0_rxd no 11 i 1 pr1_edio_data_in5 no 12 i 0 pr1_edio_data_out5 no 13 o gpio4_1 14 io driver off 15 i b9 vin2a_d1 vin2a_d1 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d22 4 o emu11 5 o uart9_rtsn 7 o spi4_cs0 8 io 1 kbd_row5 9 i 0 ehrpwm1_tripzone_input 10 io 0 pr1_uart0_txd no 11 o pr1_edio_data_in6 no 12 i 0 pr1_edio_data_out6 no 13 o gpio4_2 14 io driver off 15 i a7 vin2a_d2 vin2a_d2 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d21 4 o emu12 5 o uart10_rxd 8 i 1 kbd_row6 9 i 0 ecap1_in_pwm1_out 10 io 0 pr1_ecap0_ecap_capin_apwm_ o no 11 io 0 pr1_edio_data_in7 no 12 i 0 pr1_edio_data_out7 no 13 o gpio4_3 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 56 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] a9 vin2a_d3 vin2a_d3 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d20 4 o emu13 5 o uart10_txd 8 o kbd_col0 9 o ehrpwm1_synci 10 i 0 pr1_edc_latch0_in no 11 i 0 pr1_pru1_gpi0 no 12 i pr1_pru1_gpo0 no 13 o gpio4_4 14 io driver off 15 i a8 vin2a_d4 vin2a_d4 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d19 4 o emu14 5 o uart10_ctsn 8 i 1 kbd_col1 9 o ehrpwm1_synco 10 o pr1_edc_sync0_out no 11 o pr1_pru1_gpi1 no 12 i pr1_pru1_gpo1 no 13 o gpio4_5 14 io driver off 15 i a11 vin2a_d5 vin2a_d5 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d18 4 o emu15 5 o uart10_rtsn 8 o kbd_col2 9 o eqep2a_in 10 i 0 pr1_edio_sof no 11 o pr1_pru1_gpi2 no 12 i pr1_pru1_gpo2 no 13 o gpio4_6 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 57 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] f10 vin2a_d6 vin2a_d6 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d17 4 o emu16 5 o mii1_rxd1 8 i 0 kbd_col3 9 o eqep2b_in 10 i 0 pr1_mii_mt1_clk no 11 i 0 pr1_pru1_gpi3 no 12 i pr1_pru1_gpo3 no 13 o gpio4_7 14 io driver off 15 i a10 vin2a_d7 vin2a_d7 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d16 4 o emu17 5 o mii1_rxd2 8 i 0 kbd_col4 9 o eqep2_index 10 io 0 pr1_mii1_txen no 11 o pr1_pru1_gpi4 no 12 i pr1_pru1_gpo4 no 13 o gpio4_8 14 io driver off 15 i b10 vin2a_d8 vin2a_d8 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d15 4 o emu18 5 o mii1_rxd3 8 i 0 kbd_col5 9 o eqep2_strobe 10 io 0 pr1_mii1_txd3 no 11 o pr1_pru1_gpi5 no 12 i pr1_pru1_gpo5 no 13 o gpio4_9 gpmc_a26 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 58 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] e10 vin2a_d9 vin2a_d9 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vout2_d14 4 o emu19 5 o mii1_rxd0 8 i 0 kbd_col6 9 o ehrpwm2a 10 o pr1_mii1_txd2 no 11 o pr1_pru1_gpi6 no 12 i pr1_pru1_gpo6 no 13 o gpio4_10 gpmc_a25 14 io driver off 15 i d10 vin2a_d10 vin2a_d10 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 mdio_mclk 3 o 1 vout2_d13 4 o kbd_col7 9 o ehrpwm2b 10 o pr1_mdio_mdclk no 11 o pr1_pru1_gpi7 no 12 i pr1_pru1_gpo7 no 13 o gpio4_11 gpmc_a24 14 io driver off 15 i c10 vin2a_d11 vin2a_d11 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 mdio_d 3 io 1 vout2_d12 4 o kbd_row7 9 i 0 ehrpwm2_tripzone_input 10 io 0 pr1_mdio_data no 11 io 1 pr1_pru1_gpi8 no 12 i pr1_pru1_gpo8 no 13 o gpio4_12 gpmc_a23 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 59 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b11 vin2a_d12 vin2a_d12 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 rgmii1_txc 3 o vout2_d11 4 o mii1_rxclk 8 i 0 kbd_col8 9 o ecap2_in_pwm2_out 10 io 0 pr1_mii1_txd1 no 11 o pr1_pru1_gpi9 no 12 i pr1_pru1_gpo9 no 13 o gpio4_13 14 io driver off 15 i d11 vin2a_d13 vin2a_d13 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 rgmii1_txctl 3 o vout2_d10 4 o mii1_rxdv 8 i 0 kbd_row8 9 i 0 eqep3a_in 10 i 0 pr1_mii1_txd0 no 11 o pr1_pru1_gpi10 no 12 i pr1_pru1_gpo10 no 13 o gpio4_14 14 io driver off 15 i c11 vin2a_d14 vin2a_d14 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 rgmii1_txd3 3 o vout2_d9 4 o mii1_txclk 8 i 0 eqep3b_in 10 i 0 pr1_mii_mr1_clk no 11 i 0 pr1_pru1_gpi11 no 12 i pr1_pru1_gpo11 no 13 o gpio4_15 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 60 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b12 vin2a_d15 vin2a_d15 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 rgmii1_txd2 3 o vout2_d8 4 o mii1_txd0 8 o eqep3_index 10 io 0 pr1_mii1_rxdv no 11 i 0 pr1_pru1_gpi12 no 12 i pr1_pru1_gpo12 no 13 o gpio4_16 14 io driver off 15 i a12 vin2a_d16 vin2a_d16 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d7 2 i 0 rgmii1_txd1 3 o vout2_d7 4 o mii1_txd1 8 o eqep3_strobe 10 io 0 pr1_mii1_rxd3 no 11 i 0 pr1_pru1_gpi13 no 12 i pr1_pru1_gpo13 no 13 o gpio4_24 14 io driver off 15 i a13 vin2a_d17 vin2a_d17 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d6 2 i 0 rgmii1_txd0 3 o vout2_d6 4 o mii1_txd2 8 o ehrpwm3a 10 o pr1_mii1_rxd2 no 11 i 0 pr1_pru1_gpi14 no 12 i pr1_pru1_gpo14 no 13 o gpio4_25 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 61 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] e11 vin2a_d18 vin2a_d18 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d5 2 i 0 rgmii1_rxc 3 i 0 vout2_d5 4 o mii1_txd3 8 o ehrpwm3b 10 o pr1_mii1_rxd1 no 11 i 0 pr1_pru1_gpi15 no 12 i pr1_pru1_gpo15 no 13 o gpio4_26 14 io driver off 15 i f11 vin2a_d19 vin2a_d19 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d4 2 i 0 rgmii1_rxctl 3 i 0 vout2_d4 4 o mii1_txer 8 o 0 ehrpwm3_tripzone_input 10 io 0 pr1_mii1_rxd0 no 11 i 0 pr1_pru1_gpi16 no 12 i pr1_pru1_gpo16 no 13 o gpio4_27 14 io driver off 15 i b13 vin2a_d20 vin2a_d20 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d3 2 i 0 rgmii1_rxd3 3 i 0 vout2_d3 4 o mii1_rxer 8 i 0 ecap3_in_pwm3_out 10 io 0 pr1_mii1_rxer no 11 i 0 pr1_pru1_gpi17 no 12 i pr1_pru1_gpo17 no 13 o gpio4_28 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 62 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] e13 vin2a_d21 vin2a_d21 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d2 2 i 0 rgmii1_rxd2 3 i 0 vout2_d2 4 o mii1_col 8 i 0 pr1_mii1_rxlink no 11 i 0 pr1_pru1_gpi18 no 12 i pr1_pru1_gpo18 no 13 o gpio4_29 14 io driver off 15 i c13 vin2a_d22 vin2a_d22 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d1 2 i 0 rgmii1_rxd1 3 i 0 vout2_d1 4 o mii1_crs 8 i 0 pr1_mii1_col no 11 i 0 pr1_pru1_gpi19 no 12 i pr1_pru1_gpo19 no 13 o gpio4_30 14 io driver off 15 i d13 vin2a_d23 vin2a_d23 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd 0 vin2b_d0 2 i 0 rgmii1_rxd0 3 i 0 vout2_d0 4 o mii1_txen 8 o pr1_mii1_crs no 11 i 0 pr1_pru1_gpi20 no 12 i pr1_pru1_gpo20 no 13 o gpio4_31 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 63 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b7 vin2a_de0 vin2a_de0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd vin2a_fld0 1 i vin2b_fld1 2 i vin2b_de1 3 i vout2_de 4 o emu6 5 o kbd_row1 9 i 0 eqep1b_in 10 i 0 pr1_edio_data_in1 no 12 i 0 pr1_edio_data_out1 no 13 o gpio3_29 14 io driver off 15 i c7 vin2a_fld0 vin2a_fld0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd vin2b_clk1 2 i vout2_clk 4 o emu7 5 o eqep1_index 10 io 0 pr1_edio_data_in2 no 12 i 0 pr1_edio_data_out2 no 13 o gpio3_30 gpmc_a27 gpmc_a18 14 io driver off 15 i e8 vin2a_hsync0 vin2a_hsync0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd vin2b_hsync1 3 i vout2_hsync 4 o emu8 5 o uart9_rxd 7 i 1 spi4_sclk 8 io 0 kbd_row2 9 i 0 eqep1_strobe 10 io 0 pr1_uart0_cts_n no 11 i 1 pr1_edio_data_in3 no 12 i 0 pr1_edio_data_out3 no 13 o gpio3_31 gpmc_a27 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 64 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] b8 vin2a_vsync0 vin2a_vsync0 0 i pd pd 15 1.8/3.3 vddshv1 yes dual voltage lvcmos pu/pd vin2b_vsync1 3 i vout2_vsync 4 o emu9 5 o uart9_txd 7 o spi4_d1 8 io 0 kbd_row3 9 i 0 ehrpwm1a 10 o pr1_uart0_rts_n no 11 o pr1_edio_data_in4 no 12 i 0 pr1_edio_data_out4 no 13 o gpio4_0 14 io driver off 15 i a1, a25, aa13, aa15, aa7, aa8, aa9, ab8, ac13, ae1, ae15, ae25, g13, g16, g8, h10, h12, h14, h16, h18, h19, h8, j10, j12, j14, j17, k11, k13, k15, k17, k9, l11, l13, l15, l18, l8, m12, m14, m16, m18, m20, m8, m9, n12, n14, n16, n17, n20, p11, p13, p15, p17, p19, p9, r11, r13, r15, r18, r19, r8, r9, t10, t12, t14, t16, t18, t8, u10, u12, u14, u16, u17, u19, v11, v13, v15, v17, v19, v8, v9, w19, w9, y14, y16, y17, y7 vss vss gnd aa12 vssa_osc0 vssa_osc0 gnd ab11 vssa_osc1 vssa_osc1 gnd ac10 wakeup0 dcan1_rx 1 i 15 1.8/3.3 vdda33v_u sb1 yes ihhv1833 pu/pd 1 gpio1_0 sys_nirq2 14 i driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 65 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] ab10 wakeup3 sys_nirq1 1 i 15 1.8/3.3 vdda33v_u sb1 yes ihhv1833 pu/pd gpio1_3 dcan2_rx 14 i driver off 15 i y12 xi_osc0 xi_osc0 0 i 1.8 vdda_osc no lvcmos analog ac11 xi_osc1 xi_osc1 0 i 1.8 vdda_osc no lvcmos analog ab12 xo_osc0 xo_osc0 0 o 1.8 vdda_osc no lvcmos analog aa11 xo_osc1 xo_osc1 0 a 1.8 vdda_osc no lvcmos analog j25 xref_clk0 xref_clk0 0 i pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp2_axr8 1 io 0 mcasp1_axr4 2 io 0 mcasp1_ahclkx 3 o mcasp5_ahclkx 4 o atl_clk0 5 o vin1a_d0 7 i 0 hdq0 8 io 1 clkout2 9 o timer13 10 io pr2_mii1_col no 11 i 0 pr2_pru1_gpi5 no 12 i pr2_pru1_gpo5 no 13 o gpio6_17 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 66 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-1. pin attributes (1) (continued) ball number [1] ball name [2] signal name [3] support [4] muxmode [5] type [6] ball reset state [7] ball reset rel. state [8] ball reset rel. muxmode [9] i/o voltage value [10] power [11] hys [12] buffer type [13] pull up/down type [14] dsis [15] j24 xref_clk1 xref_clk1 0 i pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp2_axr9 1 io 0 mcasp1_axr5 2 io 0 mcasp2_ahclkx 3 o mcasp6_ahclkx 4 o atl_clk1 5 o vin1a_clk0 7 i 0 timer14 10 io pr2_mii1_crs no 11 i 0 pr2_pru1_gpi6 no 12 i pr2_pru1_gpo6 no 13 o gpio6_18 14 io driver off 15 i h24 xref_clk2 xref_clk2 0 i pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp2_axr10 1 io 0 mcasp1_axr6 2 io 0 mcasp3_ahclkx 3 o mcasp7_ahclkx 4 o atl_clk2 5 o timer15 10 io gpio6_19 14 io driver off 15 i h25 xref_clk3 xref_clk3 0 i pd pd 15 1.8/3.3 vddshv3 yes dual voltage lvcmos pu/pd mcasp2_axr11 1 io 0 mcasp1_axr7 2 io 0 mcasp4_ahclkx 3 o mcasp8_ahclkx 4 o atl_clk3 5 o hdq0 7 io 1 clkout3 9 o timer16 10 io gpio6_20 14 io driver off 15 i copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 67 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 (1) na in this table stands for not applicable. (2) for more information on recommended operating conditions, see section 5.4 , recommended operating conditions . (3) the pullup or pulldown block strength is equal to: minimum = 50 a, typical = 100 a, maximum = 250 a. (4) the output impedance settings of this io cell are programmable; by default, the value is ds[1:0] = 10, this means 40 ? . for more information on ds[1:0] register configuration, see the device trm. (5) io drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 ma, maximum 89 ma (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 v). (6) minimum pu = 900 , maximum pu = 3.090 k and minimum pd = 14.25 k , maximum pd = 24.8 k . for more information, see chapter 7 of the usb2.0 specification, in particular section signaling / device speed identification. (7) this function will not be supported on some pin-compatible roadmap devices. pin compatibility can be maintained in the future by not using these gpio signals. (8) in pux / pdy, x and y = 60 to 200 a. the output impedance settings (or drive strengths) of this io are programmable (34 , 40 , 48 , 60 , 80 ) depending on the values of the i[2:0] registers. (9) the internal pull resistors for balls a4, e7, d6, c5, d7, c6, a5, b6 are permanently disabled when sysboot15 is set to 0 as described in the section sysboot configuration of the device trm. if internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. if gpmc boot mode is used with sysboot15=0 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot. (10) i2c6 is not supported in ti standard software. i2c6 is not recommended for use to due to internal clock/reset dependencies on i2c1-5 and uart7. (11) this signal is valid only for high-security devices. for more details, see section 5.8 vpp specification for one-time programmable (otp) efuses . for general purpose devices do not connect any signal, test point, or board trace to this signal. copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 68 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com 4.3 signal descriptions many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. 1. signal name: the name of the signal passing through the pin. note the subsystem multiplexing signals are not described in table 4-1 and table 4-32 . 2. description: description of the signal 3. type: signal direction and type: ? i = input ? o = output ? io = input or output ? d = open drain ? ds = differential ? a = analog ? pwr = power ? gnd = ground 4. ball: associated ball(s) bottom note for more information, see the control module / control module register manual section of the device trm. 4.3.1 vip note for more information, see the video input port (vip) section of the device trm. table 4-2. vip signal descriptions signal name description type ball video input 1 vin1a_clk0 video input 1 port a clock input. input clock for 8-bit 16-bit or 24-bit port a video capture. input data is sampled on the clk0 edge. i g3 , j24 , y5 vin1a_d0 video input 1 port a data input i aa1 , b23 , f1 , j25 vin1a_d1 video input 1 port a data input i b22 , e2 , y3 vin1a_d2 video input 1 port a data input i a23 , e1 , w2 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 69 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-2. vip signal descriptions (continued) signal name description type ball vin1a_d3 video input 1 port a data input i a22 , aa3 , c1 vin1a_d4 video input 1 port a data input i aa2 , b21 , d1 vin1a_d5 video input 1 port a data input i a21 , d2 , y4 vin1a_d6 video input 1 port a data input i b1 , d19 , y1 vin1a_d7 video input 1 port a data input i b2 , e19 , y2 vin1a_d8 video input 1 port a data input i c2 , f16 vin1a_d9 video input 1 port a data input i d3 , e16 vin1a_d10 video input 1 port a data input i a2 , e17 vin1a_d11 video input 1 port a data input i a19 , b3 vin1a_d12 video input 1 port a data input i b18 , c3 vin1a_d13 video input 1 port a data input i b16 , c4 vin1a_d14 video input 1 port a data input i a3 , b17 vin1a_d15 video input 1 port a data input i a18 , b4 vin1a_d16 video input 1 port a data input i m1 vin1a_d17 video input 1 port a data input i m2 vin1a_d18 video input 1 port a data input i l2 vin1a_d19 video input 1 port a data input i l1 vin1a_d20 video input 1 port a data input i k3 vin1a_d21 video input 1 port a data input i k2 vin1a_d22 video input 1 port a data input i j1 vin1a_d23 video input 1 port a data input i k1 vin1a_de0 video input 1 port a field id input i c17 , j2 , y6 vin1a_fld0 video input 1 port a field id input i c16 , l3 vin1a_hsync0 video input 1 port a horizontal sync input i aa4 , b14 , k4 vin1a_vsync0 video input 1 port a vertical sync input i ab1 , d14 , h1 vin1b_clk1 video input 1 port b clock input i j2 , l5 vin1b_d0 video input 1 port b data input i l6 , m1 vin1b_d1 video input 1 port b data input i m2 , n5 vin1b_d2 video input 1 port b data input i l2 , n6 vin1b_d3 video input 1 port b data input i l1 , t4 vin1b_d4 video input 1 port b data input i k3 , t5 vin1b_d5 video input 1 port b data input i k2 , n2 vin1b_d6 video input 1 port b data input i j1 , p2 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 70 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-2. vip signal descriptions (continued) signal name description type ball vin1b_d7 video input 1 port b data input i k1 , n1 vin1b_de1 video input 1 port b field id input i l3 , p4 vin1b_fld1 video input 1 port b field id input i g1 , n4 vin1b_hsync1 video input 1 port b horizontal sync input i k4 , p3 vin1b_vsync1 video input 1 port b vertical sync input i h1 , r2 video input 2 vin2a_clk0 video input 2 port a clock input. i d8 , l5 vin2a_d0 video input 2 port a data input i c8 , l6 vin2a_d1 video input 2 port a data input i b9 , n5 vin2a_d2 video input 2 port a data input i a7 , n6 vin2a_d3 video input 2 port a data input i a9 , t4 vin2a_d4 video input 2 port a data input i a8 , t5 vin2a_d5 video input 2 port a data input i a11 , n2 vin2a_d6 video input 2 port a data input i f10 , p2 vin2a_d7 video input 2 port a data input i a10 , n1 vin2a_d8 video input 2 port a data input i b10 , p1 vin2a_d9 video input 2 port a data input i e10 , n3 vin2a_d10 video input 2 port a data input i d10 , r1 vin2a_d11 video input 2 port a data input i c10 , p5 vin2a_d12 video input 2 port a data input i b11 vin2a_d13 video input 2 port a data input i d11 vin2a_d14 video input 2 port a data input i c11 vin2a_d15 video input 2 port a data input i b12 vin2a_d16 video input 2 port a data input i a12 vin2a_d17 video input 2 port a data input i a13 vin2a_d18 video input 2 port a data input i e11 vin2a_d19 video input 2 port a data input i f11 vin2a_d20 video input 2 port a data input i b13 vin2a_d21 video input 2 port a data input i e13 vin2a_d22 video input 2 port a data input i c13 vin2a_d23 video input 2 port a data input i d13 vin2a_de0 video input 2 port a field id input i b7 , p4 vin2a_fld0 video input 2 port a field id input i b7 , c7 , n4 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 71 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-2. vip signal descriptions (continued) signal name description type ball vin2a_hsync0 video input 2 port a horizontal sync input i e8 , p3 vin2a_vsync0 video input 2 port a vertical sync input i b8 , r2 vin2b_clk1 video input 2 port b clock input i ab1 , c7 , l4 , h6 vin2b_d0 video input 2 port b data input i aa1 , d13 , a4 vin2b_d1 video input 2 port b data input i c13 , y3 , e7 vin2b_d2 video input 2 port b data input i e13 , w2 , d6 vin2b_d3 video input 2 port b data input i aa3 , b13 , c5 vin2b_d4 video input 2 port b data input i aa2 , f11 , b5 vin2b_d5 video input 2 port b data input i e11 , y4 , d7 vin2b_d6 video input 2 port b data input i a13 , y1 , c6 vin2b_d7 video input 2 port b data input i a12 , y2 , a5 vin2b_de1 video input 2 port b field id input i aa4 , b7 , h2 vin2b_fld1 video input 2 port b field id input i b7 , h6 vin2b_hsync1 video input 2 port b horizontal sync input i e8 , y5 , b6 vin2b_vsync1 video input 2 port b vertical sync input i b8 , y6 , a6 72 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4.3.2 dss table 4-3. dss signal descriptions signal name description type ball dpi video output 2 vout2_clk video output 2 clock output o c7 vout2_d0 video output 2 data output o d13 vout2_d1 video output 2 data output o c13 vout2_d2 video output 2 data output o e13 vout2_d3 video output 2 data output o b13 vout2_d4 video output 2 data output o f11 vout2_d5 video output 2 data output o e11 vout2_d6 video output 2 data output o a13 vout2_d7 video output 2 data output o a12 vout2_d8 video output 2 data output o b12 vout2_d9 video output 2 data output o c11 vout2_d10 video output 2 data output o d11 vout2_d11 video output 2 data output o b11 vout2_d12 video output 2 data output o c10 vout2_d13 video output 2 data output o d10 vout2_d14 video output 2 data output o e10 vout2_d15 video output 2 data output o b10 vout2_d16 video output 2 data output o a10 vout2_d17 video output 2 data output o f10 vout2_d18 video output 2 data output o a11 vout2_d19 video output 2 data output o a8 vout2_d20 video output 2 data output o a9 vout2_d21 video output 2 data output o a7 vout2_d22 video output 2 data output o b9 vout2_d23 video output 2 data output o c8 vout2_de video output 2 data enable output o b7 vout2_fld video output 2 field id output. this signal is not used for embedded sync modes. o d8 vout2_hsync video output 2 horizontal sync output. this signal is not used for embedded sync modes. o e8 vout2_vsync video output 2 vertical sync output. this signal is not used for embedded sync modes. o b8 dpi video output 3 vout3_clk video output 3 clock output o g3 vout3_d0 video output 3 data output o f1 vout3_d1 video output 3 data output o e2 vout3_d2 video output 3 data output o e1 vout3_d3 video output 3 data output o c1 vout3_d4 video output 3 data output o d1 vout3_d5 video output 3 data output o d2 vout3_d6 video output 3 data output o b1 vout3_d7 video output 3 data output o b2 vout3_d8 video output 3 data output o c2 vout3_d9 video output 3 data output o d3 vout3_d10 video output 3 data output o a2 vout3_d11 video output 3 data output o b3 73 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-3. dss signal descriptions (continued) signal name description type ball vout3_d12 video output 3 data output o c3 vout3_d13 video output 3 data output o c4 vout3_d14 video output 3 data output o a3 vout3_d15 video output 3 data output o b4 vout3_d16 video output 3 data output o m1 vout3_d17 video output 3 data output o m2 vout3_d18 video output 3 data output o l2 vout3_d19 video output 3 data output o l1 vout3_d20 video output 3 data output o k3 vout3_d21 video output 3 data output o k2 vout3_d22 video output 3 data output o j1 vout3_d23 video output 3 data output o k1 vout3_de video output 3 data enable output o j2 vout3_fld video output 3 field id output. this signal is not used for embedded sync modes. o l3 vout3_hsync video output 3 horizontal sync output. this signal is not used for embedded sync modes. o k4 vout3_vsync video output 3 vertical sync output. this signal is not used for embedded sync modes. o h1 4.3.3 hdmi note for more information, see the display subsystem / display subsystem overview of the device trm. table 4-4. hdmi signal descriptions signal name description type ball hdmi1_cec hdmi consumer electronic control iod e25 , h23 hdmi1_hpd hdmi display hot plug detect io e24 , h22 hdmi1_ddc_scl hdmi display data channel clock iod f23 hdmi1_ddc_sda hdmi display data channel data iod g21 hdmi1_clockx hdmi clock differential positive or negative ods ae9 hdmi1_clocky hdmi clock differential positive or negative ods ad10 hdmi1_data2x hdmi data 2 differential positive or negative ods ae14 hdmi1_data2y hdmi data 2 differential positive or negative ods ad15 hdmi1_data1x hdmi data 1 differential positive or negative ods ae12 hdmi1_data1y hdmi data 1 differential positive or negative ods ad13 hdmi1_data0x hdmi data 0 differential positive or negative ods ae11 hdmi1_data0y hdmi data 0 differential positive or negative ods ad12 4.3.4 csi2 note for more information, see the cal subsystem / cal subsystem overview of the device trm. 74 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-5. csi 2 signal descriptions signal name description type ball csi2_0_dx0 serial data/clock input - line 0 (position 1) i ac1 csi2_0_dy0 serial data/clock input - line 0 (position 1) i ab2 csi2_0_dx1 serial data/clock input - line 1 (position 2) i ad1 csi2_0_dy1 serial data/clock input - line 1 (position 2) i ac2 csi2_0_dx2 serial data/clock input - line 2 (position 3) i ae2 csi2_0_dy2 serial data/clock input - line 2 (position 3) i ad2 4.3.5 emif note for more information, see the memory subsystem / emif controller section of the device trm. note the index number 1 which is part of the emif1 signal prefixes (ddr1_*) listed in table 4-6 , emif signal descriptions, column "signal name" not to be confused with ddr1 type of sdram memories. table 4-6. emif signal descriptions signal name description type ball ddr1_csn0 emif1 chip select 0 o ac19 ddr1_cke emif1 clock enable o ab18 ddr1_ck emif1 clock o ad21 ddr1_nck emif1 negative clock o ae21 ddr1_odt0 emif1 on-die termination for chip select 0 o ad18 ddr1_casn emif1 column address strobe o ad16 ddr1_rasn emif1 row address strobe o ad17 ddr1_wen emif1 write enable o ae18 ddr1_rst emif1 reset output (ddr3-sdram only) o ae17 ddr1_ba0 emif1 bank address o ae16 ddr1_ba1 emif1 bank address o aa16 ddr1_ba2 emif1 bank address o ab16 ddr1_a0 emif1 address bus o ac18 ddr1_a1 emif1 address bus o ae19 ddr1_a2 emif1 address bus o ad19 ddr1_a3 emif1 address bus o ab19 ddr1_a4 emif1 address bus o ad20 ddr1_a5 emif1 address bus o ae20 ddr1_a6 emif1 address bus o aa18 ddr1_a7 emif1 address bus o aa20 ddr1_a8 emif1 address bus o y21 ddr1_a9 emif1 address bus o ac20 ddr1_a10 emif1 address bus o aa21 ddr1_a11 emif1 address bus o ac21 ddr1_a12 emif1 address bus o ac22 ddr1_a13 emif1 address bus o ac15 75 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-6. emif signal descriptions (continued) signal name description type ball ddr1_a14 emif1 address bus o ab15 ddr1_a15 emif1 address bus o ac16 ddr1_d0 emif1 data bus io aa23 ddr1_d1 emif1 data bus io ac24 ddr1_d2 emif1 data bus io ab24 ddr1_d3 emif1 data bus io ad24 ddr1_d4 emif1 data bus io ab23 ddr1_d5 emif1 data bus io ac23 ddr1_d6 emif1 data bus io ad23 ddr1_d7 emif1 data bus io ae24 ddr1_d8 emif1 data bus io aa24 ddr1_d9 emif1 data bus io w25 ddr1_d10 emif1 data bus io y23 ddr1_d11 emif1 data bus io ad25 ddr1_d12 emif1 data bus io ac25 ddr1_d13 emif1 data bus io ab25 ddr1_d14 emif1 data bus io aa25 ddr1_d15 emif1 data bus io w24 ddr1_d16 emif1 data bus io w23 ddr1_d17 emif1 data bus io u25 ddr1_d18 emif1 data bus io u24 ddr1_d19 emif1 data bus io w21 ddr1_d20 emif1 data bus io t22 ddr1_d21 emif1 data bus io u22 ddr1_d22 emif1 data bus io u23 ddr1_d23 emif1 data bus io t21 ddr1_d24 emif1 data bus io t23 ddr1_d25 emif1 data bus io t25 ddr1_d26 emif1 data bus io t24 ddr1_d27 emif1 data bus io p21 ddr1_d28 emif1 data bus io n21 ddr1_d29 emif1 data bus io p22 ddr1_d30 emif1 data bus io p23 ddr1_d31 emif1 data bus io p24 ddr1_dqm0 emif1 data mask o ae23 ddr1_dqm1 emif1 data mask o w22 ddr1_dqm2 emif1 data mask o u21 ddr1_dqm3 emif1 data mask o p25 ddr1_dqs0 data strobe 0 input/output for byte 0 of the 32-bit data bus. this signal is output to the emif1 memory when writing and input when reading. io ad22 ddr1_dqsn0 data strobe 0 invert io ae22 ddr1_dqs1 data strobe 1 input/output for byte 1 of the 32-bit data bus. this signal is output to the emif1 memory when writing and input when reading. io y24 ddr1_dqsn1 data strobe 1 invert io y25 ddr1_dqs2 data strobe 2 input/output for byte 2 of the 32-bit data bus. this signal is output to the emif1 memory when writing and input when reading. io v24 ddr1_dqsn2 data strobe 2 invert io v25 76 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-6. emif signal descriptions (continued) signal name description type ball ddr1_dqs3 data strobe 3 input/output for byte 3 of the 32-bit data bus. this signal is output to the emif1 memory when writing and input when reading. io r24 ddr1_dqsn3 data strobe 3 invert io r25 ddr1_vref0 reference power supply emif1 a y20 4.3.6 gpmc note for more information, see the memory subsystem / general-purpose memory controller section of the device trm. table 4-7. gpmc signal descriptions signal name description type ball gpmc_ad0 gpmc data 0 in a/d nonmultiplexed mode and additionally address 1 in a/d multiplexed mode io f1 gpmc_ad1 gpmc data 1 in a/d nonmultiplexed mode and additionally address 2 in a/d multiplexed mode io e2 gpmc_ad2 gpmc data 2 in a/d nonmultiplexed mode and additionally address 3 in a/d multiplexed mode io e1 gpmc_ad3 gpmc data 3 in a/d nonmultiplexed mode and additionally address 4 in a/d multiplexed mode io c1 gpmc_ad4 gpmc data 4 in a/d nonmultiplexed mode and additionally address 5 in a/d multiplexed mode io d1 gpmc_ad5 gpmc data 5 in a/d nonmultiplexed mode and additionally address 6 in a/d multiplexed mode io d2 gpmc_ad6 gpmc data 6 in a/d nonmultiplexed mode and additionally address 7 in a/d multiplexed mode io b1 gpmc_ad7 gpmc data 7 in a/d nonmultiplexed mode and additionally address 8 in a/d multiplexed mode io b2 gpmc_ad8 gpmc data 8 in a/d nonmultiplexed mode and additionally address 9 in a/d multiplexed mode io c2 gpmc_ad9 gpmc data 9 in a/d nonmultiplexed mode and additionally address 10 in a/d multiplexed mode io d3 gpmc_ad10 gpmc data 10 in a/d nonmultiplexed mode and additionally address 11 in a/d multiplexed mode io a2 gpmc_ad11 gpmc data 11 in a/d nonmultiplexed mode and additionally address 12 in a/d multiplexed mode io b3 gpmc_ad12 gpmc data 12 in a/d nonmultiplexed mode and additionally address 13 in a/d multiplexed mode io c3 gpmc_ad13 gpmc data 13 in a/d nonmultiplexed mode and additionally address 14 in a/d multiplexed mode io c4 gpmc_ad14 gpmc data 14 in a/d nonmultiplexed mode and additionally address 15 in a/d multiplexed mode io a3 gpmc_ad15 gpmc data 15 in a/d nonmultiplexed mode and additionally address 16 in a/d multiplexed mode io b4 gpmc_a0 gpmc address 0. only used to effectively address 8-bit data nonmultiplexed memories o g1 , m1 gpmc_a1 gpmc address 1 in a/d nonmultiplexed mode and address 17 in a/d multiplexed mode o g3 , m2 gpmc_a2 gpmc address 2 in a/d nonmultiplexed mode and address 18 in a/d multiplexed mode o h5 , l2 gpmc_a3 gpmc address 3 in a/d nonmultiplexed mode and address 19 in a/d multiplexed mode o h6 , l1 77 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-7. gpmc signal descriptions (continued) signal name description type ball gpmc_a4 gpmc address 4 in a/d nonmultiplexed mode and address 20 in a/d multiplexed mode o k3 gpmc_a5 gpmc address 5 in a/d nonmultiplexed mode and address 21 in a/d multiplexed mode o k2 gpmc_a6 gpmc address 6 in a/d nonmultiplexed mode and address 22 in a/d multiplexed mode o j1 gpmc_a7 gpmc address 7 in a/d nonmultiplexed mode and address 23 in a/d multiplexed mode o k1 gpmc_a8 gpmc address 8 in a/d nonmultiplexed mode and address 24 in a/d multiplexed mode o k4 gpmc_a9 gpmc address 9 in a/d nonmultiplexed mode and address 25 in a/d multiplexed mode o h1 gpmc_a10 gpmc address 10 in a/d nonmultiplexed mode and address 26 in a/d multiplexed mode o j2 gpmc_a11 gpmc address 11 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o l3 gpmc_a12 gpmc address 12 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o g1 gpmc_a13 gpmc address 13 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o a4 , h3 , g4 gpmc_a14 gpmc address 14 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o e7 , h4 , g3 gpmc_a15 gpmc address 15 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o d6 , k6 , f6 gpmc_a16 gpmc address 16 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o c5 , k5 , m1 gpmc_a17 gpmc address 17 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o b5 , g2 , d8 gpmc_a18 gpmc address 18 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o d7 , f2 , c7 gpmc_a19 gpmc address 19 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o a4 (3) , c6 , h5 gpmc_a20 gpmc address 20 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o a5 , e7 (3) , l4 gpmc_a21 gpmc address 21 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o b6 , d6 (3) , h2 gpmc_a22 gpmc address 22 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o a6 , c5 (3) , h6 gpmc_a23 gpmc address 23 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o b5 , h5 , c10 , g4 gpmc_a24 gpmc address 24 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o d7 (3) , d10 , g3 gpmc_a25 gpmc address 25 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o c6 (3) , f6 , e10 gpmc_a26 gpmc address 26 in a/d nonmultiplexed mode and unused in a/d multiplexed mode o a5 (3) , m1 , b10 gpmc_a27 gpmc address 27 in a/d nonmultiplexed mode and address 27 in a/d multiplexed mode o b6 (3) , d8 , c7 , e8 gpmc_cs0 gpmc chip select 0 (active low) o f3 gpmc_cs1 gpmc chip select 1 (active low) o a6 gpmc_cs2 gpmc chip select 2 (active low) o g4 gpmc_cs3 gpmc chip select 3 (active low) o g3 gpmc_cs4 gpmc chip select 4 (active low) o h2 gpmc_cs5 gpmc chip select 5 (active low) o h6 gpmc_cs6 gpmc chip select 6 (active low) o h5 78 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-7. gpmc signal descriptions (continued) signal name description type ball gpmc_cs7 gpmc chip select 7 (active low) o l4 gpmc_clk (1) (2) gpmc clock output io l4 gpmc_advn_ale gpmc address valid active low or address latch enable o h5 gpmc_oen_ren gpmc output enable active low or read enable o g5 gpmc_wen gpmc write enable active low o g6 gpmc_ben0 gpmc lower-byte enable active low o h2 gpmc_ben1 gpmc upper-byte enable active low o h6 gpmc_wait0 gpmc external indication of wait 0 i f6 gpmc_wait1 gpmc external indication of wait 1 i h5 , l4 (1) this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. any nonmonotonicity in voltage that occurs at the pad loopback clock pin between v ih and v il must be less than v hys . (2) the gpio6_16.clkout1 signal can be used as an ? always-on ? alternative to gpmc_clk provided that the external device can support the associated timing. see table 5-48 gpmc/nor flash interface switching characteristics - synchronous mode - default and table 5-50 gpmc/nor flash interface switching characteristics - synchronous mode - alternate for timing information. (3) the internal pull resistors for balls a4, e7, d6, c5, d7, c6, a5, b6 are permanently disabled when sysboot15 is set to 0 as described in the section sysboot configuration of the device trm. if internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. if gpmc boot mode is used with sysboot15=0 (not recommended) then external pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot. 4.3.7 timers note for more information, see the timers section of the device trm. table 4-8. timers signal descriptions signal name description type ball timer1 pwm output/event trigger input io h21 , h6 timer2 pwm output/event trigger input io h2 , k22 timer3 pwm output/event trigger input io h5 , k23 timer4 pwm output/event trigger input io a16 , l4 timer5 pwm output/event trigger input io a18 , k6 timer6 pwm output/event trigger input io b17 , h4 timer7 pwm output/event trigger input io b16 , h3 timer8 pwm output/event trigger input io b18 , g1 timer9 pwm output/event trigger input io a19 , l3 timer10 pwm output/event trigger input io e17 , j2 timer11 pwm output/event trigger input io e16 , h1 timer12 pwm output/event trigger input io f16 , k4 timer13 pwm output/event trigger input io j25 timer14 pwm output/event trigger input io j24 timer15 pwm output/event trigger input io aa6 , h24 timer16 pwm output/event trigger input io ad3 , h25 79 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4.3.8 i 2 c note for more information, see the serial communication interface / multimaster high-speed i2c controller / hs i2c environment / hs i2c in i2c mode section of the device trm. note i 2 c1 and i 2 c2 do not support hs-mode. table 4-9. i 2 c signal descriptions signal name description type ball inter-integrated circuit interface 1 (i2c1) i2c1_scl i2c1 clock iod g22 i2c1_sda i2c1 data iod g23 inter-integrated circuit interface 2 (i2c2) i2c2_scl i2c2 clock iod g21 i2c2_sda i2c2 data iod f23 inter-integrated circuit interface 3 (i2c3) i2c3_scl i2c3 clock iod c17 , k22 , l4 , y6 i2c3_sda i2c3 data iod c16 , h21 , h5 , y5 inter-integrated circuit interface 4 (i2c4) i2c4_scl i2c4 clock iod b25 , d17 , m1 , v5 i2c4_sda i2c4 data iod c23 , d16 , m2 , u5 inter-integrated circuit interface 5 (i2c5) i2c5_scl i2c5 clock iod b14 , k3 , u6 i2c5_sda i2c5 data iod ac3 , d14 , k2 inter-integrated circuit interface 6 (i2c6) i2c6_scl (1) i2c6 clock iod a24 i2c6_sda (1) i2c6 data iod d23 (1) i2c6 is not supported in ti standard software. i2c6 is not recommended for use to due to internal clock/reset dependencies on i2c1-5 and uart7. 4.3.9 hdq1w note for more information, see the serial communication interface / hdq/1-wire section of the device trm. table 4-10. hdq / 1-wire signal descriptions signal name description type ball hdq0 hdq or 1-wire protocol single interface pin iod h25 , j25 4.3.10 uart note for more information about uart booting, see the initialization / device initialization by rom code / perypheral booting / initialization phase for uart boot section of the device trm. 80 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-11. uart signal descriptions signal name description type ball universal asynchronous receiver/transmitter 1 (uart1) uart1_dcdn uart1 data carrier detect active low i n23 uart1_dsrn uart1 data set ready active low i n25 uart1_dtrn uart1 data terminal ready active low o n22 uart1_rin uart1 ring indicator i n24 uart1_rxd uart1 receive data i l25 uart1_txd uart1 transmit data o m25 uart1_ctsn uart1 clear to send active low i l20 uart1_rtsn uart1 request to send active low o m24 universal asynchronous receiver/transmitter 2 (uart2) uart2_rxd uart2 receive data i n23 uart2_txd uart2 transmit data o n25 uart2_ctsn uart2 clear to send active low i n22 uart2_rtsn uart2 request to send active low o n24 universal asynchronous receiver/transmitter 3 (uart3)/irda uart3_rxd uart3 receive data i aa5 , g25 , n22 , n5 uart3_txd uart3 transmit data o ac4 , f25 , n24 , n6 uart3_ctsn uart3 clear to send active low i g24 , l6 , n23 , t4 uart3_rtsn uart3 request to send active low o f24 , l5 , n25 , t5 uart3_rctx remote control data o n23 uart3_sd infrared transceiver configure/shutdown o n25 uart3_irtx infrared data output o n24 universal asynchronous receiver/transmitter 4 (uart4) uart4_rxd uart4 receive data i a24 , e24 , p4 uart4_txd uart4 transmit data o d23 , e25 , p3 uart4_ctsn uart4 clear to send active low i r2 uart4_rtsn uart4 request to send active low o r1 universal asynchronous receiver/transmitter 5 (uart5) uart5_rxd uart5 receive data i b22 , g24 , m1 , y4 uart5_txd uart5 transmit data o aa2 , b23 , f24 , m2 uart5_ctsn uart5 clear to send active low i aa3 , l2 uart5_rtsn uart5 request to send active low o l1 , w2 universal asynchronous receiver/transmitter 6 (uart6) uart6_rxd uart6 receive data i d14 , k3 , u5 uart6_txd uart6 transmit data o b14 , k2 , v5 uart6_ctsn uart6 clear to send active low i c14 , j1 uart6_rtsn uart6 request to send active low o b15 , k1 universal asynchronous receiver/transmitter 7 (uart7) uart7_rxd uart7 receive data i a22 , l2 uart7_txd uart7 transmit data o a23 , l1 uart7_ctsn uart7 clear to send active low i b22 uart7_rtsn uart7 request to send active low o b23 universal asynchronous receiver/transmitter 8 (uart8) uart8_rxd uart8 receive data i c23 , h22 , j1 uart8_txd uart8 transmit data o b25 , h23 , k1 uart8_ctsn uart8 clear to send active low i a24 uart8_rtsn uart8 request to send active low o d23 81 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-11. uart signal descriptions (continued) signal name description type ball universal asynchronous receiver/transmitter 9 (uart9) uart9_rxd uart9 receive data i ac3 , e8 , l20 uart9_txd uart9 transmit data o b8 , m24 , u6 uart9_ctsn uart9 clear to send active low i aa5 , c8 uart9_rtsn uart9 request to send active low o ac4 , b9 universal asynchronous receiver/transmitter 10 (uart10) uart10_rxd uart10 receive data i a7 , h21 , n22 , y3 uart10_txd uart10 transmit data o a9 , aa1 , k22 , n24 uart10_ctsn uart10 clear to send active low i a8 , aa4 uart10_rtsn uart10 request to send active low o a11 , ab1 4.3.11 mcspi note for more information, see the serial communication interface / multichannel serial peripheral interface (mcspi) section of the device trm. table 4-12. spi signal descriptions signal name description type ball serial peripheral interface 1 spi1_sclk (1) spi1 clock io c24 spi1_d1 spi1 data. can be configured as either miso or mosi. io d24 spi1_d0 spi1 data. can be configured as either miso or mosi. io d25 spi1_cs0 spi1 chip select io b24 spi1_cs1 spi1 chip select io c25 spi1_cs2 spi1 chip select io e24 spi1_cs3 spi1 chip select io e25 serial peripheral interface 2 spi2_sclk (1) spi2 clock io g25 spi2_d1 spi2 data. can be configured as either miso or mosi. io f25 spi2_d0 spi2 data. can be configured as either miso or mosi. io g24 spi2_cs0 spi2 chip select io f24 spi2_cs1 spi2 chip select io c25 spi2_cs2 spi2 chip select io e24 spi2_cs3 spi2 chip select io e25 serial peripheral interface 3 spi3_sclk (1) spi3 clock io a18 , c23 , n5 , y1 spi3_d1 spi3 data. can be configured as either miso or mosi. io b17 , b25 , n6 , y4 spi3_d0 spi3 data. can be configured as either miso or mosi. io a24 , aa2 , b16 , t4 spi3_cs0 spi3 chip select io aa3 , b18 , d23 , t5 spi3_cs1 spi3 chip select io a19 , w2 serial peripheral interface 4 spi4_sclk (1) spi4 clock io ac3 , e8 , k4 , p4 , y3 spi4_d1 spi4 data. can be configured as either miso or mosi. io aa1 , b8 , h1 , p3 , u6 spi4_d0 spi4 data. can be configured as either miso or mosi. io aa4 , aa5 , c8 , j2 , r2 82 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-12. spi signal descriptions (continued) signal name description type ball spi4_cs0 spi4 chip select io ab1 , ac4 , b9 , l3 , r1 spi4_cs1 spi4 chip select io g1 , n6 spi4_cs2 spi4 chip select io h3 , t4 spi4_cs3 spi4 chip select io h4 , t5 (1) this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. any nonmonotonicity in voltage that occurs at the pad loopback clock pin between v ih and v il must be less than v hys . 4.3.12 qspi note for more information about uart booting, see the initialization / device initialization by rom code / memory booting / spi/qspi flash devices section of the device trm. table 4-13. qspi signal descriptions signal name description type ball qspi1_sclk qspi1 serial clock io f2 qspi1_rtclk qspi1 return clock input. must be connected from qspi1_sclk on pcb. refer to pcb guidelines for qspi1 i h3 qspi1_d0 qspi1 data[0]. this pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. io k5 qspi1_d1 qspi1 data[1]. input read data in all modes. io g2 qspi1_d2 qspi1 data[2]. this pin is used only in quad read mode as input data pin during read phase io k6 qspi1_d3 qspi1 data[3]. this pin is used only in quad read mode as input data pin during read phase io h4 qspi1_cs0 qspi1 chip select[0]. this pin is used for qspi1 boot modes. io g4 qspi1_cs1 qspi1 chip select[1] o g3 qspi1_cs2 qspi1 chip select[2] o l1 qspi1_cs3 qspi1 chip select[3] o k3 4.3.13 mcasp note for more information, see the serial communication interface / multichannel audio serial port (mcasp) section of the device trm. table 4-14. mcasp signal descriptions signal name description type ball multichannel audio serial port 1 mcasp1_axr0 mcasp1 transmit/receive data io d14 mcasp1_axr1 mcasp1 transmit/receive data io b14 mcasp1_axr2 mcasp1 transmit/receive data io c14 mcasp1_axr3 mcasp1 transmit/receive data io b15 mcasp1_axr4 mcasp1 transmit/receive data io a15 , j25 mcasp1_axr5 mcasp1 transmit/receive data io a14 , j24 mcasp1_axr6 mcasp1 transmit/receive data io a17 , h24 mcasp1_axr7 mcasp1 transmit/receive data io a16 , h25 83 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-14. mcasp signal descriptions (continued) signal name description type ball mcasp1_axr8 mcasp1 transmit/receive data io a18 , h21 mcasp1_axr9 mcasp1 transmit/receive data io b17 , k22 mcasp1_axr10 mcasp1 transmit/receive data io b16 , k23 mcasp1_axr11 mcasp1 transmit/receive data io b18 mcasp1_axr12 mcasp1 transmit/receive data io a19 mcasp1_axr13 mcasp1 transmit/receive data io e17 mcasp1_axr14 mcasp1 transmit/receive data io e16 mcasp1_axr15 mcasp1 transmit/receive data io f16 mcasp1_fsx mcasp1 transmit frame sync io c17 mcasp1_aclkr (1) mcasp1 receive bit clock io d16 mcasp1_fsr mcasp1 receive frame sync io d17 mcasp1_ahclkx mcasp1 transmit high-frequency master clock o j25 mcasp1_aclkx (1) mcasp1 transmit bit clock io c16 multichannel audio serial port 2 mcasp2_axr0 mcasp2 transmit/receive data io a20 mcasp2_axr1 mcasp2 transmit/receive data io b19 mcasp2_axr2 mcasp2 transmit/receive data io a21 mcasp2_axr3 mcasp2 transmit/receive data io b21 mcasp2_axr4 mcasp2 transmit/receive data io b20 mcasp2_axr5 mcasp2 transmit/receive data io c19 mcasp2_axr6 mcasp2 transmit/receive data io d20 mcasp2_axr7 mcasp2 transmit/receive data io c20 mcasp2_axr8 mcasp2 transmit/receive data io j25 mcasp2_axr9 mcasp2 transmit/receive data io j24 mcasp2_axr10 mcasp2 transmit/receive data io h24 mcasp2_axr11 mcasp2 transmit/receive data io h25 mcasp2_axr12 mcasp2 transmit/receive data io a22 mcasp2_axr13 mcasp2 transmit/receive data io a23 mcasp2_axr14 mcasp2 transmit/receive data io b22 mcasp2_axr15 mcasp2 transmit/receive data io b23 mcasp2_fsx mcasp2 transmit frame sync io d19 mcasp2_ahclkx mcasp2 transmit high-frequency master clock o j24 mcasp2_aclkx (1) mcasp2 transmit bit clock io e19 multichannel audio serial port 3 mcasp3_axr0 mcasp3 transmit/receive data io b22 mcasp3_axr1 mcasp3 transmit/receive data io b23 mcasp3_axr2 mcasp3 transmit/receive data io a21 mcasp3_axr3 mcasp3 transmit/receive data io b21 mcasp3_fsx mcasp3 transmit frame sync io a23 mcasp3_ahclkx mcasp3 transmit high-frequency master clock o h24 mcasp3_aclkx (1) mcasp3 transmit bit clock io a22 mcasp3_aclkr (1) mcasp3 receive bit clock io a22 mcasp3_fsr mcasp3 receive frame sync io a23 multichannel audio serial port 4 mcasp4_axr0 mcasp4 transmit/receive data io a24 mcasp4_axr1 mcasp4 transmit/receive data io d23 mcasp4_axr2 mcasp4 transmit/receive data io a15 84 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-14. mcasp signal descriptions (continued) signal name description type ball mcasp4_axr3 mcasp4 transmit/receive data io a14 mcasp4_fsx mcasp4 transmit frame sync io b25 mcasp4_ahclkx mcasp4 transmit high-frequency master clock o h25 mcasp4_aclkx (1) mcasp4 transmit bit clock io c23 mcasp4_aclkr (1) mcasp4 receive bit clock io c23 mcasp4_fsr mcasp4 receive frame sync io b25 multichannel audio serial port 5 mcasp5_axr0 mcasp5 transmit/receive data io aa5 mcasp5_axr1 mcasp5 transmit/receive data io ac4 mcasp5_axr2 mcasp5 transmit/receive data io a17 mcasp5_axr3 mcasp5 transmit/receive data io a16 mcasp5_fsx mcasp5 transmit frame sync io u6 mcasp5_ahclkx mcasp5 transmit high-frequency master clock o j25 mcasp5_aclkx (1) mcasp5 transmit bit clock io ac3 mcasp5_aclkr (1) mcasp5 receive bit clock io ac3 mcasp5_fsr mcasp5 receive frame sync io u6 multichannel audio serial port 6 mcasp6_axr0 mcasp6 transmit/receive data io a18 mcasp6_axr1 mcasp6 transmit/receive data io b17 mcasp6_axr2 mcasp6 transmit/receive data io c14 mcasp6_axr3 mcasp6 transmit/receive data io b15 mcasp6_ahclkx mcasp6 transmit high-frequency master clock o j24 mcasp6_aclkx (1) mcasp6 transmit bit clock io b16 mcasp6_fsx mcasp6 transmit frame sync io b18 mcasp6_aclkr (1) mcasp6 receive bit clock io b16 mcasp6_fsr mcasp6 receive frame sync io b18 multichannel audio serial port 7 mcasp7_aclkr (1) mcasp7 receive bit clock i/o io e16 mcasp7_aclkx (1) mcasp7 transmit bit clock i/o io e16 mcasp7_ahclkx mcasp7 transmit high-frequency master clock o h24 mcasp7_axr0 mcasp7 transmit/receive data i/o io a19 mcasp7_axr1 mcasp7 transmit/receive data i/o io e17 mcasp7_axr2 mcasp7 transmit/receive data i/o io d16 mcasp7_axr3 mcasp7 transmit/receive data i/o io d17 mcasp7_fsr mcasp7 receive frame sync i/o io f16 mcasp7_fsx mcasp7 transmit frame sync i/o io f16 multichannel audio serial port 8 mcasp8_aclkr (1) mcasp8 receive bit clock i/o io d20 mcasp8_aclkx (1) mcasp8 transmit bit clock i/o io d20 mcasp8_ahclkx mcasp8 transmit high-frequency master clock i/o o h25 mcasp8_axr0 mcasp8 transmit/receive data i/o io b20 mcasp8_axr1 mcasp8 transmit/receive data i/o io c19 mcasp8_fsr mcasp8 receive frame sync i/o io c20 mcasp8_fsx mcasp8 transmit frame sync i/o io c20 85 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated (1) this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. any nonmonotonicity in voltage that occurs at the pad loopback clock pin between v ih and v il must be less than v hys . 4.3.14 usb note for more information, see: serial communication interface / superspeed usb drd subsystem section of the device trm. table 4-15. universal serial bus signal descriptions signal name description type ball universal serial bus 1 usb1_dm usb1 usb2.0 differential signal pair (negative) iods ab7 usb1_dp usb1 usb2.0 differential signal pair (positive) iods ac6 usb1_drvvbus usb1 drive vbus signal o ad3 usb_rxn0 (1) usb1 usb3.0 receiver negative lane ids ae5 usb_rxp0 (1) usb1 usb3.0 receiver positive lane ids ad6 usb_txn0 (1) usb1 usb3.0 transmitter negative lane ods ae3 usb_txp0 (1) usb1 usb3.0 transmitter positive lane ods ad4 universal serial bus 2 usb2_dm usb2 usb2.0 differential signal pair (negative) io ac5 usb2_dp usb2 usb2.0 differential signal pair (positive) io ab6 usb2_drvvbus usb2 drive vbus signal o aa6 universal serial bus 3 usb3_ulpi_d0 usb3 - ulpi 8-bit data bus iods r2 , w2 usb3_ulpi_d1 usb3 - ulpi 8-bit data bus iods aa3 , r1 usb3_ulpi_d2 usb3 - ulpi 8-bit data bus io aa2 , n2 usb3_ulpi_d3 usb3 - ulpi 8-bit data bus io p2 , y4 usb3_ulpi_d4 usb3 - ulpi 8-bit data bus io n1 , y1 usb3_ulpi_d5 usb3 - ulpi 8-bit data bus io p1 , y2 usb3_ulpi_d6 usb3 - ulpi 8-bit data bus io n3 , y6 usb3_ulpi_d7 usb3 - ulpi 8-bit data bus io n4 , y5 usb3_ulpi_nxt usb3 - ulpi next i p3 , y3 usb3_ulpi_dir usb3 - ulpi bus direction i aa1 , p4 usb3_ulpi_stp usb3 - ulpi stop o aa4 , t5 usb3_ulpi_clk usb3 - ulpi functional clock i ab1 , t4 (1) signals are enabled by selecting the correct field in the pcie_b1c0_mode_sel register. there are no ctrl_core_pad* register involved. 4.3.15 pcie note for more information, see the serial communication interfaces / pcie controllers and the shared phy component subsystems / pcie shared phy susbsytem sections of the device trm. table 4-16. pcie signal descriptions signal name description type ball pcie_rxn0 pcie1_phy_rx receive data lane 0 (negative) - mapped to pcie_ss1 only. ids ae6 86 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-16. pcie signal descriptions (continued) signal name description type ball pcie_rxp0 pcie1_phy_rx receive data lane 0 (positive) - mapped to pcie_ss1 only. ids ad7 pcie_txn0 pcie1_phy_tx transmit data lane 0 (negative) - mapped to pcie_ss1 only. ods ae8 pcie_txp0 pcie1_phy_tx transmit data lane 0 (positive) - mapped to pcie_ss1 only. ods ad9 pcie_rxn1 pcie2_phy_rx receive data lane 1 (negative) - mapped to either pcie_ss1 (dual lane- mode) or pcie_ss2 (single lane- mode) ids ae5 pcie_rxp1 pcie2_phy_rx receive data lane 1 (positive) - mapped to either pcie_ss1 (dual lane- mode) or pcie_ss2 (single lane- mode) ids ad6 pcie_txn1 pcie2_phy_tx transmit data lane 1 (negative) - mapped to either pcie_ss1 (dual lane- mode) or pcie_ss2 (single lane- mode) ods ae3 pcie_txp1 pcie2_phy_tx transmit data lane 1 (positive) - mapped to either pcie_ss1 (dual lane- mode) or pcie_ss2 (single lane- mode) ods ad4 ljcb_clkn pcie1_phy / pcie2_phy shared reference clock input / output differential pair (negative) iods ab9 ljcb_clkp pcie1_phy / pcie2_phy shared reference clock input / output differential pair (positive) iods ac8 4.3.16 dcan note for more information, see the serial communication interface / dcan section of the device trm. table 4-17. dcan signal descriptions signal name description type ball dcan 1 dcan1_rx dcan1 receive data pin io h23 , ac10 dcan1_tx dcan1 transmit data pin io h22 dcan 2 dcan2_rx dcan2 receive data pin io e25 , k22 , ab10 dcan2_tx dcan2 transmit data pin io e24 , h21 4.3.17 gmac_sw note for more information, see the serial communication interfaces / ethernet controller section of the device trm. table 4-18. gmac signal descriptions signal name description type ball rgmii0_rxc rgmii0 receive clock i n2 rgmii0_rxctl rgmii0 receive control i p2 rgmii0_rxd0 rgmii0 receive data i n4 rgmii0_rxd1 rgmii0 receive data i n3 rgmii0_rxd2 rgmii0 receive data i p1 rgmii0_rxd3 rgmii0 receive data i n1 rgmii0_txc rgmii0 transmit clock o t4 rgmii0_txctl rgmii0 transmit enable o t5 rgmii0_txd0 rgmii0 transmit data o r1 87 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-18. gmac signal descriptions (continued) signal name description type ball rgmii0_txd1 rgmii0 transmit data o r2 rgmii0_txd2 rgmii0 transmit data o p3 rgmii0_txd3 rgmii0 transmit data o p4 rgmii1_rxc rgmii1 receive clock i e11 rgmii1_rxctl rgmii1 receive control i f11 rgmii1_rxd0 rgmii1 receive data i d13 rgmii1_rxd1 rgmii1 receive data i c13 rgmii1_rxd2 rgmii1 receive data i e13 rgmii1_rxd3 rgmii1 receive data i b13 rgmii1_txc rgmii1 transmit clock o b11 rgmii1_txctl rgmii1 transmit enable o d11 rgmii1_txd0 rgmii1 transmit data o a13 rgmii1_txd1 rgmii1 transmit data o a12 rgmii1_txd2 rgmii1 transmit data o b12 rgmii1_txd3 rgmii1 transmit data o c11 mii1_col mii1 collision detect (sense) input i e13 mii1_crs mii1 carrier sense input i c13 mii1_rxclk mii1 receive clock i b11 mii1_rxd0 mii1 receive data i e10 mii1_rxd1 mii1 receive data i f10 mii1_rxd2 mii1 receive data i a10 mii1_rxd3 mii1 receive data i b10 mii1_rxdv mii1 receive data valid input i d11 mii1_rxer mii1 receive data error input i b13 mii1_txclk mii1 transmit clock i c11 mii1_txd0 mii1 transmit data o b12 mii1_txd1 mii1 transmit data o a12 mii1_txd2 mii1 transmit data o a13 mii1_txd3 mii1 transmit data o e11 mii1_txen mii1 transmit data enable output o d13 mii1_txer mii1 transmit error o f11 mii0_col mii0 collision detect (sense) input i l5 mii0_crs mii0 carrier sense input i p4 mii0_rxclk mii0 receive clock i n6 mii0_rxd0 mii0 receive data i r1 mii0_rxd1 mii0 receive data i r2 mii0_rxd2 mii0 receive data i t5 mii0_rxd3 mii0 receive data i t4 mii0_rxdv mii0 receive data valid input i n5 mii0_rxer mii0 receive data error input i p3 mii0_txclk mii0 transmit clock i n2 mii0_txd0 mii0 transmit data o n4 mii0_txd1 mii0 transmit data o n3 mii0_txd2 mii0 transmit data o n1 mii0_txd3 mii0 transmit data o p2 mii0_txen mii0 transmit data enable output o p1 mii0_txer mii0 transmit error o l6 88 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-18. gmac signal descriptions (continued) signal name description type ball rmii1_crs rmii1 carrier sense input i n5 rmii1_rxd0 rmii1 receive data i t5 rmii1_rxd1 rmii1 receive data i t4 rmii1_rxer rmii1 receive data error input i n6 rmii1_txd0 rmii1 transmit data o n1 rmii1_txd1 rmii1 transmit data o p2 rmii1_txen rmii1 transmit data enable output o n2 rmii0_crs rmii0 carrier sense input i p4 rmii0_rxd0 rmii0 receive data i r1 rmii0_rxd1 rmii0 receive data i r2 rmii0_rxer rmii0 receive data error input i p3 rmii0_txd0 rmii0 transmit data o n4 rmii0_txd1 rmii0 transmit data o n3 rmii0_txen rmii0 transmit data enable output o p1 mdio_mclk management data serial clock o d10 , e24 , l5 , y5 mdio_d management data io c10 , e25 , l6 , y6 4.3.18 mlb note mlb in 6-pin mode may require pull ups/ downs on sig and dat bus signals. for additional details, please consult the mlb bus interface specification. note for more information, see the serial communication interface / media local bus (mlb) section of the device trm. table 4-19. mlb signal descriptions signal name description type ball mlb_dat media local bus (mlb) subsystem data input and output io ac4 mlb_sig media local bus (mlb) subsystem signal input and output io aa5 mlb_clk media local bus (mlb) subsystem clock i ac3 mlbp_clk_n media local bus (mlb) subsystem clock differential pair (negative) ids u1 mlbp_clk_p media local bus (mlb) subsystem clock differential pair (positive) ids u2 mlbp_dat_n media local bus (mlb) subsystem data differential pair (negative) iods t1 mlbp_dat_p media local bus (mlb) subsystem data differential pair (positive) iods t2 mlbp_sig_n media local bus (mlb) subsystem signal differential pair (negative) iods u4 mlbp_sig_p media local bus (mlb) subsystem signal differential pair (positive) iods t3 4.3.19 emmc/sd/sdio note for more information, see the hs mmc/sdio section of the device trm. 89 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-20. emmc/sd/sdio signal descriptions signal name description type ball multi media card 1 mmc1_clk (1) mmc1 clock io u3 mmc1_cmd mmc1 command io v4 mmc1_dat0 mmc1 data bit 0 io v3 mmc1_dat1 mmc1 data bit 1 io v2 mmc1_dat2 mmc1 data bit 2 io w1 mmc1_dat3 mmc1 data bit 3 io v1 mmc1_sdcd mmc1 card detect i u5 mmc1_sdwp mmc1 write protect i v5 multi media card 2 mmc2_clk (1) mmc2 clock io b5 mmc2_cmd mmc2 command io a6 mmc2_dat0 mmc2 data bit 0 io d7 mmc2_dat1 mmc2 data bit 1 io c6 mmc2_dat2 mmc2 data bit 2 io a5 mmc2_dat3 mmc2 data bit 3 io b6 mmc2_dat4 mmc2 data bit 4 io a4 mmc2_dat5 mmc2 data bit 5 io e7 mmc2_dat6 mmc2 data bit 6 io d6 mmc2_dat7 mmc2 data bit 7 io c5 mmc2_sdcd mmc2 card detect i h22 mmc2_sdwp mmc2 write protect i h23 multi media card 3 mmc3_clk (1) mmc3 clock io y2 mmc3_cmd mmc3 command io y1 mmc3_dat0 mmc3 data bit 0 io y4 mmc3_dat1 mmc3 data bit 1 io aa2 mmc3_dat2 mmc3 data bit 2 io aa3 mmc3_dat3 mmc3 data bit 3 io w2 mmc3_dat4 mmc3 data bit 4 io y3 mmc3_dat5 mmc3 data bit 5 io aa1 mmc3_dat6 mmc3 data bit 6 io aa4 mmc3_dat7 mmc3 data bit 7 io ab1 mmc3_sdcd mmc3 card detect i e24 mmc3_sdwp mmc3 write protect i e25 multi media card 4 mmc4_clk (1) mmc4 clock io l20 mmc4_cmd mmc4 command io m24 mmc4_sdcd mmc4 card detect i l25 mmc4_sdwp mmc4 write protect i m25 mmc4_dat0 mmc4 data bit 0 io n23 mmc4_dat1 mmc4 data bit 1 io n25 mmc4_dat2 mmc4 data bit 2 io n22 mmc4_dat3 mmc4 data bit 3 io n24 90 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated (1) by default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal loopback clock' instead of the default 'pad loopback clock'. if the 'pad loopback clock' is used, series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. any nonmonotonicity in voltage that occurs at the pad loopback clock pin between v ih and v il must be less than v hys . 4.3.20 gpio note for more information, see the general-purpose interface section of the device trm. table 4-21. gpios signal descriptions signal name description type ball gpio 1 gpio1_0 general-purpose input i ac10 gpio1_3 general-purpose input i ab10 gpio1_4 general-purpose input/output io b20 gpio1_5 general-purpose input/output io c20 gpio1_6 general-purpose input/output io f1 gpio1_7 general-purpose input/output io e2 gpio1_8 general-purpose input/output io e1 gpio1_9 general-purpose input/output io c1 gpio1_10 general-purpose input/output io d1 gpio1_11 general-purpose input/output io d2 gpio1_12 general-purpose input/output io b1 gpio1_13 general-purpose input/output io b2 gpio1_14 general-purpose input/output io h22 gpio1_15 general-purpose input/output io h23 gpio1_16 general-purpose input/output io n22 gpio1_17 general-purpose input/output io n24 gpio1_18 general-purpose input/output io c3 gpio1_19 general-purpose input/output io c4 gpio1_20 general-purpose input/output io a3 gpio1_21 general-purpose input/output io b4 gpio1_22 general-purpose input/output io y3 gpio1_23 general-purpose input/output io aa1 gpio1_24 general-purpose input/output io aa4 gpio1_25 general-purpose input/output io ab1 gpio1_26 general-purpose input/output io k3 gpio1_27 general-purpose input/output io k2 gpio1_28 general-purpose input/output io j1 gpio1_29 general-purpose input/output io k1 gpio1_30 general-purpose input/output io k4 gpio1_31 general-purpose input/output io h1 gpio2 gpio2_0 general-purpose input/output io j2 gpio2_1 general-purpose input/output io l3 gpio2_2 general-purpose input/output io g1 gpio2_3 general-purpose input/output io h3 gpio2_4 general-purpose input/output io h4 91 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-21. gpios signal descriptions (continued) signal name description type ball gpio2_5 general-purpose input/output io k6 gpio2_6 general-purpose input/output io k5 gpio2_7 general-purpose input/output io g2 gpio2_8 general-purpose input/output io f2 gpio2_9 general-purpose input/output io a4 gpio2_10 general-purpose input/output io e7 gpio2_11 general-purpose input/output io d6 gpio2_12 general-purpose input/output io c5 gpio2_13 general-purpose input/output io b5 gpio2_14 general-purpose input/output io d7 gpio2_15 general-purpose input/output io c6 gpio2_16 general-purpose input/output io a5 gpio2_17 general-purpose input/output io b6 gpio2_18 general-purpose input/output io a6 gpio2_19 general-purpose input/output io f3 gpio2_20 general-purpose input/output io g4 gpio2_21 general-purpose input/output io g3 gpio2_22 general-purpose input/output io l4 gpio2_23 general-purpose input/output io h5 gpio2_24 general-purpose input/output io g5 gpio2_25 general-purpose input/output io g6 gpio2_26 general-purpose input/output io h2 gpio2_27 general-purpose input/output io h6 gpio2_28 general-purpose input/output io f6 gpio2_29 general-purpose input/output io d20 gpio 3 gpio3_28 general-purpose input/output io d8 gpio3_29 general-purpose input/output io b7 gpio3_30 general-purpose input/output io c7 gpio3_31 general-purpose input/output io e8 gpio 4 gpio4_0 general-purpose input/output io b8 gpio4_1 general-purpose input/output io c8 gpio4_2 general-purpose input/output io b9 gpio4_3 general-purpose input/output io a7 gpio4_4 general-purpose input/output io a9 gpio4_5 general-purpose input/output io a8 gpio4_6 general-purpose input/output io a11 gpio4_7 general-purpose input/output io f10 gpio4_8 general-purpose input/output io a10 gpio4_9 general-purpose input/output io b10 gpio4_10 general-purpose input/output io e10 gpio4_11 general-purpose input/output io d10 gpio4_12 general-purpose input/output io c10 gpio4_13 general-purpose input/output io b11 gpio4_14 general-purpose input/output io d11 gpio4_15 general-purpose input/output io c11 92 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-21. gpios signal descriptions (continued) signal name description type ball gpio4_16 general-purpose input/output io b12 gpio4_17 general-purpose input/output io b18 gpio4_18 general-purpose input/output io a19 gpio4_24 general-purpose input/output io a12 gpio4_25 general-purpose input/output io a13 gpio4_26 general-purpose input/output io e11 gpio4_27 general-purpose input/output io f11 gpio4_28 general-purpose input/output io b13 gpio4_29 general-purpose input/output io e13 gpio4_30 general-purpose input/output io c13 gpio4_31 general-purpose input/output io d13 gpio 5 gpio5_0 general-purpose input/output io d16 gpio5_1 general-purpose input/output io d17 gpio5_2 general-purpose input/output io d14 gpio5_3 general-purpose input/output io b14 gpio5_4 general-purpose input/output io c14 gpio5_5 general-purpose input/output io b15 gpio5_6 general-purpose input/output io a15 gpio5_7 general-purpose input/output io a14 gpio5_8 general-purpose input/output io a17 gpio5_9 general-purpose input/output io a16 gpio5_10 general-purpose input/output io a18 gpio5_11 general-purpose input/output io b17 gpio5_12 general-purpose input/output io b16 gpio5_13 general-purpose input/output io a22 gpio5_14 general-purpose input/output io a23 gpio5_15 general-purpose input/output io l5 gpio5_16 general-purpose input/output io l6 gpio5_17 general-purpose input/output io p5 gpio5_18 general-purpose input/output io n5 gpio5_19 general-purpose input/output io n6 gpio5_20 general-purpose input/output io t4 gpio5_21 general-purpose input/output io t5 gpio5_22 general-purpose input/output io p4 gpio5_23 general-purpose input/output io p3 gpio5_24 general-purpose input/output io r2 gpio5_25 general-purpose input/output io r1 gpio5_26 general-purpose input/output io n2 gpio5_27 general-purpose input/output io p2 gpio5_28 general-purpose input/output io n1 gpio5_29 general-purpose input/output io p1 gpio5_30 general-purpose input/output io n3 gpio5_31 general-purpose input/output io n4 gpio 6 gpio6_4 general-purpose input/output io e17 gpio6_5 general-purpose input/output io e16 93 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-21. gpios signal descriptions (continued) signal name description type ball gpio6_6 general-purpose input/output io f16 gpio6_7 general-purpose input/output io c19 gpio6_8 general-purpose input/output io a21 gpio6_9 general-purpose input/output io b21 gpio6_10 general-purpose input/output io y5 gpio6_11 general-purpose input/output io y6 gpio6_12 general-purpose input/output io ad3 gpio6_13 general-purpose input/output io aa6 gpio6_14 general-purpose input/output io h21 gpio6_15 general-purpose input/output io k22 gpio6_16 general-purpose input/output io k23 gpio6_17 general-purpose input/output io j25 gpio6_18 general-purpose input/output io j24 gpio6_19 general-purpose input/output io h24 gpio6_20 general-purpose input/output io h25 gpio6_21 general-purpose input/output io u3 gpio6_22 general-purpose input/output io v4 gpio6_23 general-purpose input/output io v3 gpio6_24 general-purpose input/output io v2 gpio6_25 general-purpose input/output io w1 gpio6_26 general-purpose input/output io v1 gpio6_27 general-purpose input/output io u5 gpio6_28 general-purpose input/output io v5 gpio6_29 general-purpose input/output io y2 gpio6_30 general-purpose input/output io y1 gpio6_31 general-purpose input/output io y4 gpio 7 gpio7_0 general-purpose input/output io aa2 gpio7_1 general-purpose input/output io aa3 gpio7_2 general-purpose input/output io w2 gpio7_3 general-purpose input/output io m1 gpio7_4 general-purpose input/output io m2 gpio7_5 general-purpose input/output io l2 gpio7_6 general-purpose input/output io l1 gpio7_7 general-purpose input/output io c24 gpio7_8 general-purpose input/output io d24 gpio7_9 general-purpose input/output io d25 gpio7_10 general-purpose input/output io b24 gpio7_11 general-purpose input/output io c25 gpio7_12 general-purpose input/output io e24 gpio7_13 general-purpose input/output io e25 gpio7_14 general-purpose input/output io g25 gpio7_15 general-purpose input/output io f25 gpio7_16 general-purpose input/output io g24 gpio7_17 general-purpose input/output io f24 gpio7_18 general-purpose input/output io c2 gpio7_19 general-purpose input/output io d3 94 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-21. gpios signal descriptions (continued) signal name description type ball gpio7_22 general-purpose input/output io l25 gpio7_23 general-purpose input/output io m25 gpio7_24 general-purpose input/output io l20 gpio7_25 general-purpose input/output io m24 gpio7_26 general-purpose input/output io n23 gpio7_27 general-purpose input/output io n25 gpio7_28 general-purpose input/output io a2 gpio7_29 general-purpose input/output io b3 gpio7_30 general-purpose input/output io c17 gpio7_31 general-purpose input/output io c16 gpio 8 gpio8_27 general-purpose input i l23 gpio8_28 general-purpose input/output io j20 gpio8_29 general-purpose input/output io k25 gpio8_30 general-purpose input/output io c21 gpio8_31 general-purpose input/output io c22 4.3.21 kbd note for more information, see keyboard controller section of the device trm. table 4-22. keyboard signal descriptions signal name description type ball kbd_row0 keypad row 0 i d8 kbd_row1 keypad row 1 i b7 kbd_row2 keypad row 2 i e8 kbd_row3 keypad row 3 i b8 kbd_row4 keypad row 4 i c8 kbd_row5 keypad row 5 i b9 kbd_row6 keypad row 6 i a7 kbd_row7 keypad row 7 i c10 kbd_row8 keypad row 8 i d11 kbd_col0 keypad column 0 o a9 kbd_col1 keypad column 1 o a8 kbd_col2 keypad column 2 o a11 kbd_col3 keypad column 3 o f10 kbd_col4 keypad column 4 o a10 kbd_col5 keypad column 5 o b10 kbd_col6 keypad column 6 o e10 kbd_col7 keypad column 7 o d10 kbd_col8 keypad column 8 o b11 95 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4.3.22 pwm note for more information, see the pulse-width modulation (pwm) ss section of the device trm. table 4-23. pwm signal descriptions signal name description type ball pwmss1 ecap1_in_pwm1_out ecap1 capture input / pwm output io a7 ehrpwm1_synci ehrpwm1 sync input i a9 ehrpwm1_synco ehrpwm1 sync output o a8 ehrpwm1_tripzone_in put ehrpwm1 trip zone input io b9 ehrpwm1a ehrpwm1 output a o b8 ehrpwm1b ehrpwm1 output b o c8 eqep1_index eqep1 index input io c7 eqep1_strobe eqep1 strobe input io e8 eqep1a_in eqep1 quadrature input a i d8 eqep1b_in eqep1 quadrature input b i b7 pwmss2 ecap2_in_pwm2_out ecap2 capture input / pwm output io b11 , y1 ehrpwm2_tripzone_in put ehrpwm2 trip zone input io c10 , y2 ehrpwm2a ehrpwm2 output a o e10 , y5 ehrpwm2b ehrpwm2 output b o d10 , y6 eqep2_index eqep2 index input io a10 eqep2_strobe eqep2 strobe input io b10 eqep2a_in eqep2 quadrature input a i a11 eqep2b_in eqep2 quadrature input b i f10 pwmss3 ecap3_in_pwm3_out ecap3 capture input / pwm output io ab1 , b13 ehrpwm3_tripzone_in put ehrpwm3 trip zone input io aa4 , f11 ehrpwm3a ehrpwm3 output a o a13 , y3 ehrpwm3b ehrpwm3 output b o aa1 , e11 eqep3_index eqep3 index input io aa3 , b12 eqep3_strobe eqep3 strobe input io a12 , w2 eqep3a_in eqep3 quadrature input a i d11 , y4 eqep3b_in eqep3 quadrature input b i aa2 , c11 4.3.23 pru-icss note for more information, see the serial communication interfaces / pcie controllers and the shared phy component subsystems / pcie shared phy susbsytem sections of the device trm. 96 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-24. pru-icss signal descriptions signal name description type ball pru-icss1 pr1_ecap0_ecap_capin _apwm_o capture input / pwm output io a7 pr1_edc_sync0_out sync 0 output o a8 pr1_edio_data_in0 ethernet digital input i d8 pr1_edio_data_in1 ethernet digital input i b7 pr1_edio_data_in2 ethernet digital input i c7 pr1_edio_data_in3 ethernet digital input i e8 pr1_edio_data_in4 ethernet digital input i b8 pr1_edio_data_in5 ethernet digital input i c8 pr1_edio_data_in6 ethernet digital input i b9 pr1_edio_data_in7 ethernet digital input i a7 pr1_edio_data_out0 ethernet digital output o d8 pr1_edio_data_out1 ethernet digital output o b7 pr1_edio_data_out2 ethernet digital output o c7 pr1_edio_data_out3 ethernet digital output o e8 pr1_edio_data_out4 ethernet digital output o b8 pr1_edio_data_out5 ethernet digital output o c8 pr1_edio_data_out6 ethernet digital output o b9 pr1_edio_data_out7 ethernet digital output o a7 pr1_edio_sof start of frame o a11 pr1_mdio_data mdio data io c10 pr1_mdio_mdclk mdio clock o d10 pr1_edc_latch0_in latch input 0 i a9 pr1_mii0_col mii0 collision detect i l5 pr1_mii0_crs mii0 carrier sense i p4 pr1_mii0_rxd0 mii0 receive data i r1 pr1_mii0_rxd1 mii0 receive data i r2 pr1_mii0_rxd2 mii0 receive data i t5 pr1_mii0_rxd3 mii0 receive data i t4 pr1_mii0_rxdv mii0 data valid i n5 pr1_mii0_rxer mii0 receive error i p3 pr1_mii0_rxlink mii0 receive link i l6 pr1_mii0_txd0 mii0 transmit data o n4 pr1_mii0_txd1 mii0 transmit data o n3 pr1_mii0_txd2 mii0 transmit data o n1 pr1_mii0_txd3 mii0 transmit data o p2 pr1_mii0_txen mii0 transmit enable o p1 pr1_mii1_col mii1 collision detect i c13 pr1_mii1_crs mii1 carrier sense i d13 pr1_mii1_rxd0 mii1 receive data i f11 pr1_mii1_rxd1 mii1 receive data i e11 pr1_mii1_rxd2 mii1 receive data i a13 pr1_mii1_rxd3 mii1 receive data i a12 pr1_mii1_rxdv mii1 data valid i b12 pr1_mii1_rxer mii1 receive error i b13 pr1_mii1_rxlink mii1 receive link i e13 97 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-24. pru-icss signal descriptions (continued) signal name description type ball pr1_mii1_txd0 mii1 transmit data o d11 pr1_mii1_txd1 mii1 transmit data o b11 pr1_mii1_txd2 mii1 transmit data o e10 pr1_mii1_txd3 mii1 transmit data o b10 pr1_mii1_txen mii1 transmit enable o a10 pr1_mii_mr0_clk mii0 master receive clock i n6 pr1_mii_mr1_clk mii1 master receive clock i c11 pr1_mii_mt0_clk mii0 master transmit clock i n2 pr1_mii_mt1_clk mii1 master transmit clock i f10 pr1_pru1_gpi0 pru1 general-purpose input i a9 pr1_pru1_gpi1 pru1 general-purpose input i a8 pr1_pru1_gpi2 pru1 general-purpose input i a11 pr1_pru1_gpi3 pru1 general-purpose input i f10 pr1_pru1_gpi4 pru1 general-purpose input i a10 pr1_pru1_gpi5 pru1 general-purpose input i b10 pr1_pru1_gpi6 pru1 general-purpose input i e10 pr1_pru1_gpi7 pru1 general-purpose input i d10 pr1_pru1_gpi8 pru1 general-purpose input i c10 pr1_pru1_gpi9 pru1 general-purpose input i b11 pr1_pru1_gpi10 pru1 general-purpose input i d11 pr1_pru1_gpi11 pru1 general-purpose input i c11 pr1_pru1_gpi12 pru1 general-purpose input i b12 pr1_pru1_gpi13 pru1 general-purpose input i a12 pr1_pru1_gpi14 pru1 general-purpose input i a13 pr1_pru1_gpi15 pru1 general-purpose input i e11 pr1_pru1_gpi16 pru1 general-purpose input i f11 pr1_pru1_gpi17 pru1 general-purpose input i b13 pr1_pru1_gpi18 pru1 general-purpose input i e13 pr1_pru1_gpi19 pru1 general-purpose input i c13 pr1_pru1_gpi20 pru1 general-purpose input i d13 pr1_pru1_gpo0 pru1 general-purpose output o a9 pr1_pru1_gpo1 pru1 general-purpose output o a8 pr1_pru1_gpo2 pru1 general-purpose output o a11 pr1_pru1_gpo3 pru1 general-purpose output o f10 pr1_pru1_gpo4 pru1 general-purpose output o a10 pr1_pru1_gpo5 pru1 general-purpose output o b10 pr1_pru1_gpo6 pru1 general-purpose output o e10 pr1_pru1_gpo7 pru1 general-purpose output o d10 pr1_pru1_gpo8 pru1 general-purpose output o c10 pr1_pru1_gpo9 pru1 general-purpose output o b11 pr1_pru1_gpo10 pru1 general-purpose output o d11 pr1_pru1_gpo11 pru1 general-purpose output o c11 pr1_pru1_gpo12 pru1 general-purpose output o b12 pr1_pru1_gpo13 pru1 general-purpose output o a12 pr1_pru1_gpo14 pru1 general-purpose output o a13 pr1_pru1_gpo15 pru1 general-purpose output o e11 pr1_pru1_gpo16 pru1 general-purpose output o f11 98 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-24. pru-icss signal descriptions (continued) signal name description type ball pr1_pru1_gpo17 pru1 general-purpose output o b13 pr1_pru1_gpo18 pru1 general-purpose output o e13 pr1_pru1_gpo19 pru1 general-purpose output o c13 pr1_pru1_gpo20 pru1 general-purpose output o d13 pr1_uart0_cts_n uart clear-to-send i e8 pr1_uart0_rts_n uart ready-to-send o b8 pr1_uart0_rxd uart receive data i c8 pr1_uart0_txd uart transmit data o b9 pru-icss 2 pr2_mdio_data mdio data io ac4 , c17 pr2_mdio_mdclk mdio clock o aa5 , c16 pr2_mii0_col mii0 collision detect i a23 pr2_mii0_crs mii0 carrier sense i a22 pr2_mii0_rxd0 mii0 receive data i a21 pr2_mii0_rxd1 mii0 receive data i d19 pr2_mii0_rxd2 mii0 receive data i e19 pr2_mii0_rxd3 mii0 receive data i f16 pr2_mii0_rxdv mii0 data valid i e16 pr2_mii0_rxer mii0 receive error i d14 pr2_mii0_rxlink mii0 receive link i b21 pr2_mii0_txd0 mii0 transmit data o a19 pr2_mii0_txd1 mii0 transmit data o b18 pr2_mii0_txd2 mii0 transmit data o b16 pr2_mii0_txd3 mii0 transmit data o b17 pr2_mii0_txen mii0 transmit enable o a18 pr2_mii1_col mii1 collision detect i j25 pr2_mii1_crs mii1 carrier sense i j24 pr2_mii1_rxd0 mii1 receive data i ab1 pr2_mii1_rxd1 mii1 receive data i aa4 pr2_mii1_rxd2 mii1 receive data i aa1 pr2_mii1_rxd3 mii1 receive data i y3 pr2_mii1_rxdv mii1 data valid i w2 pr2_mii1_rxer mii1 receive error i b22 pr2_mii1_rxlink mii1 receive link i b23 pr2_mii1_txd0 mii1 transmit data o aa2 pr2_mii1_txd1 mii1 transmit data o y4 pr2_mii1_txd2 mii1 transmit data o y1 pr2_mii1_txd3 mii1 transmit data o y2 pr2_mii1_txen mii1 transmit enable o y6 pr2_mii_mr0_clk mii0 master receive clock i e17 pr2_mii_mr1_clk mii1 master receive clock i aa3 pr2_mii_mt0_clk mii0 master transmit clock i b14 pr2_mii_mt1_clk mii1 master transmit clock i y5 pr2_pru0_gpi0 pru0 general-purpose input i y5 pr2_pru0_gpi1 pru0 general-purpose input i y6 pr2_pru0_gpi2 pru0 general-purpose input i y2 pr2_pru0_gpi3 pru0 general-purpose input i y1 99 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-24. pru-icss signal descriptions (continued) signal name description type ball pr2_pru0_gpi4 pru0 general-purpose input i y4 pr2_pru0_gpi5 pru0 general-purpose input i aa2 pr2_pru0_gpi6 pru0 general-purpose input i aa3 pr2_pru0_gpi7 pru0 general-purpose input i w2 pr2_pru0_gpi8 pru0 general-purpose input i y3 pr2_pru0_gpi9 pru0 general-purpose input i aa1 pr2_pru0_gpi10 pru0 general-purpose input i aa4 pr2_pru0_gpi11 pru0 general-purpose input i ab1 pr2_pru0_gpi12 pru0 general-purpose input i a22 pr2_pru0_gpi13 pru0 general-purpose input i a23 pr2_pru0_gpi14 pru0 general-purpose input i b22 pr2_pru0_gpi15 pru0 general-purpose input i b23 pr2_pru0_gpi16 pru0 general-purpose input i a21 pr2_pru0_gpi17 pru0 general-purpose input i b21 pr2_pru0_gpi18 pru0 general-purpose input i e19 pr2_pru0_gpi19 pru0 general-purpose input i d19 pr2_pru0_gpi20 pru0 general-purpose input i f16 pr2_pru0_gpo0 pru0 general-purpose output o y5 pr2_pru0_gpo1 pru0 general-purpose output o y6 pr2_pru0_gpo2 pru0 general-purpose output o y2 pr2_pru0_gpo3 pru0 general-purpose output o y1 pr2_pru0_gpo4 pru0 general-purpose output o y4 pr2_pru0_gpo5 pru0 general-purpose output o aa2 pr2_pru0_gpo6 pru0 general-purpose output o aa3 pr2_pru0_gpo7 pru0 general-purpose output o w2 pr2_pru0_gpo8 pru0 general-purpose output o y3 pr2_pru0_gpo9 pru0 general-purpose output o aa1 pr2_pru0_gpo10 pru0 general-purpose output o aa4 pr2_pru0_gpo11 pru0 general-purpose output o ab1 pr2_pru0_gpo12 pru0 general-purpose output o a22 pr2_pru0_gpo13 pru0 general-purpose output o a23 pr2_pru0_gpo14 pru0 general-purpose output o b22 pr2_pru0_gpo15 pru0 general-purpose output o b23 pr2_pru0_gpo16 pru0 general-purpose output o a21 pr2_pru0_gpo17 pru0 general-purpose output o b21 pr2_pru0_gpo18 pru0 general-purpose output o e19 pr2_pru0_gpo19 pru0 general-purpose output o d19 pr2_pru0_gpo20 pru0 general-purpose output o f16 pr2_pru1_gpi0 pru1 general-purpose input i d23 , l5 pr2_pru1_gpi1 pru1 general-purpose input i ac3 , l6 pr2_pru1_gpi2 pru1 general-purpose input i u6 , p5 pr2_pru1_gpi3 pru1 general-purpose input i aa5 , n5 pr2_pru1_gpi4 pru1 general-purpose input i ac4 , n6 pr2_pru1_gpi5 pru1 general-purpose input i j25 , t4 pr2_pru1_gpi6 pru1 general-purpose input i j24 , t5 pr2_pru1_gpi7 pru1 general-purpose input i c16 , p4 pr2_pru1_gpi8 pru1 general-purpose input i d14 , p3 100 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-24. pru-icss signal descriptions (continued) signal name description type ball pr2_pru1_gpi9 pru1 general-purpose input i b14 , r2 pr2_pru1_gpi10 pru1 general-purpose input i a18 , r1 pr2_pru1_gpi11 pru1 general-purpose input i b17 , n2 pr2_pru1_gpi12 pru1 general-purpose input i b16 , p2 pr2_pru1_gpi13 pru1 general-purpose input i b18 , n1 pr2_pru1_gpi14 pru1 general-purpose input i a19 , p1 pr2_pru1_gpi15 pru1 general-purpose input i e17 , n3 pr2_pru1_gpi16 pru1 general-purpose input i e16 , n4 pr2_pru1_gpo0 pru1 general-purpose output o d23 , l5 pr2_pru1_gpo1 pru1 general-purpose output o ac3 , l6 pr2_pru1_gpo2 pru1 general-purpose output o u6 , p5 pr2_pru1_gpo3 pru1 general-purpose output o aa5 , n5 pr2_pru1_gpo4 pru1 general-purpose output o ac4 , n6 pr2_pru1_gpo5 pru1 general-purpose output o j25 , t4 pr2_pru1_gpo6 pru1 general-purpose output o j24 , t5 pr2_pru1_gpo7 pru1 general-purpose output o c16 , p4 pr2_pru1_gpo8 pru1 general-purpose output o d14 , p3 pr2_pru1_gpo9 pru1 general-purpose output o b14 , r2 pr2_pru1_gpo10 pru1 general-purpose output o a18 , r1 pr2_pru1_gpo11 pru1 general-purpose output o b17 , n2 pr2_pru1_gpo12 pru1 general-purpose output o b16 , p2 pr2_pru1_gpo13 pru1 general-purpose output o b18 , n1 pr2_pru1_gpo14 pru1 general-purpose output o a19 , p1 pr2_pru1_gpo15 pru1 general-purpose output o e17 , n3 pr2_pru1_gpo16 pru1 general-purpose output o e16 , n4 4.3.24 atl note for more information, see the audio tracking logic (atl) section of the device trm. table 4-25. atl signal descriptions signal name description type ball atl_clk0 audio tracking logic clock 0 o j25 atl_clk1 audio tracking logic clock 1 o j24 atl_clk2 audio tracking logic clock 2 o h24 atl_clk3 audio tracking logic clock 3 o h25 4.3.25 emulation and debug subsystem note for more information, see the on-chip debug support / debug ports section of the device trm. 101 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-26. debug signal descriptions signal name description type ball tms jtag test port mode select. an external pullup resistor should be used on this ball. io l21 tdi jtag test data i l23 tdo jtag test port data o j20 tclk jtag test clock i k21 trstn jtag test reset i l22 rtck jtag return clock o k25 emu0 emulator pin 0 io c21 emu1 emulator pin 1 io c22 emu2 emulator pin 2 io e14 emu3 emulator pin 3 io f14 emu4 emulator pin 4 io f13 emu5 emulator pin 5 o d8 emu6 emulator pin 6 o b7 emu7 emulator pin 7 o c7 emu8 emulator pin 8 o e8 emu9 emulator pin 9 o b8 emu10 emulator pin 10 o c8 emu11 emulator pin 11 o b9 emu12 emulator pin 12 o a7 emu13 emulator pin 13 o a9 emu14 emulator pin 14 o a8 emu15 emulator pin 15 o a11 emu16 emulator pin 16 o f10 emu17 emulator pin 17 o a10 emu18 emulator pin 18 o b10 emu19 emulator pin 19 o e10 4.3.26 system and miscellaneous 4.3.26.1 sysboot note for more information, see the initialization (rom code) section of the device trm. table 4-27. sysboot signal descriptions signal name description type ball sysboot0 boot mode configuration 0. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i f1 sysboot1 boot mode configuration 1. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i e2 sysboot2 boot mode configuration 2. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i e1 sysboot3 boot mode configuration 3. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i c1 sysboot4 boot mode configuration 4. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i d1 sysboot5 boot mode configuration 5. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i d2 102 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-27. sysboot signal descriptions (continued) signal name description type ball sysboot6 boot mode configuration 6. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i b1 sysboot7 boot mode configuration 7. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i b2 sysboot8 boot mode configuration 8. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i c2 sysboot9 boot mode configuration 9. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i d3 sysboot10 boot mode configuration 10. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i a2 sysboot11 boot mode configuration 11. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i b3 sysboot12 boot mode configuration 12. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i c3 sysboot13 boot mode configuration 13. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i c4 sysboot14 boot mode configuration 14. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i a3 sysboot15 boot mode configuration 15. the value latched on this pin upon porz reset release will determine the boot mode configuration of the device. i b4 4.3.26.2 power, reset, and clock management (prcm) note for more information, see prcm section of the device trm. table 4-28. prcm signal descriptions signal name description type ball clkout1 device clock output 1. can be used externally for devices with non- critical timing requirements, or for debug, or as a reference clock on gpmc as described in table 5-48 gpmc/nor flash interface switching characteristics - synchronous mode - default and table 5- 50 gpmc/nor flash interface switching characteristics - synchronous mode - alternate . o k23 , l4 clkout2 device clock output 2. can be used externally for devices with non- critical timing requirements, or for debug. o h5 , j25 clkout3 device clock output 3. can be used xternally for devices with non- critical timing requirements, or for debug. o h25 porz power on reset (active low) input must be asserted low during a device power up sequence or cold reset state when all supplies are disabled. typically, an external pmic is the source and sets porz high after all supplies reach valid operating levels. asserting porz low puts the entire device in a safe reset state. i f19 resetn reset (active low) input ? s falling edge can trigger a device warm reset state from an external component. this signal should be high prior to or simultaneous with, porz rising. if the signal is not used in the system, resetn should be pulled high with an external pull-up resistor to vddshv3. i k24 rstoutn reset out (active low) output is asserted low whenever any global reset condition exists. after a brief delay, it will be set high upon removal of the internal global reset condition (i.e. porz, warm reset). it is only functional after its output buffer ? s reference voltage (vddshv3) is valid. if it is used as a reset for device peripheral components, then it should be and gated with porz to avoid the possibility of reset signal glitches during a power up sequence. (2) o e20 103 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-28. prcm signal descriptions (continued) signal name description type ball xi_osc0 system oscillator osc0 crystal input / lvcmos clock input. functions as the input connection to a crystal when the internal oscillator osc0 is used. functions as an lvcmos-compatible input clock when an external oscillator is used. i y12 xi_osc1 auxiliary oscillator osc1 crystal input / lvcmos clock input. functions as the input connection to a crystal when the internal oscillator osc1 is used. functions as an lvcmos-compatible input clock when an external oscillator is used i ac11 xo_osc0 system oscillator osc0 crystal output o ab12 xo_osc1 auxiliary oscillator osc1 crystal output o aa11 xref_clk0 external reference clock 0. for audio and other peripherals. i j25 xref_clk1 external reference clock 1. for audio and other peripherals. i j24 xref_clk2 external reference clock 2. for audio and other peripherals. i h24 xref_clk3 external reference clock 3. for audio and other peripherals. i h25 rmii_mhz_50_clk (1) rmii reference clock (50mhz). this pin is an input when external reference is used or output when internal reference is used. io p5 (1) this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. any nonmonotonicity in voltage that occurs at the pad loopback clock pin between v ih and v il must be less than v hys . (2) note that rstoutn is only valid after vddshv3 is valid. if the rstoutn signal will be used as a reset into other devices attached to the soc, it must be and'ed with porz. this will prevent glitches occurring during supply ramping being propagated. 4.3.26.3 system direct memory access (sdma) note for more information, see the dma controllers / system dma section of the device trm. table 4-29. sdma signal descriptions signal name description type ball dma_evt1 system dma event input 1 i g1 , l4 dma_evt2 system dma event input 2 i h3 , h5 dma_evt3 system dma event input 3 i h2 dma_evt4 system dma event input 4 i h6 4.3.26.4 interrupt controllers (intc) note for more information, see the interrupt controllers section of the device trm. table 4-30. intc signal descriptions signal name description type ball nmin_dsp non maskable interrupt input, active-low. this pin can be optionally routed to the dsp nmi input or as generic input to the arm cores. note that by default this pin has an internal pulldown resistor enabled. this internal pulldown should be disabled or countered by a stronger external pullup resistor before routing to the dsp or arm processors. i l24 sys_nirq2 external interrupt event to any device intc i ac10 sys_nirq1 external interrupt event to any device intc i ab10 104 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4.3.27 power supplies note for more information, see power, reset, and clock management / prcm subsystem environment / external voltage inputs section of the device trm. table 4-31. power supply signal descriptions signal name description type ball vdd core voltage domain supply pwr j15 , j16 , j18 , k12 , k18 , l12 , l17 , m11 , m13 , m15 , m17 , n11 , n13 , n15 , n18 , p10 , p12 , p14 , p16 , p18 , r10 , r12 , r14 , r16 , r17 , t11 , t13 , t15 , t17 , t9 , u11 , u13 , u15 , u18 , u9 , v10 , v12 , v14 , v16 , v18 , w10 , w12 , w14 , w16 vpp (2) efuse power supply pwr f20 vss ground gnd a1 , a25 , aa13 , aa15 , aa7 , aa8 , aa9 , ab8 , ac13 , ae1 , ae15 , ae25 , g13 , g16 , g8 , h10 , h12 , h14 , h16 , h18 , h19 , h8 , j10 , j12 , j14 , j17 , k11 , k13 , k15 , k17 , k9 , l11 , l13 , l15 , l18 , l8 , m12 , m14 , m16 , m18 , m20 , m8 , m9 , n12 , n14 , n16 , n17 , n20 , p11 , p13 , p15 , p17 , p19 , p9 , r11 , r13 , r15 , r18 , r19 , r8 , r9 , t10 , t12 , t14 , t16 , t18 , t8 , u10 , u12 , u14 , u16 , u17 , u19 , v11 , v13 , v15 , v17 , v19 , v8 , v9 , w19 , w9 , y14 , y16 , y17 , y7 cap_vbbldo_gpu (1) mm (sgx) back bias supply cap t7 cap_vbbldo_iva (1) iva back bias supply cap g14 cap_vbbldo_mpu (1) mpu back bias supply cap f17 cap_vbbldo_dsp (1) external capacitor connection for the dsp vbb ldo output cap f8 cap_vddram_core1 (1) sram array supply for core memories cap u20 cap_vddram_core3 (1) sram array supply for core memories cap k7 cap_vddram_core4 (1) sram array supply for core memories cap g19 cap_vddram_gpu (1) sram array supply for sgx (mm) memories cap v7 cap_vddram_iva (1) sram array supply for iva memories cap g12 cap_vddram_dsp (1) external capacitor connection for the dsp cap l7 cap_vddram_mpu (1) external capacitor connection for the mpu sram array ldo output cap g18 vdda33v_usb1 hs usb1 3p3 supply pwr aa10 vdda33v_usb2 hs usb1 3p3 supply pwr y10 vdda_core_gmac dpll_core and core hsdivider analog power supply pwr l9 vdda_csi csi interface 1.8v supply pwr t6 vdda_dsp_iva dsp pll and iva pll analog power supply pwr k10 , l10 vdda_mpu_abe mpu_abe pll analog power supply pwr k16 , l16 105 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated table 4-31. power supply signal descriptions (continued) signal name description type ball vdda_per dpll_abe, dpll_per, and per hsdivider analog power supply pwr m10 vdda_usb2 hs usb2 1.8v analog power supply pwr y8 vdds_mlbp mlbp io power supply pwr p7 , r7 vdd_dsp dsp voltage domain supply pwr h11 , h13 , h9 , j11 , j13 , j9 vdda_ddr ddr pll and ddr hsdivider analog power supply pwr r20 vdda_debug debug pll inside iosc pll supply pwr n10 vdda_gpu gpu (sgx) pll analog power supply pwr n9 vdda_hdmi hdmi pll and hdmi analog power supply pwr w15 , y15 vdda_osc hfosc - 1.8v vdds supply pwr w13 , y13 vdda_pcie pcie pll analog power supply pwr w11 , y11 vdda_usb1 usb2 pll analog power supply pwr w8 vdda_usb3 usb3 pll analog power supply pwr y9 vdda_video video1 and video2 pll analog power supply pwr k14 , l14 vdds18v 1.8v bump added for atestv esd supply pwr g11 , h20 , w7 , y18 vdds18v_ddr1 ddr2 - 1.8v bias supply pwr aa19 , p20 , y19 vddshv1 vin2 domain - 1.8/3.3 mode voltage power cell - secondary power supply pwr g10 , g9 vddshv3 general domain - 1.8/3.3 mode voltage power cell - secondary power supply pwr g15 , g17 , h15 , h17 , j19 , k19 vddshv4 mmc4 domain (uart4) - 1.8/3.3 mode voltage power cell - secondary power supply pwr m19 , n19 vddshv7 wifi power group (mmc3/mcasp5) - 1.8/3.3 mode voltage power cell - secondary power supply pwr u7 , u8 vddshv8 dual voltage (1.8v or 3.3v) power supply for the mmc1 power group pins pwr n8 , p8 vddshv9 rgmii - 1.8/3.3 mode voltage power cell - secondary power supply pwr m7 , n7 vddshv10 gpmc - 1.8/3.3 mode voltage power cell - secondary power supply pwr j7 , j8 , k8 vddshv11 mmc2 - 1.8/3.3 mode voltage power cell - secondary power supply pwr f7 , g7 , h7 vdds_ddr1 ddr2 - vdds2 can be 1.8 (ddr2)/1.5(ddr3) - secondary power supply pwr t19 , t20 , v20 , w17 , w18 , w20 vssa_osc0 osc0 analog ground gnd aa12 vssa_osc1 osc1 analog ground gnd ab11 (1) this pin must always be connected via a 1- f capacitor to vss. (2) this signal is valid only for high-security devices. for more details, see section 5.8 vpp specification for one-time programmable (otp) efuses . for general purpose devices do not connect any signal, test point, or board trace to this signal. copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 106 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com 4.4 pin multiplexing table 4-32 describes the device pin multiplexing (no characteristics are provided in this table). note table 4-32 , pin multiplexing doesn't take into account subsystem multiplexing signals. subsystem multiplexing signals are described in section 4.3 , signal descriptions . note for more information, see the control module / control module functional description / pad functional multiplexing and configuration section of the device trm. note configuring two pins to the same input signal is not supported as it can yield unexpected results. this can be easily prevented with the proper software configuration (hi-z mode is not an input signal). note when a pad is set into a pin multiplexing mode which is not defined, that pad ? s behavior is undefined. this should be avoided. note in some cases table 4-32 may present more than one signal per muxmode for the same ball. first signal in the list is the dominant function as selected via ctrl_core_pad_* register. all other signals are virtual functions that present alternate multiplexing options. this virtual functions are controlled via ctrl_core_alt_select_mux or ctrl_core_vip_mux_select register. for more information on how to use this options, please refer to device trm, chapter control module , section pad configuration registers. table 4-32. pin multiplexing address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 p25 ddr1_dqm3 y23 ddr1_d10 p21 ddr1_d27 t3 mlbp_sig_p u25 ddr1_d17 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 107 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 aa20 ddr1_a7 v25 ddr1_dqsn2 ab16 ddr1_ba2 t25 ddr1_d25 n21 ddr1_d28 ab25 ddr1_d13 ae9 hdmi1_cloc kx w23 ddr1_d16 ac24 ddr1_d1 ad16 ddr1_casn aa23 ddr1_d0 ad18 ddr1_odt0 ae19 ddr1_a1 ac20 ddr1_a9 u21 ddr1_dqm2 aa24 ddr1_d8 u4 mlbp_sig_n ac11 xi_osc1 ad1 csi2_0_dx1 ae3 usb_txn0 pcie_txn1 ac6 usb1_dp ad6 usb_rxp0 pcie_rxp1 aa16 ddr1_ba1 y12 xi_osc0 ab15 ddr1_a14 ac18 ddr1_a0 ae11 hdmi1_data 0x r25 ddr1_dqsn3 y24 ddr1_dqs1 y21 ddr1_a8 w21 ddr1_d19 ad20 ddr1_a4 aa25 ddr1_d14 ad13 hdmi1_data 1y ab9 ljcb_clkn ac25 ddr1_d12 u22 ddr1_d21 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 108 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 ab23 ddr1_d4 ab24 ddr1_d2 ae16 ddr1_ba0 t22 ddr1_d20 t21 ddr1_d23 ab19 ddr1_a3 ae24 ddr1_d7 ac15 ddr1_a13 ac21 ddr1_a11 ad17 ddr1_rasn ab12 xo_osc0 ad23 ddr1_d6 ad9 pcie_txp0 v24 ddr1_dqs2 u1 mlbp_clk_n u23 ddr1_d22 t1 mlbp_dat_n ac22 ddr1_a12 ad24 ddr1_d3 ac8 ljcb_clkp ae21 ddr1_nck y20 ddr1_vref0 ad7 pcie_rxp0 t2 mlbp_dat_p ae23 ddr1_dqm0 ad21 ddr1_ck y25 ddr1_dqsn1 aa11 xo_osc1 ae17 ddr1_rst w22 ddr1_dqm1 ae12 hdmi1_data 1x ae14 hdmi1_data 2x ab2 csi2_0_dy0 ab18 ddr1_cke ab6 usb2_dp ac1 csi2_0_dx0 ae8 pcie_txn0 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 109 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 ac19 ddr1_csn0 aa21 ddr1_a10 ae6 pcie_rxn0 ab7 usb1_dm f19 porz w25 ddr1_d9 p24 ddr1_d31 ad22 ddr1_dqs0 p22 ddr1_d29 u24 ddr1_d18 ad2 csi2_0_dy2 ae18 ddr1_wen ae20 ddr1_a5 w24 ddr1_d15 t24 ddr1_d26 r24 ddr1_dqs3 ad15 hdmi1_data 2y ae22 ddr1_dqsn0 aa18 ddr1_a6 u2 mlbp_clk_p ac2 csi2_0_dy1 ad12 hdmi1_data 0y t23 ddr1_d24 ad10 hdmi1_cloc ky ae5 usb_rxn0 pcie_rxn1 ae2 csi2_0_dx2 p23 ddr1_d30 ac5 usb2_dm ac23 ddr1_d5 ad19 ddr1_a2 ac16 ddr1_a15 ad25 ddr1_d11 ad4 usb_txp0 pcie_txp1 0x1400 ctrl_core_pad _gpmc_ad0 f1 gpmc_ad0 vin1a_d0 vout3_d0 gpio1_6 sysboot0 0x1404 ctrl_core_pad _gpmc_ad1 e2 gpmc_ad1 vin1a_d1 vout3_d1 gpio1_7 sysboot1 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 110 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x1408 ctrl_core_pad _gpmc_ad2 e1 gpmc_ad2 vin1a_d2 vout3_d2 gpio1_8 sysboot2 0x140c ctrl_core_pad _gpmc_ad3 c1 gpmc_ad3 vin1a_d3 vout3_d3 gpio1_9 sysboot3 0x1410 ctrl_core_pad _gpmc_ad4 d1 gpmc_ad4 vin1a_d4 vout3_d4 gpio1_10 sysboot4 0x1414 ctrl_core_pad _gpmc_ad5 d2 gpmc_ad5 vin1a_d5 vout3_d5 gpio1_11 sysboot5 0x1418 ctrl_core_pad _gpmc_ad6 b1 gpmc_ad6 vin1a_d6 vout3_d6 gpio1_12 sysboot6 0x141c ctrl_core_pad _gpmc_ad7 b2 gpmc_ad7 vin1a_d7 vout3_d7 gpio1_13 sysboot7 0x1420 ctrl_core_pad _gpmc_ad8 c2 gpmc_ad8 vin1a_d8 vout3_d8 gpio7_18 sysboot8 0x1424 ctrl_core_pad _gpmc_ad9 d3 gpmc_ad9 vin1a_d9 vout3_d9 gpio7_19 sysboot9 0x1428 ctrl_core_pad _gpmc_ad10 a2 gpmc_ad10 vin1a_d10 vout3_d10 gpio7_28 sysboot10 0x142c ctrl_core_pad _gpmc_ad11 b3 gpmc_ad11 vin1a_d11 vout3_d11 gpio7_29 sysboot11 0x1430 ctrl_core_pad _gpmc_ad12 c3 gpmc_ad12 vin1a_d12 vout3_d12 gpio1_18 sysboot12 0x1434 ctrl_core_pad _gpmc_ad13 c4 gpmc_ad13 vin1a_d13 vout3_d13 gpio1_19 sysboot13 0x1438 ctrl_core_pad _gpmc_ad14 a3 gpmc_ad14 vin1a_d14 vout3_d14 gpio1_20 sysboot14 0x143c ctrl_core_pad _gpmc_ad15 b4 gpmc_ad15 vin1a_d15 vout3_d15 gpio1_21 sysboot15 0x1440 ctrl_core_pad _gpmc_a0 m1 gpmc_a0 vin1a_d16 vout3_d16 vin1b_d0 i2c4_scl uart5_rxd gpio7_3 gpmc_a26 gpmc_a16 driver off 0x1444 ctrl_core_pad _gpmc_a1 m2 gpmc_a1 vin1a_d17 vout3_d17 vin1b_d1 i2c4_sda uart5_txd gpio7_4 driver off 0x1448 ctrl_core_pad _gpmc_a2 l2 gpmc_a2 vin1a_d18 vout3_d18 vin1b_d2 uart7_rxd uart5_ctsn gpio7_5 driver off 0x144c ctrl_core_pad _gpmc_a3 l1 gpmc_a3 qspi1_cs2 vin1a_d19 vout3_d19 vin1b_d3 uart7_txd uart5_rtsn gpio7_6 driver off 0x1450 ctrl_core_pad _gpmc_a4 k3 gpmc_a4 qspi1_cs3 vin1a_d20 vout3_d20 vin1b_d4 i2c5_scl uart6_rxd gpio1_26 driver off 0x1454 ctrl_core_pad _gpmc_a5 k2 gpmc_a5 vin1a_d21 vout3_d21 vin1b_d5 i2c5_sda uart6_txd gpio1_27 driver off 0x1458 ctrl_core_pad _gpmc_a6 j1 gpmc_a6 vin1a_d22 vout3_d22 vin1b_d6 uart8_rxd uart6_ctsn gpio1_28 driver off 0x145c ctrl_core_pad _gpmc_a7 k1 gpmc_a7 vin1a_d23 vout3_d23 vin1b_d7 uart8_txd uart6_rtsn gpio1_29 driver off 0x1460 ctrl_core_pad _gpmc_a8 k4 gpmc_a8 vin1a_hsyn c0 vout3_hsyn c vin1b_hsyn c1 timer12 spi4_sclk gpio1_30 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 111 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x1464 ctrl_core_pad _gpmc_a9 h1 gpmc_a9 vin1a_vsyn c0 vout3_vsyn c vin1b_vsyn c1 timer11 spi4_d1 gpio1_31 driver off 0x1468 ctrl_core_pad _gpmc_a10 j2 gpmc_a10 vin1a_de0 vout3_de vin1b_clk1 timer10 spi4_d0 gpio2_0 driver off 0x146c ctrl_core_pad _gpmc_a11 l3 gpmc_a11 vin1a_fld0 vout3_fld vin1b_de1 timer9 spi4_cs0 gpio2_1 driver off 0x1470 ctrl_core_pad _gpmc_a12 g1 gpmc_a12 gpmc_a0 vin1b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 driver off 0x1474 ctrl_core_pad _gpmc_a13 h3 gpmc_a13 qspi1_rtclk timer7 spi4_cs2 dma_evt2 gpio2_3 driver off 0x1478 ctrl_core_pad _gpmc_a14 h4 gpmc_a14 qspi1_d3 timer6 spi4_cs3 gpio2_4 driver off 0x147c ctrl_core_pad _gpmc_a15 k6 gpmc_a15 qspi1_d2 timer5 gpio2_5 driver off 0x1480 ctrl_core_pad _gpmc_a16 k5 gpmc_a16 qspi1_d0 gpio2_6 driver off 0x1484 ctrl_core_pad _gpmc_a17 g2 gpmc_a17 qspi1_d1 gpio2_7 driver off 0x1488 ctrl_core_pad _gpmc_a18 f2 gpmc_a18 qspi1_sclk gpio2_8 driver off 0x148c ctrl_core_pad _gpmc_a19 a4 gpmc_a19 mmc2_dat4 gpmc_a13 vin2b_d0 gpio2_9 driver off 0x1490 ctrl_core_pad _gpmc_a20 e7 gpmc_a20 mmc2_dat5 gpmc_a14 vin2b_d1 gpio2_10 driver off 0x1494 ctrl_core_pad _gpmc_a21 d6 gpmc_a21 mmc2_dat6 gpmc_a15 vin2b_d2 gpio2_11 driver off 0x1498 ctrl_core_pad _gpmc_a22 c5 gpmc_a22 mmc2_dat7 gpmc_a16 vin2b_d3 gpio2_12 driver off 0x149c ctrl_core_pad _gpmc_a23 b5 gpmc_a23 mmc2_clk gpmc_a17 vin2b_d4 gpio2_13 driver off 0x14a0 ctrl_core_pad _gpmc_a24 d7 gpmc_a24 mmc2_dat0 gpmc_a18 vin2b_d5 gpio2_14 driver off 0x14a4 ctrl_core_pad _gpmc_a25 c6 gpmc_a25 mmc2_dat1 gpmc_a19 vin2b_d6 gpio2_15 driver off 0x14a8 ctrl_core_pad _gpmc_a26 a5 gpmc_a26 mmc2_dat2 gpmc_a20 vin2b_d7 gpio2_16 driver off 0x14ac ctrl_core_pad _gpmc_a27 b6 gpmc_a27 mmc2_dat3 gpmc_a21 vin2b_hsyn c1 gpio2_17 driver off 0x14b0 ctrl_core_pad _gpmc_cs1 a6 gpmc_cs1 mmc2_cmd gpmc_a22 vin2b_vsyn c1 gpio2_18 driver off 0x14b4 ctrl_core_pad _gpmc_cs0 f3 gpmc_cs0 gpio2_19 driver off 0x14b8 ctrl_core_pad _gpmc_cs2 g4 gpmc_cs2 qspi1_cs0 gpio2_20 gpmc_a23 gpmc_a13 driver off 0x14bc ctrl_core_pad _gpmc_cs3 g3 gpmc_cs3 qspi1_cs1 vin1a_clk0 vout3_clk gpmc_a1 gpio2_21 gpmc_a24 gpmc_a14 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 112 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x14c0 ctrl_core_pad _gpmc_clk l4 gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin2b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 gpmc_a20 driver off 0x14c4 ctrl_core_pad _gpmc_advn_al e h5 gpmc_advn _ale gpmc_cs6 clkout2 gpmc_wait1 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 gpmc_a19 driver off 0x14c8 ctrl_core_pad _gpmc_oen_re n g5 gpmc_oen_ ren gpio2_24 driver off 0x14cc ctrl_core_pad _gpmc_wen g6 gpmc_wen gpio2_25 driver off 0x14d0 ctrl_core_pad _gpmc_ben0 h2 gpmc_ben0 gpmc_cs4 vin2b_de1 timer2 dma_evt3 gpio2_26 gpmc_a21 driver off 0x14d4 ctrl_core_pad _gpmc_ben1 h6 gpmc_ben1 gpmc_cs5 vin2b_clk1 gpmc_a3 vin2b_fld1 timer1 dma_evt4 gpio2_27 gpmc_a22 driver off 0x14d8 ctrl_core_pad _gpmc_wait0 f6 gpmc_wait0 gpio2_28 gpmc_a25 gpmc_a15 driver off 0x1554 ctrl_core_pad _vin2a_clk0 d8 vin2a_clk0 vout2_fld emu5 kbd_row0 eqep1a_in pr1_edio_d ata_in0 pr1_edio_d ata_out0 gpio3_28 gpmc_a27 gpmc_a17 driver off 0x1558 ctrl_core_pad _vin2a_de0 b7 vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 kbd_row1 eqep1b_in pr1_edio_d ata_in1 pr1_edio_d ata_out1 gpio3_29 driver off 0x155c ctrl_core_pad _vin2a_fld0 c7 vin2a_fld0 vin2b_clk1 vout2_clk emu7 eqep1_ind ex pr1_edio_d ata_in2 pr1_edio_d ata_out2 gpio3_30 gpmc_a27 gpmc_a18 driver off 0x1560 ctrl_core_pad _vin2a_hsync0 e8 vin2a_hsyn c0 vin2b_hsyn c1 vout2_hsyn c emu8 uart9_rxd spi4_sclk kbd_row2 eqep1_str obe pr1_uart0_c ts_n pr1_edio_d ata_in3 pr1_edio_d ata_out3 gpio3_31 gpmc_a27 driver off 0x1564 ctrl_core_pad _vin2a_vsync0 b8 vin2a_vsyn c0 vin2b_vsyn c1 vout2_vsyn c emu9 uart9_txd spi4_d1 kbd_row3 ehrpwm1a pr1_uart0_r ts_n pr1_edio_d ata_in4 pr1_edio_d ata_out4 gpio4_0 driver off 0x1568 ctrl_core_pad _vin2a_d0 c8 vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 kbd_row4 ehrpwm1b pr1_uart0_r xd pr1_edio_d ata_in5 pr1_edio_d ata_out5 gpio4_1 driver off 0x156c ctrl_core_pad _vin2a_d1 b9 vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 kbd_row5 ehrpwm1_tr ipzone_inpu t pr1_uart0_t xd pr1_edio_d ata_in6 pr1_edio_d ata_out6 gpio4_2 driver off 0x1570 ctrl_core_pad _vin2a_d2 a7 vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 ecap1_in_ pwm1_out pr1_ecap0_ ecap_capin _apwm_o pr1_edio_d ata_in7 pr1_edio_d ata_out7 gpio4_3 driver off 0x1574 ctrl_core_pad _vin2a_d3 a9 vin2a_d3 vout2_d20 emu13 uart10_txd kbd_col0 ehrpwm1_s ynci pr1_edc_lat ch0_in pr1_pru1_g pi0 pr1_pru1_g po0 gpio4_4 driver off 0x1578 ctrl_core_pad _vin2a_d4 a8 vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 ehrpwm1_s ynco pr1_edc_sy nc0_out pr1_pru1_g pi1 pr1_pru1_g po1 gpio4_5 driver off 0x157c ctrl_core_pad _vin2a_d5 a11 vin2a_d5 vout2_d18 emu15 uart10_rtsn kbd_col2 eqep2a_in pr1_edio_s of pr1_pru1_g pi2 pr1_pru1_g po2 gpio4_6 driver off 0x1580 ctrl_core_pad _vin2a_d6 f10 vin2a_d6 vout2_d17 emu16 mii1_rxd1 kbd_col3 eqep2b_in pr1_mii_mt 1_clk pr1_pru1_g pi3 pr1_pru1_g po3 gpio4_7 driver off 0x1584 ctrl_core_pad _vin2a_d7 a10 vin2a_d7 vout2_d16 emu17 mii1_rxd2 kbd_col4 eqep2_ind ex pr1_mii1_tx en pr1_pru1_g pi4 pr1_pru1_g po4 gpio4_8 driver off 0x1588 ctrl_core_pad _vin2a_d8 b10 vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 eqep2_str obe pr1_mii1_tx d3 pr1_pru1_g pi5 pr1_pru1_g po5 gpio4_9 gpmc_a26 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 113 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x158c ctrl_core_pad _vin2a_d9 e10 vin2a_d9 vout2_d14 emu19 mii1_rxd0 kbd_col6 ehrpwm2a pr1_mii1_tx d2 pr1_pru1_g pi6 pr1_pru1_g po6 gpio4_10 gpmc_a25 driver off 0x1590 ctrl_core_pad _vin2a_d10 d10 vin2a_d10 mdio_mclk vout2_d13 kbd_col7 ehrpwm2b pr1_mdio_ mdclk pr1_pru1_g pi7 pr1_pru1_g po7 gpio4_11 gpmc_a24 driver off 0x1594 ctrl_core_pad _vin2a_d11 c10 vin2a_d11 mdio_d vout2_d12 kbd_row7 ehrpwm2_tr ipzone_inpu t pr1_mdio_d ata pr1_pru1_g pi8 pr1_pru1_g po8 gpio4_12 gpmc_a23 driver off 0x1598 ctrl_core_pad _vin2a_d12 b11 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 ecap2_in_ pwm2_out pr1_mii1_tx d1 pr1_pru1_g pi9 pr1_pru1_g po9 gpio4_13 driver off 0x159c ctrl_core_pad _vin2a_d13 d11 vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv kbd_row8 eqep3a_in pr1_mii1_tx d0 pr1_pru1_g pi10 pr1_pru1_g po10 gpio4_14 driver off 0x15a0 ctrl_core_pad _vin2a_d14 c11 vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eqep3b_in pr1_mii_mr 1_clk pr1_pru1_g pi11 pr1_pru1_g po11 gpio4_15 driver off 0x15a4 ctrl_core_pad _vin2a_d15 b12 vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eqep3_ind ex pr1_mii1_rx dv pr1_pru1_g pi12 pr1_pru1_g po12 gpio4_16 driver off 0x15a8 ctrl_core_pad _vin2a_d16 a12 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 mii1_txd1 eqep3_str obe pr1_mii1_rx d3 pr1_pru1_g pi13 pr1_pru1_g po13 gpio4_24 driver off 0x15ac ctrl_core_pad _vin2a_d17 a13 vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 mii1_txd2 ehrpwm3a pr1_mii1_rx d2 pr1_pru1_g pi14 pr1_pru1_g po14 gpio4_25 driver off 0x15b0 ctrl_core_pad _vin2a_d18 e11 vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 mii1_txd3 ehrpwm3b pr1_mii1_rx d1 pr1_pru1_g pi15 pr1_pru1_g po15 gpio4_26 driver off 0x15b4 ctrl_core_pad _vin2a_d19 f11 vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 mii1_txer ehrpwm3_tr ipzone_inpu t pr1_mii1_rx d0 pr1_pru1_g pi16 pr1_pru1_g po16 gpio4_27 driver off 0x15b8 ctrl_core_pad _vin2a_d20 b13 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 mii1_rxer ecap3_in_ pwm3_out pr1_mii1_rx er pr1_pru1_g pi17 pr1_pru1_g po17 gpio4_28 driver off 0x15bc ctrl_core_pad _vin2a_d21 e13 vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 mii1_col pr1_mii1_rx link pr1_pru1_g pi18 pr1_pru1_g po18 gpio4_29 driver off 0x15c0 ctrl_core_pad _vin2a_d22 c13 vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 mii1_crs pr1_mii1_c ol pr1_pru1_g pi19 pr1_pru1_g po19 gpio4_30 driver off 0x15c4 ctrl_core_pad _vin2a_d23 d13 vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 mii1_txen pr1_mii1_cr s pr1_pru1_g pi20 pr1_pru1_g po20 gpio4_31 driver off 0x15e4 ctrl_core_pad _vout1_d2 e14 emu2 0x1604 ctrl_core_pad _vout1_d10 f14 emu3 0x1624 ctrl_core_pad _vout1_d18 f13 emu4 0x163c ctrl_core_pad _mdio_mclk l5 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin1b_clk1 pr1_mii0_c ol pr2_pru1_g pi0 pr2_pru1_g po0 gpio5_15 driver off 0x1640 ctrl_core_pad _mdio_d l6 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin1b_d0 pr1_mii0_rx link pr2_pru1_g pi1 pr2_pru1_g po1 gpio5_16 driver off 0x1644 ctrl_core_pad _rmii_mhz_50_cl k p5 rmii_mhz_ 50_clk vin2a_d11 pr2_pru1_g pi2 pr2_pru1_g po2 gpio5_17 driver off 0x1648 ctrl_core_pad _uart3_rxd n5 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin1b_d1 spi3_sclk pr1_mii0_rx dv pr2_pru1_g pi3 pr2_pru1_g po3 gpio5_18 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 114 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x164c ctrl_core_pad _uart3_txd n6 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin1b_d2 spi3_d1 spi4_cs1 pr1_mii_mr 0_clk pr2_pru1_g pi4 pr2_pru1_g po4 gpio5_19 driver off 0x1650 ctrl_core_pad _rgmii0_txc t4 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin1b_d3 usb3_ulpi_c lk spi3_d0 spi4_cs2 pr1_mii0_rx d3 pr2_pru1_g pi5 pr2_pru1_g po5 gpio5_20 driver off 0x1654 ctrl_core_pad _rgmii0_txctl t5 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin1b_d4 usb3_ulpi_s tp spi3_cs0 spi4_cs3 pr1_mii0_rx d2 pr2_pru1_g pi6 pr2_pru1_g po6 gpio5_21 driver off 0x1658 ctrl_core_pad _rgmii0_txd3 p4 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin1b_de1 usb3_ulpi_d ir spi4_sclk uart4_rxd pr1_mii0_cr s pr2_pru1_g pi7 pr2_pru1_g po7 gpio5_22 driver off 0x165c ctrl_core_pad _rgmii0_txd2 p3 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsyn c0 vin1b_hsyn c1 usb3_ulpi_n xt spi4_d1 uart4_txd pr1_mii0_rx er pr2_pru1_g pi8 pr2_pru1_g po8 gpio5_23 driver off 0x1660 ctrl_core_pad _rgmii0_txd1 r2 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsyn c0 vin1b_vsyn c1 usb3_ulpi_d 0 spi4_d0 uart4_ctsn pr1_mii0_rx d1 pr2_pru1_g pi9 pr2_pru1_g po9 gpio5_24 driver off 0x1664 ctrl_core_pad _rgmii0_txd0 r1 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb3_ulpi_d 1 spi4_cs0 uart4_rtsn pr1_mii0_rx d0 pr2_pru1_g pi10 pr2_pru1_g po10 gpio5_25 driver off 0x1668 ctrl_core_pad _rgmii0_rxc n2 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin1b_d5 usb3_ulpi_d 2 pr1_mii_mt 0_clk pr2_pru1_g pi11 pr2_pru1_g po11 gpio5_26 driver off 0x166c ctrl_core_pad _rgmii0_rxctl p2 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin1b_d6 usb3_ulpi_d 3 pr1_mii0_tx d3 pr2_pru1_g pi12 pr2_pru1_g po12 gpio5_27 driver off 0x1670 ctrl_core_pad _rgmii0_rxd3 n1 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin1b_d7 usb3_ulpi_d 4 pr1_mii0_tx d2 pr2_pru1_g pi13 pr2_pru1_g po13 gpio5_28 driver off 0x1674 ctrl_core_pad _rgmii0_rxd2 p1 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb3_ulpi_d 5 pr1_mii0_tx en pr2_pru1_g pi14 pr2_pru1_g po14 gpio5_29 driver off 0x1678 ctrl_core_pad _rgmii0_rxd1 n3 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb3_ulpi_d 6 pr1_mii0_tx d1 pr2_pru1_g pi15 pr2_pru1_g po15 gpio5_30 driver off 0x167c ctrl_core_pad _rgmii0_rxd0 n4 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin1b_fld1 usb3_ulpi_d 7 pr1_mii0_tx d0 pr2_pru1_g pi16 pr2_pru1_g po16 gpio5_31 driver off 0x1680 ctrl_core_pad _usb1_drvvbus ad3 usb1_drvvb us timer16 gpio6_12 driver off 0x1684 ctrl_core_pad _usb2_drvvbus aa6 usb2_drvvb us timer15 gpio6_13 driver off 0x1688 ctrl_core_pad _gpio6_14 h21 gpio6_14 mcasp1_ax r8 dcan2_tx uart10_rxd i2c3_sda timer1 gpio6_14 driver off 0x168c ctrl_core_pad _gpio6_15 k22 gpio6_15 mcasp1_ax r9 dcan2_rx uart10_txd i2c3_scl timer2 gpio6_15 driver off 0x1690 ctrl_core_pad _gpio6_16 k23 gpio6_16 mcasp1_ax r10 clkout1 timer3 gpio6_16 driver off 0x1694 ctrl_core_pad _xref_clk0 j25 xref_clk0 mcasp2_ax r8 mcasp1_ax r4 mcasp1_ah clkx mcasp5_ah clkx atl_clk0 vin1a_d0 hdq0 clkout2 timer13 pr2_mii1_c ol pr2_pru1_g pi5 pr2_pru1_g po5 gpio6_17 driver off 0x1698 ctrl_core_pad _xref_clk1 j24 xref_clk1 mcasp2_ax r9 mcasp1_ax r5 mcasp2_ah clkx mcasp6_ah clkx atl_clk1 vin1a_clk0 timer14 pr2_mii1_cr s pr2_pru1_g pi6 pr2_pru1_g po6 gpio6_18 driver off 0x169c ctrl_core_pad _xref_clk2 h24 xref_clk2 mcasp2_ax r10 mcasp1_ax r6 mcasp3_ah clkx mcasp7_ah clkx atl_clk2 timer15 gpio6_19 driver off 0x16a0 ctrl_core_pad _xref_clk3 h25 xref_clk3 mcasp2_ax r11 mcasp1_ax r7 mcasp4_ah clkx mcasp8_ah clkx atl_clk3 hdq0 clkout3 timer16 gpio6_20 driver off 0x16a4 ctrl_core_pad _mcasp1_aclkx c16 mcasp1_acl kx vin1a_fld0 i2c3_sda pr2_mdio_ mdclk pr2_pru1_g pi7 pr2_pru1_g po7 gpio7_31 driver off 0x16a8 ctrl_core_pad _mcasp1_fsx c17 mcasp1_fsx vin1a_de0 i2c3_scl pr2_mdio_d ata gpio7_30 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 115 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x16ac ctrl_core_pad _mcasp1_aclkr d16 mcasp1_acl kr mcasp7_ax r2 i2c4_sda gpio5_0 driver off 0x16b0 ctrl_core_pad _mcasp1_fsr d17 mcasp1_fsr mcasp7_ax r3 i2c4_scl gpio5_1 driver off 0x16b4 ctrl_core_pad _mcasp1_axr0 d14 mcasp1_ax r0 uart6_rxd vin1a_vsyn c0 i2c5_sda pr2_mii0_rx er pr2_pru1_g pi8 pr2_pru1_g po8 gpio5_2 driver off 0x16b8 ctrl_core_pad _mcasp1_axr1 b14 mcasp1_ax r1 uart6_txd vin1a_hsyn c0 i2c5_scl pr2_mii_mt 0_clk pr2_pru1_g pi9 pr2_pru1_g po9 gpio5_3 driver off 0x16bc ctrl_core_pad _mcasp1_axr2 c14 mcasp1_ax r2 mcasp6_ax r2 uart6_ctsn gpio5_4 driver off 0x16c0 ctrl_core_pad _mcasp1_axr3 b15 mcasp1_ax r3 mcasp6_ax r3 uart6_rtsn gpio5_5 driver off 0x16c4 ctrl_core_pad _mcasp1_axr4 a15 mcasp1_ax r4 mcasp4_ax r2 gpio5_6 driver off 0x16c8 ctrl_core_pad _mcasp1_axr5 a14 mcasp1_ax r5 mcasp4_ax r3 gpio5_7 driver off 0x16cc ctrl_core_pad _mcasp1_axr6 a17 mcasp1_ax r6 mcasp5_ax r2 gpio5_8 driver off 0x16d0 ctrl_core_pad _mcasp1_axr7 a16 mcasp1_ax r7 mcasp5_ax r3 timer4 gpio5_9 driver off 0x16d4 ctrl_core_pad _mcasp1_axr8 a18 mcasp1_ax r8 mcasp6_ax r0 spi3_sclk vin1a_d15 timer5 pr2_mii0_tx en pr2_pru1_g pi10 pr2_pru1_g po10 gpio5_10 driver off 0x16d8 ctrl_core_pad _mcasp1_axr9 b17 mcasp1_ax r9 mcasp6_ax r1 spi3_d1 vin1a_d14 timer6 pr2_mii0_tx d3 pr2_pru1_g pi11 pr2_pru1_g po11 gpio5_11 driver off 0x16dc ctrl_core_pad _mcasp1_axr10 b16 mcasp1_ax r10 mcasp6_acl kx mcasp6_acl kr spi3_d0 vin1a_d13 timer7 pr2_mii0_tx d2 pr2_pru1_g pi12 pr2_pru1_g po12 gpio5_12 driver off 0x16e0 ctrl_core_pad _mcasp1_axr11 b18 mcasp1_ax r11 mcasp6_fsx mcasp6_fsr spi3_cs0 vin1a_d12 timer8 pr2_mii0_tx d1 pr2_pru1_g pi13 pr2_pru1_g po13 gpio4_17 driver off 0x16e4 ctrl_core_pad _mcasp1_axr12 a19 mcasp1_ax r12 mcasp7_ax r0 spi3_cs1 vin1a_d11 timer9 pr2_mii0_tx d0 pr2_pru1_g pi14 pr2_pru1_g po14 gpio4_18 driver off 0x16e8 ctrl_core_pad _mcasp1_axr13 e17 mcasp1_ax r13 mcasp7_ax r1 vin1a_d10 timer10 pr2_mii_mr 0_clk pr2_pru1_g pi15 pr2_pru1_g po15 gpio6_4 driver off 0x16ec ctrl_core_pad _mcasp1_axr14 e16 mcasp1_ax r14 mcasp7_acl kx mcasp7_acl kr vin1a_d9 timer11 pr2_mii0_rx dv pr2_pru1_g pi16 pr2_pru1_g po16 gpio6_5 driver off 0x16f0 ctrl_core_pad _mcasp1_axr15 f16 mcasp1_ax r15 mcasp7_fsx mcasp7_fsr vin1a_d8 timer12 pr2_mii0_rx d3 pr2_pru0_g pi20 pr2_pru0_g po20 gpio6_6 driver off 0x16f4 ctrl_core_pad _mcasp2_aclkx e19 mcasp2_acl kx vin1a_d7 pr2_mii0_rx d2 pr2_pru0_g pi18 pr2_pru0_g po18 driver off 0x16f8 ctrl_core_pad _mcasp2_fsx d19 mcasp2_fsx vin1a_d6 pr2_mii0_rx d1 pr2_pru0_g pi19 pr2_pru0_g po19 driver off 0x1704 ctrl_core_pad _mcasp2_axr0 a20 mcasp2_ax r0 driver off 0x1708 ctrl_core_pad _mcasp2_axr1 b19 mcasp2_ax r1 driver off 0x170c ctrl_core_pad _mcasp2_axr2 a21 mcasp2_ax r2 mcasp3_ax r2 vin1a_d5 pr2_mii0_rx d0 pr2_pru0_g pi16 pr2_pru0_g po16 gpio6_8 driver off 0x1710 ctrl_core_pad _mcasp2_axr3 b21 mcasp2_ax r3 mcasp3_ax r3 vin1a_d4 pr2_mii0_rx link pr2_pru0_g pi17 pr2_pru0_g po17 gpio6_9 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 116 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x1714 ctrl_core_pad _mcasp2_axr4 b20 mcasp2_ax r4 mcasp8_ax r0 gpio1_4 driver off 0x1718 ctrl_core_pad _mcasp2_axr5 c19 mcasp2_ax r5 mcasp8_ax r1 gpio6_7 driver off 0x171c ctrl_core_pad _mcasp2_axr6 d20 mcasp2_ax r6 mcasp8_acl kx mcasp8_acl kr gpio2_29 driver off 0x1720 ctrl_core_pad _mcasp2_axr7 c20 mcasp2_ax r7 mcasp8_fsx mcasp8_fsr gpio1_5 driver off 0x1724 ctrl_core_pad _mcasp3_aclkx a22 mcasp3_acl kx mcasp3_acl kr mcasp2_ax r12 uart7_rxd vin1a_d3 pr2_mii0_cr s pr2_pru0_g pi12 pr2_pru0_g po12 gpio5_13 driver off 0x1728 ctrl_core_pad _mcasp3_fsx a23 mcasp3_fsx mcasp3_fsr mcasp2_ax r13 uart7_txd vin1a_d2 pr2_mii0_c ol pr2_pru0_g pi13 pr2_pru0_g po13 gpio5_14 driver off 0x172c ctrl_core_pad _mcasp3_axr0 b22 mcasp3_ax r0 mcasp2_ax r14 uart7_ctsn uart5_rxd vin1a_d1 pr2_mii1_rx er pr2_pru0_g pi14 pr2_pru0_g po14 driver off 0x1730 ctrl_core_pad _mcasp3_axr1 b23 mcasp3_ax r1 mcasp2_ax r15 uart7_rtsn uart5_txd vin1a_d0 pr2_mii1_rx link pr2_pru0_g pi15 pr2_pru0_g po15 driver off 0x1734 ctrl_core_pad _mcasp4_aclkx c23 mcasp4_acl kx mcasp4_acl kr spi3_sclk uart8_rxd i2c4_sda driver off 0x1738 ctrl_core_pad _mcasp4_fsx b25 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl driver off 0x173c ctrl_core_pad _mcasp4_axr0 a24 mcasp4_ax r0 spi3_d0 uart8_ctsn uart4_rxd i2c6_scl driver off 0x1740 ctrl_core_pad _mcasp4_axr1 d23 mcasp4_ax r1 spi3_cs0 uart8_rtsn uart4_txd pr2_pru1_g pi0 pr2_pru1_g po0 i2c6_sda driver off 0x1744 ctrl_core_pad _mcasp5_aclkx ac3 mcasp5_acl kx mcasp5_acl kr spi4_sclk uart9_rxd i2c5_sda mlb_clk pr2_pru1_g pi1 pr2_pru1_g po1 driver off 0x1748 ctrl_core_pad _mcasp5_fsx u6 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl pr2_pru1_g pi2 pr2_pru1_g po2 driver off 0x174c ctrl_core_pad _mcasp5_axr0 aa5 mcasp5_ax r0 spi4_d0 uart9_ctsn uart3_rxd mlb_sig pr2_mdio_ mdclk pr2_pru1_g pi3 pr2_pru1_g po3 driver off 0x1750 ctrl_core_pad _mcasp5_axr1 ac4 mcasp5_ax r1 spi4_cs0 uart9_rtsn uart3_txd mlb_dat pr2_mdio_d ata pr2_pru1_g pi4 pr2_pru1_g po4 driver off 0x1754 ctrl_core_pad _mmc1_clk u3 mmc1_clk gpio6_21 driver off 0x1758 ctrl_core_pad _mmc1_cmd v4 mmc1_cmd gpio6_22 driver off 0x175c ctrl_core_pad _mmc1_dat0 v3 mmc1_dat0 gpio6_23 driver off 0x1760 ctrl_core_pad _mmc1_dat1 v2 mmc1_dat1 gpio6_24 driver off 0x1764 ctrl_core_pad _mmc1_dat2 w1 mmc1_dat2 gpio6_25 driver off 0x1768 ctrl_core_pad _mmc1_dat3 v1 mmc1_dat3 gpio6_26 driver off 0x176c ctrl_core_pad _mmc1_sdcd u5 mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 driver off 0x1770 ctrl_core_pad _mmc1_sdwp v5 mmc1_sdw p uart6_txd i2c4_scl gpio6_28 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 117 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x1774 ctrl_core_pad _gpio6_10 y5 gpio6_10 mdio_mclk i2c3_sda usb3_ulpi_d 7 vin2b_hsyn c1 vin1a_clk0 ehrpwm2a pr2_mii_mt 1_clk pr2_pru0_g pi0 pr2_pru0_g po0 gpio6_10 driver off 0x1778 ctrl_core_pad _gpio6_11 y6 gpio6_11 mdio_d i2c3_scl usb3_ulpi_d 6 vin2b_vsyn c1 vin1a_de0 ehrpwm2b pr2_mii1_tx en pr2_pru0_g pi1 pr2_pru0_g po1 gpio6_11 driver off 0x177c ctrl_core_pad _mmc3_clk y2 mmc3_clk usb3_ulpi_d 5 vin2b_d7 vin1a_d7 ehrpwm2_tr ipzone_inpu t pr2_mii1_tx d3 pr2_pru0_g pi2 pr2_pru0_g po2 gpio6_29 driver off 0x1780 ctrl_core_pad _mmc3_cmd y1 mmc3_cmd spi3_sclk usb3_ulpi_d 4 vin2b_d6 vin1a_d6 ecap2_in_ pwm2_out pr2_mii1_tx d2 pr2_pru0_g pi3 pr2_pru0_g po3 gpio6_30 driver off 0x1784 ctrl_core_pad _mmc3_dat0 y4 mmc3_dat0 spi3_d1 uart5_rxd usb3_ulpi_d 3 vin2b_d5 vin1a_d5 eqep3a_in pr2_mii1_tx d1 pr2_pru0_g pi4 pr2_pru0_g po4 gpio6_31 driver off 0x1788 ctrl_core_pad _mmc3_dat1 aa2 mmc3_dat1 spi3_d0 uart5_txd usb3_ulpi_d 2 vin2b_d4 vin1a_d4 eqep3b_in pr2_mii1_tx d0 pr2_pru0_g pi5 pr2_pru0_g po5 gpio7_0 driver off 0x178c ctrl_core_pad _mmc3_dat2 aa3 mmc3_dat2 spi3_cs0 uart5_ctsn usb3_ulpi_d 1 vin2b_d3 vin1a_d3 eqep3_ind ex pr2_mii_mr 1_clk pr2_pru0_g pi6 pr2_pru0_g po6 gpio7_1 driver off 0x1790 ctrl_core_pad _mmc3_dat3 w2 mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d 0 vin2b_d2 vin1a_d2 eqep3_str obe pr2_mii1_rx dv pr2_pru0_g pi7 pr2_pru0_g po7 gpio7_2 driver off 0x1794 ctrl_core_pad _mmc3_dat4 y3 mmc3_dat4 spi4_sclk uart10_rxd usb3_ulpi_n xt vin2b_d1 vin1a_d1 ehrpwm3a pr2_mii1_rx d3 pr2_pru0_g pi8 pr2_pru0_g po8 gpio1_22 driver off 0x1798 ctrl_core_pad _mmc3_dat5 aa1 mmc3_dat5 spi4_d1 uart10_txd usb3_ulpi_d ir vin2b_d0 vin1a_d0 ehrpwm3b pr2_mii1_rx d2 pr2_pru0_g pi9 pr2_pru0_g po9 gpio1_23 driver off 0x179c ctrl_core_pad _mmc3_dat6 aa4 mmc3_dat6 spi4_d0 uart10_ctsn usb3_ulpi_s tp vin2b_de1 vin1a_hsyn c0 ehrpwm3_tr ipzone_inpu t pr2_mii1_rx d1 pr2_pru0_g pi10 pr2_pru0_g po10 gpio1_24 driver off 0x17a0 ctrl_core_pad _mmc3_dat7 ab1 mmc3_dat7 spi4_cs0 uart10_rtsn usb3_ulpi_c lk vin2b_clk1 vin1a_vsyn c0 ecap3_in_ pwm3_out pr2_mii1_rx d0 pr2_pru0_g pi11 pr2_pru0_g po11 gpio1_25 driver off 0x17a4 ctrl_core_pad _spi1_sclk c24 spi1_sclk gpio7_7 driver off 0x17a8 ctrl_core_pad _spi1_d1 d24 spi1_d1 gpio7_8 driver off 0x17ac ctrl_core_pad _spi1_d0 d25 spi1_d0 gpio7_9 driver off 0x17b0 ctrl_core_pad _spi1_cs0 b24 spi1_cs0 gpio7_10 driver off 0x17b4 ctrl_core_pad _spi1_cs1 c25 spi1_cs1 spi2_cs1 gpio7_11 driver off 0x17b8 ctrl_core_pad _spi1_cs2 e24 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 driver off 0x17bc ctrl_core_pad _spi1_cs3 e25 spi1_cs3 uart4_txd mmc3_sdw p spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 driver off 0x17c0 ctrl_core_pad _spi2_sclk g25 spi2_sclk uart3_rxd gpio7_14 driver off 0x17c4 ctrl_core_pad _spi2_d1 f25 spi2_d1 uart3_txd gpio7_15 driver off 0x17c8 ctrl_core_pad _spi2_d0 g24 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 driver off 0x17cc ctrl_core_pad _spi2_cs0 f24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 driver off copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 118 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x17d0 ctrl_core_pad _dcan1_tx h22 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 driver off 0x17d4 ctrl_core_pad _dcan1_rx h23 dcan1_rx uart8_txd mmc2_sdw p hdmi1_cec gpio1_15 driver off 0x17e0 ctrl_core_pad _uart1_rxd l25 uart1_rxd mmc4_sdcd gpio7_22 driver off 0x17e4 ctrl_core_pad _uart1_txd m25 uart1_txd mmc4_sdw p gpio7_23 driver off 0x17e8 ctrl_core_pad _uart1_ctsn l20 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 driver off 0x17ec ctrl_core_pad _uart1_rtsn m24 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 driver off 0x17f0 ctrl_core_pad _uart2_rxd n23 uart2_rxd uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 driver off 0x17f4 ctrl_core_pad _uart2_txd n25 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 driver off 0x17f8 ctrl_core_pad _uart2_ctsn n22 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 driver off 0x17fc ctrl_core_pad _uart2_rtsn n24 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 driver off 0x1800 ctrl_core_pad _i2c1_sda g23 i2c1_sda driver off 0x1804 ctrl_core_pad _i2c1_scl g22 i2c1_scl driver off 0x1808 ctrl_core_pad _i2c2_sda f23 i2c2_sda hdmi1_ddc _scl driver off 0x180c ctrl_core_pad _i2c2_scl g21 i2c2_scl hdmi1_ddc _sda driver off 0x1818 ctrl_core_pad _wakeup0 ac10 dcan1_rx gpio1_0 sys_nirq2 driver off 0x1824 ctrl_core_pad _wakeup3 ab10 sys_nirq1 gpio1_3 dcan2_rx driver off 0x1830 ctrl_core_pad _tms l21 tms 0x1834 ctrl_core_pad _tdi l23 tdi gpio8_27 0x1838 ctrl_core_pad _tdo j20 tdo gpio8_28 0x183c ctrl_core_pad _tclk k21 tclk 0x1840 ctrl_core_pad _trstn l22 trstn 0x1844 ctrl_core_pad _rtck k25 rtck gpio8_29 0x1848 ctrl_core_pad _emu0 c21 emu0 gpio8_30 0x184c ctrl_core_pad _emu1 c22 emu1 gpio8_31 copyright ? 2016 ? 2018, texas instruments incorporated terminal configuration and functions submit documentation feedback product folder links: dra71 119 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 4-32. pin multiplexing (continued) address register name ball number muxmode field settings (ctrl_core_pad_*[3:0]) 0 1 2 3* 4* 5* 6* 7 8* 9 10 11 12 13 14* 15 0x185c ctrl_core_pad _resetn k24 resetn 0x1860 ctrl_core_pad _nmin_dsp l24 nmin_dsp 0x1864 ctrl_core_pad _rstoutn e20 rstoutn 1. na in table stands for not applicable. 120 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 terminal configuration and functions copyright ? 2016 ? 2018, texas instruments incorporated 4.5 connections for unused pins this section describes the connection requirements of the unused and reserved balls. note the following balls are reserved: k20, l19, g20 these balls must be left unconnected. note all unused power supply balls must be supplied with the voltages specified in the section 5.4 , recommended operating conditions, unless alternative tie-off options are included in section 4.3 , signal descriptions . table 4-33. unused balls specific connection requirements balls connection requirements y12 / ac11 / l22 / ac10 / ab10 / ad22 / y24 / v24 / r24 these balls must be connected to gnd through an external pull resistor if unused. k21 / l24 / k24 / g22 / g23 / l21 / g21 / f23 / ae22 / y25 / v25 / r25 these balls must be connect to the corresponding power supply through an external pull resistor if unused. f20 (vpp) this ball must be left unconnected if unused note all other unused signal balls with a pad configuration register can be left unconnected with their internal pullup or pulldown resistor enabled. note all other unused signal balls without a pad configuration register can be left unconnected. 121 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5 specifications note for more information, see power, reset, and clock management / prcm subsystem environment / external voltage inputs or initialization / preinitialization / power requirements section of the device trm. note the index number 1 which is part of the emif1 signal prefixes (ddr1_*) listed in table 4-6 , emif signal descriptions , column "signal name" not to be confused with ddr1 type of sdram memories. note audio back end (abe) module is not supported for this family of devices, but ? abe ? name is still present in some clock or dpll names. caution all io cells are not fail-safe compliant and should not be externally driven in absence of their io supply. 122 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) parameter (1) min max unit v supply (steady-state) supply voltage ranges (steady- state) core (vdd, vdd_dsp) -0.3 1.5 v analog (vdda_usb1, vdda_usb2, vdda_per, vdda_ddr, vdda_debug, vdda_mpu_abe, vdda_usb3, vdda_csi, vdda_core_gmac, vdda_gpu, dda_hdmi, vdda_pcie, vdda_video, vdda_osc) -0.3 2.0 v analog 3.3v (vdda33v_usb1, vdda33v_usb2) -0.3 3.8 v vdds18v, vdds18v_ddr1, vdds_mlbp, vdds_ddr1 -0.3 2.1 v vddshv1, vddshv3, vddshv4, vddshv7-11 (1.8v mode) -0.3 2.1 v vddshv1, vddshv3, vddshv4, vddshv7, vddshv9-11 (3.3v mode) -0.3 3.8 v vddshv8 (3.3v mode) -0.3 3.6 v v io (steady-state) input and output voltage ranges (steady-state) core i/os -0.3 1.5 v analog i/os (except hdmi) -0.3 2.0 v hdmi i/os -0.3 3.5 v i/o 1.35v -0.3 1.65 v i/o 1.5v -0.3 1.8 v 1.8v i/os -0.3 2.1 v 3.3v i/os (except those powered by vddshv8) -0.3 3.8 v 3.3v i/os (powered by vddshv8) -0.3 3.6 v sr maximum slew rate, all supplies 10 5 v/s v io (transient overshoot / undershoot) input and output voltage ranges (transient overshoot/undershoot) note: valid for up to 20% of the signal period. see figure 5-1 . 0.2 vdd (4) v t j operating junction temperature range automotive -40 +125 c t stg storage temperature range after soldered onto pc board -55 +150 c latch-up i-test i-test (5) , all i/os (if different levels then one line per level) -100 100 ma latch-up ov-test over-voltage test (6) , all supplies (if different levels then one line per level) n/a 1.5 vsupply max v (1) stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under section 5.4 , recommended operating conditions , is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to vss, unless otherwise noted. (3) see i/os supplied by this power pin in table 4-1 pin attributes (4) vdd is the voltage on the corresponding power-supply pin(s) for the io. (5) per jedec jesd78 at 125 c with specified i/o pin injection current and clamp voltage of 1.5 times maximum recommended i/o voltage and negative 0.5 times maximum recommended i/o voltage. (6) per jedec jesd78 at 125 c. (7) the maximum valid input voltage on an io pin cannot exceed 0.3 volts when the supply powering the io is turned off. this requirement applies to all the io pins which are not fail-safe and for all values of io supply voltage. special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective io supply. it is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. 123 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-1. t overshoot + t undershoot < 20% of t period 5.2 esd ratings value unit v esd electrostatic discharge human-body model (hbm), per aec q100-002 (1) 1000 v charged-device model (cdm), per aec q100-011 all pins 250 corner pins (a1, a25, ae1, ae25) 750 (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 5.3 power on hours (poh) limits ip duty cycle voltage domain voltage (v) (max) frequency (mhz) (max) tj( c) poh all 100% all all support opps automotive profile (4) 20000 (1) the information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under ti ? s standard terms and conditions for ti semiconductor products. (2) poh is a functional of voltage, temperature and time. usage at higher voltages and temperatures will result in a reduction in poh to achieve the same reliability performance. for assessment of alternate use cases, contact your local ti representative. (3) unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures. (4) automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40 c, 65%@70 c, 20%@110 c, 10%@125 c. 5.4 recommended operating conditions over operating free-air temperature range (unless otherwise noted) parameter description min (2) nom max dc (3) max (2) unit input power supply voltage range vdd core voltage domain supply see section 5.5 v vdd_dsp dsp voltage domain supply see section 5.5 v vdda_usb1 dpll_usb and hs usb1 1.8v analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_usb2 hs usb2 1.8v analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda33v_usb1 (5) hs usb1 3.3v analog power supply 3.135 3.3 3.366 3.465 v maximum noise (peak-peak) 50 mv ppmax vdda33v_usb2 (5) hs usb2 3.3v analog power supply 3.135 3.3 3.366 3.465 v maximum noise (peak-peak) 50 mv ppmax vdda_per per pll and per hsdivider analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax t overshoot t undershoot t period overshoot = 20% of nominal io supply voltage undershoot = 20% of nominal io supply voltage nominal io supply voltage vss osus_sprs851 124 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) parameter description min (2) nom max dc (3) max (2) unit vdda_ddr dpll_ddr and ddr hsdivider analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_debug dpll_debug analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_core_gmac dpll_core and core hsdivider analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_gpu dpll_gpu analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_hdmi pll_hdmi and hdmi analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_pcie dpll_pcie_ref and pcie analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_usb3 dpll_usb_otg_ss and usb3.0 rx/tx analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_video dpll_video1 analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdds_mlbp mlbp io power supply 1.71 1.80 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_mpu_abe dpll_mpu analog power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_osc hfosc analog power supply 1.71 1.80 1.89 v maximum noise (peak-peak) 50 mv ppmax vdda_csi csi interface 1.8v supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdds18v 1.8v power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdds18v_ddr1 emif1 bias power supply 1.71 1.80 1.836 1.89 v maximum noise (peak-peak) 50 mv ppmax vdds_ddr1 emif1 power supply (1.5v for ddr3 mode / 1.35v ddr3l mode) 1.35-v mode 1.28 1.35 1.377 1.42 v 1.5-v mode 1.43 1.50 1.53 1.57 maximum noise (peak- peak) 1.35-v mode 50 mv ppmax 1.5-v mode vddshv1 dual voltage (1.8v or 3.3v) power supply for the vin2 power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode 125 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) parameter description min (2) nom max dc (3) max (2) unit vddshv10 dual voltage (1.8v or 3.3v) power supply for the gpmc power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv11 dual voltage (1.8v or 3.3v) power supply for the mmc2 power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv3 dual voltage (1.8v or 3.3v) power supply for the general power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv4 dual voltage (1.8v or 3.3v) power supply for the mmc4 power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv7 dual voltage (1.8v or 3.3v) power supply for the wifi power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv8 dual voltage (1.8v or 3.3v) power supply for the mmc1 power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vddshv9 dual voltage (1.8v or 3.3v) power supply for the rgmii power group pins 1.8-v mode 1.71 1.80 1.836 1.89 v 3.3-v mode 3.135 3.30 3.366 3.465 maximum noise (peak- peak) 1.8-v mode 50 mv ppmax 3.3-v mode vss ground supply 0 v vssa_osc0 osc0 analog ground 0 v vssa_osc1 osc1 analog ground 0 v t j (1) operating junction temperature range automotive -40 +125 c ddr1_vref0 reference power supply emif1 0.5 vdds_ddr1 v (1) refer to power on hours table for limitations. (2) the voltage at the device ball should never be below the min voltage or above the max voltage for any amount of time. this requirement includes dynamic voltage events such as ac ripple, voltage transients, voltage dips, etc. (3) the dc voltage at the device ball should never be above the max dc voltage to avoid impact on device reliability and lifetime poh (power-on-hours). the max dc voltage is defined as the highest allowed dc regulated voltage, without transients, seen at the ball. (4) logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. 126 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) (5) usb analog supply also powers digital io buffers. this supply cannot be tied to vss if usb is unused since digital io buffers must be powered during device operation. 5.5 operating performance points this section describes the operating conditions of the device. this section also contains the description of each opp (operating performance point) for processor clocks and device core clocks. table 5-1 describes the maximum supported frequency per speed grade for dra71x devices. table 5-1. speed grade maximum frequency (1) device speed mpu dsp ipu iva gpu l3 ddr3 / ddr3l dra71xxe 600 400 212.8 532 212.8 266 532 (ddr-1066) dra71xxf 600 750 212.8 532 212.8 266 532 (ddr-1066) dra71xxg 800 400 212.8 532 425.6 266 667 (ddr-1333) dra71xxh 800 750 212.8 532 425.6 266 667 (ddr-1333) dra71xxi 1000 600 212.8 532 425.6 266 667 (ddr-1333) dra71xxj 1000 750 212.8 532 425.6 266 667 (ddr-1333) (1) n/a in this table stands for not applicable. 5.5.1 avs and abb requirements adaptive voltage scaling (avs) and adaptive body biasing (abb) are required on most of the vdd_* supplies as defined in table 5-2 . table 5-2. avs and abb requirements per vdd_* supply supply avs required? abb required? vdd yes, for all opps no vdd_dsp yes, for all opps yes, for all opps 5.5.2 voltage and core clock specifications table 5-3 shows the recommended opp per voltage domain. table 5-3. voltage domains operating performance points (1) domain condition opp_nom opp_high min (3) nom (2) max (3) min (3) nom (2) max dc (4) max (3) vd_core (v) (8) boot (before avs is enabled) (5) 1.11 1.15 1.2 not applicable after avs is enabled (5) avs voltage (6) ? 3.5% avs voltage (6) 1.2 not applicable vd_dsp (v) (9) boot (before avs is enabled) (5) 1.02 1.06 1.16 not applicable after avs is enabled (5) avs voltage (6) ? 3.5% avs voltage (6) 1.2 avs voltage (6) ? 3.5% avs voltage (6) avs voltage (6) +2% avs voltage (6) + 5% (1) the voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. systems should be designed with the ability to modify the voltage to comply with future recommendations. (2) in a typical implementation, the power supply should target the nom voltage. (3) the voltage at the device ball should never be below the min voltage or above the max voltage for any amount of time. this requirement includes dynamic voltage events such as ac ripple, voltage transients, voltage dips, etc. (4) the dc voltage at the device ball should never be above the max dc voltage to avoid impact on device reliability and lifetime poh 127 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (power-on-hours). the max dc voltage is defined as the highest allowed dc regulated voltage, without transients, seen at the ball. (5) for all opps, avs must be enabled to avoid impact on device reliability, lifetime poh (power-on-hours), and device power. (6) the avs voltages are device-dependent, voltage domain-dependent, and opp-dependent. they must be read from the std_fuse_opp registers. for information about std_fuse_opp registers address, please refer to control module section of the trm. the power supply should be adjustable over the following ranges for each required opp: ? opp_nom for dsp: 0.85 v ? 1.15 v ? opp_nom for core: 0.85 v - 1.15 v ? opp_high: 1.05 v - 1.25 v the avs voltages will be within the above specified ranges. (7) the power supply must be programmed with the avs voltages for the core voltage domain, either just after the rom boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains. (8) the package routes vd_core (vdd) to the vd_mpu, vd_sgx, vd_core and vd_rtc domains on the die. (9) the package routes vd_dsp (vdd_dsp) to the vd_dspeve and vd_iva domains on the die. table 5-4 describes the standard processor clocks speed characteristics vs opp of the device. table 5-4. supported opp vs max frequency (2) description opp_nom opp_high max freq. (mhz) max freq. (mhz) vd_core mpu_clk 1000 n/a gpu_clk 425.6 n/a core_ipux_clk 212.8 n/a l3_clk 266 n/a ddr3 / ddr3l 667 (ddr-1333) n/a vd_dsp iva_gclk 388.3 532 dsp_clk 600 750 (1) n/a in this table stands for not applicable. (2) maximum supported frequency is limited according to the device speed grade (see table 5-1 ). 5.5.3 maximum supported frequency device modules either receive their clock directly from an external clock input, directly from a pll, or from a prcm. table 5-5 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. to ensure proper module functionality, the device plls and dividers must be programmed not to exceed the maximum frequencies listed in this table. table 5-5. maximum supported frequency module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name aes1 aes1_l3_clk int 266 l4sec_l3_giclk core_x2_clk dpll_core aes2 aes2_l3_clk int 266 l4sec_l3_giclk core_x2_clk dpll_core atl atl_iclk_l3 int 266 atl_l3_giclk core_x2_clk dpll_core atlpclk func 266 atl_gfclk core_x2_clk dpll_core per_abe_x1_gf clk dpll_abe func_32k_clk osc0 hdmi_clk dpll_hdmi video1_clk dpll_video1 bb2d bb2d_fclk func 354.6 bb2d_gfclk bb2d_gfclk dpll_core bb2d_iclk int 266 dss_l3_giclk core_x2_clk dpll_core 128 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name counter_32k counter_32k_f clk func 0.032 func_32k_clk sys_clk1/610 osc0 counter_32k_ic lk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe ctrl_module_b andgap l3instr_ts_gcl k int 4.8 l3instr_ts_gclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe ctrl_module_c ore l4cfg_l4_giclk int 133 l4cfg_l4_giclk core_x2_clk dpll_core ctrl_module_ wkup wkupaon_giclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe dcan1 dcan1_fclk func 38.4 dcan1_sys_clk sys_clk1 osc0 sys_clk2 osc1 dcan1_iclk int 266 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe dcan2 dcan2_fclk func 38.4 dcan2_sys_clk sys_clk1 osc0 dcan2_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core des3des des_clk_l3 int 266 l4sec_l3_giclk core_x2_clk dpll_core dll emif_dll_fclk func emif_dll_fc lk emif_dll_gclk emif_dll_gclk dpll_ddr dll_aging fclk int 38.4 l3instr_dll_aging _gclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe dmm dmm_clk int 266 emif_l3_giclk core_x2_clk dpll_core dpll_debug sysclk int 38.4 emu_sys_clk sys_clk1 osc0 dsp1 dsp1_ficlk int & func dsp_clk dsp1_gfclk dsp_gfclk dpll_dsp 129 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name dss dss_hdmi_cec_ clk func 0.032 hdmi_cec_gfclk sys_clk1/610 osc0 dss_hdmi_phy_ clk func 48 hdmi_phy_gfclk func_192m_clk dpll_per dss_clk func 192 dss_gfclk dss_clk dpll_per hdmi_clkinp func 38.4 hdmi_dpll_clk sys_clk1 osc0 sys_clk2 osc1 dss_l3_iclk int 266 dss_l3_giclk core_x2_clk dpll_core video1_clkinp func 38.4 video1_dpll_clk sys_clk1 osc0 sys_clk2 osc1 video2_clkinp func 38.4 video2_dpll_clk sys_clk1 osc0 sys_clk2 osc1 dpll_dsi1_a_cl k1 func 209.3 n/a hdmi_clk dpll_hdmi video1_clkout1 dpll_video1 dpll_dsi1_b_cl k1 func 209.3 n/a video1_clkout3 dpll_video1 hdmi_clk dpll_hdmi dpll_abe_x2_cl k dpll_abe dpll_dsi1_c_cl k1 func 209.3 n/a hdmi_clk dpll_hdmi video1_clkout3 dpll_video1 dpll_hdmi_clk1 func 185.6 n/a hdmi_clk dpll_hdmi dss dispc lcd1_clk func 209.3 n/a dpll_dsi1_a_cl k1 see dss data in the rows above dss_clk lcd2_clk func 209.3 n/a dpll_dsi1_b_cl k1 dss_clk lcd3_clk func 209.3 n/a dpll_dsi1_c_cl k1 dss_clk f_clk func 209.3 n/a dpll_dsi1_a_cl k1 dpll_dsi1_b_cl k1 dpll_dsi1_c_cl k1 dss_clk dpll_hdmi_clk1 efuse_ctrl_cu st ocp_clk int 133 custefuse_l4_gicl k core_x2_clk dpll_core sys_clk func 38.4 custefuse_sys_gf clk sys_clk1 osc0 elm elm_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core emif_ocp_fw l3_clk int 266 emif_l3_giclk core_x2_clk dpll_core emif_phy1 emif_phy1_fclk func ddr emif_phy_gclk emif_phy_gclk dpll_ddr emif1 emif1_iclk int 266 emif_l3_giclk core_x2_clk dpll_core 130 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name gmac_sw cpts_rft_clk func 266 gmac_rft_clk per_abe_x1_gf clk dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi core_x2_clk dpll_core main_clk int 125 gmac_main_clk gmac_250m_clk dpll_gmac mhz_250_clk func 250 gmii_250mhz_clk gmii_250mhz_cl k dpll_gmac mhz_5_clk func 5 rgmii_5mhz_clk gmac_rmii_hs_c lk dpll_gmac mhz_50_clk func 50 rmii_50mhz_clk gmac_rmii_hs_c lk dpll_gmac rmii1_mhz_50_cl k func 50 rmii_50mhz_clk gmac_rmii_hs_c lk dpll_gmac rmii2_mhz_50_cl k func 50 rmii_50mhz_clk gmac_rmii_hs_c lk dpll_gmac gpio1 gpio1_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe gpio1_dbclk func 0.032 wkupaon_sys_gfc lk wkupaon_32k_g fclk osc0 gpio2 gpio2_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio2_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 gpio3 gpio3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio3_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 gpio4 gpio4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio4_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 pidbclk func 0.032 gpio_gfclk gpio5 gpio5_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio5_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 pidbclk func 0.032 gpio_gfclk gpio6 gpio6_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio6_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 pidbclk func 0.032 gpio_gfclk gpio7 gpio7_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio7_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 pidbclk func 0.032 gpio_gfclk gpio8 gpio8_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core gpio8_dbclk func 0.032 gpio_gfclk func_32k_clk osc0 pidbclk func 0.032 gpio_gfclk gpmc gpmc_fclk int 266 l3main1_l3_giclk core_x2_clk dpll_core 131 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name gpu gpu_fclk1 func gpu_clk gpu_core_gclk core_gpu_clk dpll_core per_gpu_clk dpll_per gpu_gclk dpll_gpu gpu_fclk2 func gpu_clk gpu_hyd_gclk core_gpu_clk dpll_core per_gpu_clk dpll_per gpu_gclk dpll_gpu gpu_iclk int 266 gpu_l3_giclk core_x2_clk dpll_core hdmi phy dss_hdmi_phy_ clk func 38.4 hdmi_phy_gfclk func_192m_clk dpll_per hdq1w hdq1w_iclk int & func 266 l4per_l3_giclk core_x2_clk dpll_core hdq1w_fclk func 12 per_12m_gfclk func_192m_clk dpll_per i2c1 i2c1_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core i2c1_fclk func 96 per_96m_gfclk func_192m_clk dpll_per i2c2 i2c2_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core i2c2_fclk func 96 per_96m_gfclk func_192m_clk dpll_per i2c3 i2c3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core i2c3_fclk func 96 per_96m_gfclk func_192m_clk dpll_per i2c4 i2c4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core i2c4_fclk func 96 per_96m_gfclk func_192m_clk dpll_per i2c5 i2c5_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core i2c5_fclk func 96 ipu_96m_gfclk func_192m_clk dpll_per i2c6 i2c6_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core i2c6_fclk func 96 ipu_96m_gfclk func_192m_clk dpll_per ieee1500_2_ocp pi_l3clk int & func 266 l3init_l3_giclk core_x2_clk dpll_core ipu1 ipu1_gfclk int & func 425.6 ipu1_gfclk dpll_abe_x2_cl k dpll_abe core_ipu_iss_b oost_clk dpll_core ipu2 ipu2_gfclk int & func 425.6 ipu2_gfclk core_ipu_iss_b oost_clk dpll_core iva iva_gclk int iva_gclk iva_gclk iva_gfclk dpll_iva kbd kbd_fclk func 0.032 wkupaon_sys_gfc lk wkupaon_32k_g fclk osc0 piclkkbd func 0.032 wkupaon_sys_gfc lk kbd_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 piclkocp int 38.4 wkupaon_giclk dpll_abe_x2_cl k dpll_abe l3_instr l3_clk int l3_clk l3instr_l3_giclk core_x2_clk dpll_core l3_main l3_clk1 int l3_clk l3main1_l3_giclk core_x2_clk dpll_core l3_clk2 int l3_clk l3instr_l3_giclk core_x2_clk dpll_core l4_cfg l4_cfg_clk int 133 l4cfg_l3_giclk core_x2_clk dpll_core l4_per1 l4_per1_clk int 133 l4per_l3_giclk core_x2_clk dpll_core l4_per2 l4_per2_clk int 133 l4per2_l3_giclk core_x2_clk dpll_core l4_per3 l4_per3_clk int 133 l4per3_l3_giclk core_x2_clk dpll_core 132 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name l4_wkup l4_wkup_clk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe mailbox1 mailbox1_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox2 mailbox2_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox3 mailbox3_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox4 mailbox4_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox5 mailbox5_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox6 mailbox6_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox7 mailbox7_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox8 mailbox8_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox9 mailbox9_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox10 mailbox10_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox11 mailbox11_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox12 mailbox12_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core mailbox13 mailbox13_flck int 266 l4cfg_l3_giclk core_x2_clk dpll_core 133 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcasp1 mcasp1_ahclkr func 100 mcasp1_ahclkr abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp1_ahclkx func 100 mcasp1_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp1_fclk func 192 mcasp1_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi mcasp1_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core 134 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcasp2 mcasp2_ahclkr func 100 mcasp2_ahclkr abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp2_ahclkx func 100 mcasp2_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp2_fclk func 192 mcasp2_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi mcasp2_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core 135 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcasp3 mcasp3_ahclkx func 100 mcasp3_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp3_fclk func 192 mcasp3_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp3_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core mcasp4 mcasp4_ahclkx func 100 mcasp4_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp4_fclk func 192 mcasp4_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp4_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core 136 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcasp5 mcasp5_ahclkx func 100 mcasp5_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp5_fclk func 192 mcasp5_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp5_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core mcasp6 mcasp6_ahclkx func 100 mcasp6_ahclkx abe_24m_gfclk dpll_abe func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl mlb_clk module mlb mlbp_clk module mlb abe_sys_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mcasp6_fclk func 192 mcasp6_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp6_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core 137 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcasp7 mcasp7_ahclkx func 100 mcasp7_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp7_fclk func 192 mcasp7_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp7_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core mcasp8 mcasp8_ahclkx func 100 mcasp8_ahclkx abe_24m_gfclk dpll_abe abe_sys_clk osc0 func_24m_gfcl k dpll_per atl_clk0 module atl atl_clk1 module atl atl_clk2 module atl atl_clk3 module atl sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 mlb_clk module mlb mlbp_clk module mlb mcasp8_fclk func 192 mcasp8_aux_gfclk per_abe_x1_gf clk dpll_abe video1_clk dpll_abe hdmi_clk dpll_hdmi mcasp8_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core mcspi1 spi1_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core spi1_fclk func 48 per_48m_gfclk per_48m_gfclk dpll_per mcspi2 spi2_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core spi2_fclk func 48 per_48m_gfclk per_48m_gfclk dpll_per mcspi3 spi3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core spi3_fclk func 48 per_48m_gfclk per_48m_gfclk dpll_per 138 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name mcspi4 spi4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core spi4_fclk func 48 per_48m_gfclk per_48m_gfclk dpll_per mlb_ss mlb_l3_iclk int 266 mlb_shb_l3_giclk core_x2_clk dpll_core mlb_l4_iclk int 133 mlb_spb_l4_giclk core_x2_clk dpll_core mlb_fclk func 266 mlb_sys_l3_gfclk core_x2_clk dpll_core csi2_0 ctrlclk int & func 96 lvdsrx_96m_gfclk func_192m_clk dpll_per cal_fclk int & func 266 cal_giclk core_iss_main_ clk dpll_core l3_iclk cm_core_aon mmc1 mmc1_clk_32k func 0.032 l3init_32k_gfclk func_32k_clk osc0 mmc1_fclk func 192 mmc1_gfclk func_192m_clk dpll_per 128 func_256m_clk dpll_per mmc1_iclk1 int 266 l3init_l3_giclk core_x2_clk dpll_core mmc1_iclk2 int 133 l3init_l4_giclk core_x2_clk dpll_core mmc2 mmc2_clk_32k func 0.032 l3init_32k_gfclk func_32k_clk osc0 mmc2_fclk func 192 mmc2_gfclk func_192m_clk dpll_per 128 func_256m_clk dpll_per mmc2_iclk1 int 266 l3init_l3_giclk core_x2_clk dpll_core mmc2_iclk2 int 133 l3init_l4_giclk core_x2_clk dpll_core mmc3 mmc3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core mmc3_clk_32k func 0.032 l4per_32k_gfclk func_32k_clk osc0 mmc3_fclk func 48 mmc3_gfclk func_192m_clk dpll_per 192 mmc4 mmc4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core mmc4_clk_32k func 0.032 l4per_32k_gfclk func_32k_clk osc0 mmc4_fclk func 48 mmc4_gfclk func_192m_clk dpll_per 192 mmu_edma mmu1_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core mmu_pciess mmu2_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core mpu mpu_clk int & func mpu_clk mpu_gclk mpu_gclk dpll_mpu mpu_emu_dbg fclk int 38.4 emu_sys_clk sys_clk1 osc0 mpu_gclk dpll_mpu ocmc_ram1 ocmc1_l3_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core ocmc_rom ocmc_l3_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core ocp_wp_noc piclkocpl3 int 266 l3instr_l3_giclk core_x2_clk dpll_core ocp2scp1 l4cfg1_adapte r_clkin int 133 l3init_l4_giclk core_x2_clk dpll_core ocp2scp2 l4cfg2_adapte r_clkin int 133 l4cfg_l4_giclk core_x2_clk dpll_core ocp2scp3 l4cfg3_adapte r_clkin int 133 l3init_l4_giclk core_x2_clk dpll_core 139 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name pciess1 pcie1_phy_wku p_clk func 0.032 pcie_32k_gfclk func_32k_clk dpll_core pcie_ss1_ficlk int 266 pcie_l3_giclk core_x2_clk pciephy_clk func 2500 pcie_phy_gclk pcie_phy_gclk apll_pcie pciephy_clk_di v func 1250 pcie_phy_div_gclk pcie_phy_div_g clk apll_pcie pcie1_ref_clki n func 34.3 pcie_ref_gfclk core_usb_otg_ ss_lfps_tx_clk dpll_core pcie1_pwr_clk func 38.4 pcie_sys_gfclk sys_clk1 osc0 pciess2 pcie2_phy_wku p_clk func 0.032 pcie_32k_gfclk func_32k_clk dpll_core pcie_ss2_ficlk func 266 pcie_l3_giclk core_x2_clk pciephy_clk func 2500 pcie_phy_gclk pcie_phy_gclk apll_pcie pciephy_clk_di v func 1250 pcie_phy_div_gclk pcie_phy_div_g clk apll_pcie pcie2_ref_clki n func 34.3 pcie_ref_gfclk core_usb_otg_ ss_lfps_tx_clk dpll_core pcie2_pwr_clk func 38.4 pcie_sys_gfclk sys_clk1 osc0 prcm_mpu 32k_clk func 0.032 func_32k_clk sys_clk1/610 osc0 sys_clk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe pwmss1 pwmss1_giclk int & func 266 l4per2_l3_giclk core_x2_clk dpll_core pwmss2 pwmss2_giclk int & func 266 l4per2_l3_giclk core_x2_clk dpll_core pwmss3 pwmss3_giclk int & func 266 l4per2_l3_giclk core_x2_clk dpll_core qspi qspi_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core qspi_fclk func 128 qspi_gfclk func_256m_clk dpll_per per_qspi_clk dpll_per rng rng_iclk int 266 l4sec_l3_giclk core_x2_clk dpll_core sar_rom prcm_rom_clo ck int 266 l4cfg_l3_giclk core_x2_clk dpll_core sdma sdma_fclk int & func 266 dma_l3_giclk core_x2_clk dpll_core sha2md51 sham_1_clk int 266 l4sec_l3_giclk core_x2_clk dpll_core sha2md52 sham_2_clk int 266 l4sec_l3_giclk core_x2_clk dpll_core sl2 iva_gclk int iva_gclk iva_gclk iva_gfclk dpll_iva smartreflex_c ore mclk int 133 coreaon_l4_giclk core_x2_clk dpll_core sysclk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe smartreflex_d sp mclk int 133 coreaon_l4_giclk core_x2_clk dpll_core sysclk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe 140 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name smartreflex_g pu mclk int 133 coreaon_l4_giclk core_x2_clk dpll_core sysclk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe smartreflex_iv ahd mclk int 133 coreaon_l4_giclk core_x2_clk dpll_core sysclk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe smartreflex_m pu mclk int 133 coreaon_l4_giclk core_x2_clk dpll_core sysclk func 38.4 wkupaon_iclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe spinlock spinlock_iclk int 266 l4cfg_l3_giclk core_x2_clk dpll_core timer1 timer1_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe timer1_fclk func 100 timer1_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer2 timer2_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer2_fclk func 100 timer2_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi 141 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name timer3 timer3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer3_fclk func 100 timer3_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer4 timer4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer4_fclk func 100 timer4_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer5 timer5_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core timer5_fclk func 100 timer5_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi clkoutmux[0] clkoutmux[0] 142 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name timer6 timer6_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core timer6_fclk func 100 timer6_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi clkoutmux[0] clkoutmux[0] timer7 timer7_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core timer7_fclk func 100 timer7_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi clkoutmux[0] clkoutmux[0] timer8 timer8_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core timer8_fclk func 100 timer8_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi clkoutmux[0] clkoutmux[0] 143 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name timer9 timer9_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer9_fclk func 100 timer9_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer10 timer10_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer10_fclk func 100 timer10_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer11 timer11_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core timer11_fclk func 100 timer11_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer12 timer12_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe timer12_fclk func 0.032 osc_32k_clk rc_clk rc oscillator 144 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name timer13 timer13_iclk int 266 l4per3_l3_giclk core_x2_clk dpll_core timer13_fclk func 100 timer13_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer14 timer14_iclk int 266 l4per3_l3_giclk core_x2_clk dpll_core timer14_fclk func 100 timer14_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi timer15 timer15_iclk int 266 l4per3_l3_giclk core_x2_clk dpll_core timer15_fclk func 100 timer15_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi 145 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name timer16 timer16_iclk int 266 l4per3_l3_giclk core_x2_clk dpll_core timer16_fclk func 100 timer16_gfclk sys_clk1 osc0 func_32k_clk osc0 sys_clk2 osc1 xref_clk0 xref_clk0 xref_clk1 xref_clk1 xref_clk2 xref_clk2 xref_clk3 xref_clk3 dpll_abe_x2_cl k dpll_abe video1_clk dpll_video1 hdmi_clk dpll_hdmi tpcc tpcc_gclk int 266 l3main1_l3_giclk core_x2_clk dpll_core tptc1 tptc0_gclk int 266 l3main1_l3_giclk core_x2_clk dpll_core tptc2 tptc1_gclk int 266 l3main1_l3_giclk core_x2_clk dpll_core uart1 uart1_fclk func 48 uart1_gfclk func_192m_clk dpll_per uart1_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core uart2 uart2_fclk func 48 uart2_gfclk func_192m_clk dpll_per uart2_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core uart3 uart3_fclk func 48 uart3_gfclk func_192m_clk dpll_per uart3_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core uart4 uart4_fclk func 48 uart4_gfclk func_192m_clk dpll_per uart4_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core uart5 uart5_fclk func 48 uart5_gfclk func_192m_clk dpll_per uart5_iclk int 266 l4per_l3_giclk core_x2_clk dpll_core uart6 uart6_fclk func 48 uart6_gfclk func_192m_clk dpll_per uart6_iclk int 266 ipu_l3_giclk core_x2_clk dpll_core uart7 uart7_fclk func 48 uart7_gfclk func_192m_clk dpll_per uart7_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core uart8 uart8_fclk func 48 uart8_gfclk func_192m_clk dpll_per uart8_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core uart9 uart9_fclk func 48 uart9_gfclk func_192m_clk dpll_per uart9_iclk int 266 l4per2_l3_giclk core_x2_clk dpll_core uart10 uart10_fclk func 48 uart10_gfclk func_192m_clk dpll_per uart10_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe usb1 usb1_miclk int 266 l3init_l3_giclk core_x2_clk dpll_core usb3phy_ref_c lk func 34.3 usb_lfps_tx_gfcl k core_usb_otg_ ss_lfps_tx_clk dpll_core usb2phy1_tref _clk func 38.4 usb_otg_ss_ref_c lk sys_clk1 osc0 usb2phy1_ref_ clk func 960 l3init_960m_gfclk l3init_960_gfcl k dpll_usb 146 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-5. maximum supported frequency (continued) module clock sources instance name input clock name clock type max. clock allowed (mhz) prcm clock name pll / osc / source clock name pll / osc / source name usb2 usb2_miclk int 266 l3init_l3_giclk core_x2_clk dpll_core usb2phy2_tref _clk func 38.4 usb_otg_ss_ref_c lk sys_clk1 osc0 usb2phy2_ref_ clk func 960 l3init_960m_gfclk l3init_960_gfcl k dpll_usb usb3 usb3_miclk int 266 l3init_l3_giclk core_x2_clk dpll_core usb3phy_pwrs_ clk func 38.4 usb_otg_ss_ref_c lk sys_clk1 osc0 usb_phy1_core usb2phy1_wkup _clk func 0.032 coreaon_32k_gfcl k sys_clk1/610 osc0 usb_phy2_core usb2phy2_wkup _clk func 0.032 coreaon_32k_gfcl k sys_clk1/610 osc0 usb_phy3_core usb3phy_wkup_ clk func 0.032 coreaon_32k_gfcl k sys_clk1/610 osc0 vcp1 vcp1_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core vcp2 vcp2_clk int 266 l3main1_l3_giclk core_x2_clk dpll_core vip1 l3_clk_proc_cl k int & func 266 vip1_gclk core_x2_clk dpll_core core_iss_main_ clk dpll_core vpe l3_clk_proc_cl k int & func 300 vpe_gclk core_iss_main_ clk dpll_core video1_clkout4 dpll_video1 wd_timer1 piocpclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe pitimerclk func 0.032 osc_32k_clk rc_clk rc oscillator wd_timer2 wd_timer2_iclk int 38.4 wkupaon_giclk sys_clk1 osc0 dpll_abe_x2_cl k dpll_abe wd_timer2_fcl k func 0.032 wkupaon_sys_gfc lk wkupaon_32k_g fclk 5.6 power consumption summary note maximum power consumption for this soc depends on the specific use conditions for the end system. contact your ti representative for assistance in estimating maximum power consumption for the end system use case. 5.7 electrical characteristics note the data specified in section 5.7 through section 5.7.3 are subject to change. 147 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note the interfaces or signals described in section 5.7 through section 5.7.3 correspond to the interfaces or signals available in multiplexing mode 0 (function 1). all interfaces or signals multiplexed on the balls described in these tables have the same dc electrical characteristics, unless multiplexing involves a phy/gpio combination in which case different dc electrical characteristics are specified for the different multiplexing modes (functions). table 5-6. lvcmos ddr dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in muxmode 0 (single-ended signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn0, ddr1_cke, ddr1_odt0, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst balls: aa23 / ac24 / ab24 / ad24 / ab23 / ac23 / ad23 / ae24 / aa24 / w25 / y23 / ad25 / ac25 / ab25 / aa25 / w24 / w23 / u25 / u24 / w21 / t22 / u22 / u23 / t21 / t23 / t25 / t24 / p21 / n21 / p22 / p23 / p24 / ac18 / ae19 / ad19 / ab19 / ad20 / ae20 / aa18 / aa20 / y21 / ac20 / aa21 / ac21 / ac22 / ac15 / ab15 / ac16 / ae23 / w22 / u21 / p25 / ae16 / aa16 / ab16 / ac19 / ab18 / ad18 / ad16 / ad17 / ae18 / ae17 driver mode v oh high-level output threshold (i oh = 0.1 ma) 0.9 vdds v v ol low-level output threshold (i ol = 0.1 ma) 0.1 vdds v c pad pad capacitance (including package capacitance) 3 pf z o output impedance (drive strength) l[2:0] = 000 (imp80) 80 l[2:0] = 001 (imp60) 60 l[2:0] = 010 (imp48) 48 l[2:0] = 011 (imp40) 40 l[2:0] = 100 (imp34) 34 single-ended receiver mode v ih high-level input threshold ddr3/ddr3l vref+0.1 vdds+0.2 v v il low-level input threshold ddr3/ddr3l -0.2 vref-0.1 v v cm input common-mode voltage vref -10%vdds vref+ 10%vdds v c pad pad capacitance (including package capacitance) 3 pf signal names in muxmode 0 (differential signals): ddr1_ck, ddr1_nck, ddr1_dqs[3:0], ddr1_dqsn[3:0] bottom balls: ad21 / ae21 / ad22 / ae22 / y24 / y25 / v24 / v25 / r24 / r25 driver mode v oh high-level output threshold (i oh = 0.1 ma) 0.9 vdds v v ol low-level output threshold (i ol = 0.1 ma) 0.1 vdds v c pad pad capacitance (including package capacitance) 3 pf z o output impedance (drive strength) l[2:0] = 000 (imp80) 80 l[2:0] = 001 (imp60) 60 l[2:0] = 010 (imp48) 48 l[2:0] = 011 (imp40) 40 l[2:0] = 100 (imp34) 34 148 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-6. lvcmos ddr dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter min nom max unit single-ended receiver mode v ih high-level input threshold ddr3/ddr3l vref+0.1 vdds+0.2 v v il low-level input threshold ddr3/ddr3l -0.2 vref-0.1 v v cm input common-mode voltage vref -10%vdds vref+ 10%vdds v c pad pad capacitance (including package capacitance) 3 pf differential receiver mode v swing input voltage swing ddr3/ddr3l 0.2 vdds+0.4 v v cm input common-mode voltage vref -10%vdds vref+ 10%vdds v c pad pad capacitance (including package capacitance) 3 pf (1) vdds in this table stands for corresponding power supply (i.e. vdds_ddr1). for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. (2) vref in this table stands for corresponding reference power supply (i.e. ddr1_vref0). for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. (3) for more information on the i/o cell configurations (i[2:0], sr[1:0]), see the chapter control module of the device trm. table 5-7. dual voltage lvcmos i 2 c dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in muxmode 0: i2c1_scl; i2c1_sda; i2c2_scl; i2c_sda balls: g22 / g23 / g21 / f23 i 2 c standard mode ? 1.8 v v ih input high-level threshold 0.7 vdds v v il input low-level threshold 0.3 vdds v v hys hysteresis 0.1 vdds v i in input current at each i/o pin with an input voltage between 0.1 vdds to 0.9 vdds 12 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 12 a c in input capacitance 10 pf v ol3 output low-level threshold open-drain at 3-ma sink current 0.2 vdds v i olmin low-level output current @v ol =0.2 vdds 3 ma t of output fall time from v ihmin to v ilmax with a bus capacitance cb from 5 pf to 400 pf 250 ns i 2 c fast mode ? 1.8 v v ih input high-level threshold 0.7 vdds v v il input low-level threshold 0.3 vdds v v hys hysteresis 0.1 vdds v i in input current at each i/o pin with an input voltage between 0.1 vdds to 0.9 vdds 12 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 12 a c in input capacitance 10 pf 149 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-7. dual voltage lvcmos i 2 c dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter min nom max unit v ol3 output low-level threshold open-drain at 3-ma sink current 0.2 vdds v i olmin low-level output current @v ol =0.2 vdds 3 ma t of output fall time from v ihmin to v ilmax with a bus capacitance cb from 10 pf to 400 pf 20+0.1 cb 250 ns i 2 c standard mode ? 3.3 v v ih input high-level threshold 0.7 vdds v v il input low-level threshold 0.3 vdds v v hys hysteresis 0.05 vdds v i in input current at each i/o pin with an input voltage between 0.1 vdds to 0.9 vdds 31 80 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 31 80 a c in input capacitance 10 pf v ol3 output low-level threshold open-drain at 3-ma sink current 0.4 v i olmin low-level output current @v ol =0.4v 3 ma i olmin low-level output current @v ol =0.6v for full drive load (400pf/400khz) 6 ma t of output fall time from v ihmin to v ilmax with a bus capacitance cb from 5 pf to 400 pf 250 ns i 2 c fast mode ? 3.3 v v ih input high-level threshold 0.7 vdds v v il input low-level threshold 0.3 vdds v v hys hysteresis 0.05 vdds v i in input current at each i/o pin with an input voltage between 0.1 vdds to 0.9 vddss 31 80 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 31 80 a c in input capacitance 10 pf v ol3 output low-level threshold open-drain at 3-ma sink current 0.4 v i olmin low-level output current @v ol =0.4v 3 ma i olmin low-level output current @v ol =0.6v for full drive load (400pf/400khz) 6 ma t of output fall time from v ihmin to v ilmax with a bus capacitance cb from 10 pf to 200 pf (proper external resistor value should be used as per i2c spec) 20+0.1 cb 250 ns output fall time from v ihmin to v ilmax with a bus capacitance cb from 300 pf to 400 pf (proper external resistor value should be used as per i2c spec) 40 290 (1) vdds in this table stands for corresponding power supply (i.e. vddshv3). for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. (2) for more information on the i/o cell configurations, see the control module section of the device trm. 150 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-8. iq1833 buffers dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in muxmode 0: tclk balls: k21 1.8-v mode v ih input high-level threshold (does not meet jedec v ih ) 0.75 vdds v v il input low-level threshold (does not meet jedec v il ) 0.25 vdds v v hys input hysteresis voltage 100 mv i in input current at each i/o pin 2 11 a c pad pad capacitance (including package capacitance) 1 pf 3.3-v mode v ih input high-level threshold (does not meet jedec v ih ) 2.0 v v il input low-level threshold (does not meet jedec v il ) 0.6 v v hys input hysteresis voltage 400 mv i in input current at each i/o pin 5 11 a c pad pad capacitance (including package capacitance) 1 pf (1) vdds in this table stands for corresponding power supply (i.e. vddshv3). for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. table 5-9. ihhv1833 buffers dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in muxmode 0: porz / wakeup3 / wakeup0 balls: ab10 / ac10 / f19 1.8-v mode v ih input high-level threshold 1.2 v v il input low-level threshold 0.4 v v hys input hysteresis voltage 40 mv i in input current at each i/o pin 0.02 1 a c pad pad capacitance (including package capacitance) 1 pf 3.3-v mode v ih input high-level threshold 1.2 v v il input low-level threshold 0.4 v v hys input hysteresis voltage 40 mv i in input current at each i/o pin 5 8 a c pad pad capacitance (including package capacitance) 1 pf table 5-10. lvcmos csi2 dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signals muxmode 0 : csi2_0_dx[2:0]; csi2_0_dy[2:0] bottom balls: ac1 / ab2 / ad1 / ac2 / ae2 / ad2 mipi d-phy mode low-power receiver (lp-rx) v ih input high-level voltage 880 1350 mv v il input low-level voltage 550 mv v ith input high-level threshold (1) 880 mv 151 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-10. lvcmos csi2 dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter min nom max unit v itl input low-level threshold (2) 550 mv v hys input hysteresis (3) 25 mv mipi d-phy mode ultralow power receiver (ulp-rx) v il input low-level voltage 300 mv v itl input low-level threshold (4) 300 mv v hys input hysteresis (3) 25 mv mipi d-phy mode high-speed receiver (hs-rx) v idth differential input high-level threshold 70 mv v idtl differential input low-level threshold ? 70 mv v idmax maximum differential input voltage (7) 270 mv v ihhs single-ended input high voltage (5) 460 mv v ilhs single-ended input low voltage (5) ? 40 mv v cmrxdc differential input common-mode voltage (5) (6) 70 330 mv z id differential input impedance 80 100 125 (1) v ith is the voltage at which the receiver is required to detect a high state in the input signal. (2) v itl is the voltage at which the receiver is required to detect a low state in the input signal. v itl is larger than the maximum single-ended line high voltage during hs transmission. therefore, both low-power (lp) receivers will detect low during hs signaling. (3) to reduce noise sensitivity on the received signal, the lp receiver is required to incorporate a hysteresis, v hyst . v hyst is the difference between the v ith threshold and the v itl threshold. (4) v itl is the voltage at which the receiver is required to detect a low state in the input signal. specification is relaxed for detecting 0 during ultralow power (ulp) state. the lp receiver is not required to detect hs single-ended voltage as 0 in this state. (5) excluding possible additional rf interference of 200 mv pp beyond 450 mhz. (6) this value includes a ground difference of 50 mv between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 mhz. (7) this number corresponds to the vod max transmitter. (8) common mode is defined as the average voltage level of x and y: v cmrx = (v x + v y ) / 2. (9) common mode ripple may be due to t r or t f and transmission line impairments in the pcb. (10) for more information regarding the pin name (or ball name) and corresponding signal name, see table 4-5 csi 2 signal descriptions . table 5-11. bmlb18 buffers dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in muxmode 0: mlbp_dat_n / mlbp_dat_p / mlbp_sig_n / mlbp_sig_p / mlbp_clk_n / mlbp_clk_p balls: t1 / t2 / u4 / t3 / u1 / u2 1.8-v mode v ih /v il input high-level threshold vcm 50mv v v hys input hysteresis voltage none mv v od differential output voltage (measured with 50ohm resistor between pad and padn) 300 500 mv v cm common mode output voltage 1 1.5 v c pad pad capacitance (including package capacitance) 4 pf table 5-12. dual voltage sdio1833 dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit signal names in mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0] bottom balls: u3 / v4 / v3 / v2 / w1 / v1 152 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-12. dual voltage sdio1833 dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter min nom max unit 1.8-v mode v ih input high-level threshold 1.27 v v il input low-level threshold 0.58 v v hys input hysteresis voltage 50 (2) mv i in input current at each i/o pin 30 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i(pad)) is measured and is reported as i oz 30 a i in with pulldown enabled input current at each i/o pin with weak pulldown enabled measured when pad = vdds 50 120 210 a i in with pullup enabled input current at each i/o pin with weak pullup enabled measured when pad = 0 60 120 200 a c pad pad capacitance (including package capacitance) 5 pf v oh output high-level threshold (i oh = 2 ma) 1.4 v v ol output low-level threshold (i ol = 2 ma) 0.45 v 3.3-v mode v ih input high-level threshold 0.625 vdds v v il input low-level threshold 0.25 vdds v v hys input hysteresis voltage 40 (2) mv i in input current at each i/o pin 110 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i(pad)) is measured and is reported as i oz 110 a i in with pulldown enabled input current at each i/o pin with weak pulldown enabled measured when pad = vdds 40 100 290 a i in with pullup enabled input current at each i/o pin with weak pullup enabled measured when pad = 0 10 100 290 a c pad pad capacitance (including package capacitance) 5 pf v oh output high-level threshold (i oh = 2 ma) 0.75 vdds v v ol output low-level threshold (i ol = 2 ma) 0.125 vdds v (1) vdds in this table stands for corresponding power supply (i.e. vddshv8). for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. (2) hysteresis is enabled/disabled with ctrl_core_control_hyst_1.sdcard_hyst register. table 5-13. dual voltage lvcmos dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter min nom max unit 1.8-v mode v ih input high-level threshold 0.65 vdds v v il input low-level threshold 0.35 vdds v v hys input hysteresis voltage 100 mv v oh output high-level threshold (i oh = 2 ma) vdds-0.45 v v ol output low-level threshold (i ol = 2 ma) 0.45 v 153 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-13. dual voltage lvcmos dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter min nom max unit i drive pin drive strength at pad voltage = 0.45v or vdds-0.45v 6 ma i in input current at each i/o pin 16 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 16 a i in with pulldown enabled input current at each i/o pin with weak pulldown enabled measured when pad = vdds 50 120 210 a i in with pullup enabled input current at each i/o pin with weak pullup enabled measured when pad = 0 60 120 200 a c pad pad capacitance (including package capacitance) 4 pf z o output impedance (drive strength) 40 3.3-v mode v ih input high-level threshold 2 v v il input low-level threshold 0.8 v v hys input hysteresis voltage 200 mv v oh output high-level threshold (i oh = 100 a) vdds-0.2 v v ol output low-level threshold (i ol = 100 a) 0.2 v i drive pin drive strength at pad voltage = 0.45v or vdds-0.45v 6 ma i in input current at each i/o pin 65 a i oz i oz (i pad current) for bidi cell. this current is contributed by the tristated driver leakage + input current of the rx + weak pullup/pulldown leakage. pad is swept from 0 to vdds and the max(i (pad) ) is measured and is reported as i oz 65 a i in with pulldown enabled input current at each i/o pin with weak pulldown enabled measured when pad = vdds 40 100 200 a i in with pullup enabled input current at each i/o pin with weak pullup enabled measured when pad = 0 10 100 290 a c pad pad capacitance (including package capacitance) 4 pf z o output impedance (drive strength) 40 (1) vdds in this table stands for corresponding power supply. for more information on the power supply name and the corresponding ball, see table 4-1 , power [11] column. 5.7.1 usbphy dc electrical characteristics note usb1 instance is compliant with the usb3.0 superspeed transmitter and receiver normative electrical parameters as defined in the usb3.0 specification rev 1.0 dated jun 6, 2011. note usb1 and usb2 electrical characteristics are compliant with usb2.0 specification rev 2.0 dated april 27, 2000 including ecns and errata as applicable. 154 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.7.2 hdmiphy dc electrical characteristics note the hdmiphy dc electrical characteristics are compliant with the hdmi 1.4a specification and are not reproduced here. 5.7.3 pciephy dc electrical characteristics note the pcie interfaces are compliant with the electrical parameters specified in pci express ? base specification revision 3.0. 5.8 vpp specifications for one-time programmable (otp) efuses this section specifies the operating conditions required for programming the otp efuses and is applicable only for high-security devices. table 5-14. recommended operating conditions for otp efuse programming over operating free-air temperature range (unless otherwise noted) parameter description min nom max unit vdd supply voltage range for the core domain during otp operation 1.11 1.15 1.2 v vpp supply voltage range for the efuse rom domain during normal operation nc v supply voltage range for the efuse rom domain during otp programming (1) (2) 1.8 v tj temperature (ambient) 0 25 85 o c (1) supply voltage range includes dc errors and peak-to-peak noise. ti power management solutions tlv70718 from the tlv707x family meet the supply voltage range needed for vpp. (2) during normal operation, no voltage should be applied to vpp. this can be typically achieved by disabling the regulator attached to the vpp terminal. for more details, see tlv707, tlv707p 200-ma, low-iq, low-noise, low-dropout regulator for portable devices . 5.8.1 hardware requirements the following hardware requirements must be met when programming keys in the otp efuses: ? the vpp power supply must be disabled when not programming otp registers. ? the vpp power supply must be ramped up after the proper device power-up sequence (for more details, see section 5.10.3 ). 5.8.2 programming sequence programming sequence for otp efuses: 1. power on the board per the power-up sequencing. no voltage should be applied on the vpp terminal during power up and normal operation. 2. load the otp write software required to program the efuse (contact your local ti representative for the otp software package). 3. apply the voltage on the vpp terminal according to the specification in table 5-14 . 4. run the software that programs the otp registers. 5. after validating the content of the otp registers, remove the voltage from the vpp terminal. 155 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.8.3 impact to your hardware warranty you accept that e-fusing the ti devices with security keys permanently alters them. you acknowledge that the e-fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step. further the ti device may fail to secure boot if the error code correction check fails for the production keys or if the image is not signed and optionally encrypted with the current active production keys. these types of situations will render the ti device inoperable and ti will be unable to confirm whether the ti devices conformed to their specifications prior to the attempted e-fuse. consequently, ti will have no liability (warranty or otherwise) for any ti devices that have been e-fused with security keys. 5.9 thermal resistance characteristics for cbd package for reliability and operability concerns, the maximum junction temperature of the device has to be at or below the t j value identified in section 5.4 , recommended operating conditions . a bci compact thermal model for this device is available and recommended for use when modeling thermal performance in a system. therefore, it is recommended to perform thermal simulations at the system level with the worst case device power consumption. 5.9.1 package thermal characteristics table 5-15 provides the thermal resistance characteristics for the package used on this device. note power dissipation of 3.0 w and an ambient temperature of 85 o c is assumed for cbd package. table 5-15. thermal resistance characteristics no. parameter description c/w (1) air flow (m/s) (2) t1 r jc junction-to-case 0.23 n/a t2 r jb junction-to-board 3.65 n/a t3 r ja junction-to-free air 12.8 0 t4 junction-to-moving air 10.4 0.5 t5 9.6 1 t6 8.8 2 t7 8.3 3 t8 jt junction-to-package top 0.1 0 t9 0.1 0.5 t10 0.1 1 t11 0.1 2 t12 0.1 3 t13 jb junction-to-board 3.7 0 t14 3.7 0.5 t15 3.6 1 t16 3.6 2 t17 3.5 3 (1) these measurements were conducted in a jedec defined 2s2p system (with the exception of the theta jc [r jc ] measurement, which was conducted in a jedec defined 1s0p system) and will change based on environment as well as application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environment conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages 156 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated ? jesd51-9, test boards for area array surface mount packages (2) m/s = meters per second 157 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10 timing requirements and switching characteristics 5.10.1 timing parameters and information the timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with jedec standard 100. to shorten the symbols, some of pin names and other related terminologies have been abbreviated as follows: table 5-16. timing parameters subscripts symbol parameter c cycle time (period) d delay time dis disable time en enable time h hold time su setup time start start bit t transition time v valid time w pulse duration (width) x unknown, changing, or don't care level f fall time h high l low r rise time v valid iv invalid ae active edge fe first edge le last edge z high impedance 158 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.1.1 parameter information figure 5-2. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. 5.10.1.1.1 1.8v and 3.3v signal transition levels all input and output timing parameters are referenced to v ref for both "0" and "1" logic levels. v ref = (vdd i/o)/2. figure 5-3. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 5-4. rise and fall transition time voltage reference levels 5.10.1.1.2 1.8v and 3.3v signal transition rates the default slewcontrol settings in each pad configuration register must be used to guaranteed timings, unless specific instructions otherwise are given in the individual timing sub-sections of the datasheet. all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). transmission line 4.0 pf 1.85 pf z0 = 50(see note) tester pin electronics data sheet timing reference point output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. a transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin. 42 3.5 nh device pin(see note) pm_tstcirc_prs403 v ref pm_io_volt_prs403 v = v max (or v max) ref il ol v = v min (or v min) ref ih oh pm_transvolt_prs403 159 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.1.1.3 timing parameters and board routing analysis the timing parameter values specified in this data manual do not include delays by board routes. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends using the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839 ). if needed, external logic hardware such as buffers may be used to compensate any timing differences. 5.10.2 interface clock specifications 5.10.2.1 interface clock terminology the interface clock is used at the system level to sequence the data and/or to control transfers accordingly with the interface protocol. 5.10.2.2 interface clock frequency the two interface clock characteristics are: ? the maximum clock frequency ? the maximum operating frequency the interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. this frequency defines the maximum limit supported by the device ic and does not take into account any system consideration (pcb, peripherals). the system designer will have to consider these system considerations and the device ic timing characteristics as well to define properly the maximum operating frequency that corresponds to the maximum frequency supported to transfer the data on this interface. 5.10.3 power supply sequences this section describes the power-up and power-down sequence required to ensure proper device operation. the power supply names described in this section comprise a superset of a family of compatible devices. some members of this family will not include a subset of these power supplies and their associated device modules. refer to the section 4.2 , pin attributes of the section 4 , terminal configuration and functions to determine which power supplies are applicable. 160 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-5 through figure 5-9 and associated notes described the device recommended power sequencing. figure 5-5. recommended power-up sequencing (1) t0 = 0ms, t1 = 0.55ms, t2 = 1.1ms, t3 = 1.65ms, t4 = 2.2ms, t5 = 2.75ms, t6 = 3.3ms, t7 = 6.9ms, t8 9ms. all ? tn ? markers show total elapsed time from t0. (2) terminology: ? v opr min = minimum operational voltage level that ensures device functionality and specified performance per section 5.4 , recommended operating conditions . ? ramp up = transition time from v off to v opr min (3) general timing diagram items: ? grey shaded areas show valid transition times for supplies between v opr min and v off . ? dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note. ? dashed vertical lines show approximate elapse times based upon ti recommended pmic power sequencer circuit performance. (4) vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached note 13 note 14 note 15 note 9 note 11 vdds18v, vdds_mlbp, vdds18v_ddr1 vdda_per, vdda_ddr, vdda_debug, vdda_core_gmac, vdda_gpu, vdda_video, vdda_osc, vdda_mpu_abe (vdda_pll group) vdds_ddr1, ddr1_vref0 vdd vdd_dsp vdda_usb1, vdda_usb2, vdda_hdmi, vdda_csi, vdda_pcie, vdda_usb3 (vdda_phy group) vddshv1, vddshv3, vddshv4, vddshv7, vddshv9, vddshv10, vddshv11 vdda33v_usb1, vdda33v_usb2 vddshv8 xi_osc0 resetn/porz sysboot[15:0] rstoutn sprs960_elch_04 valid config note 12 t0 t1 t2 t3 t4 t5 t6 t7 t8 note 4 note 5 note 6 note 7 note 8 note 10 161 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated until after vdds18v. the preferred sequence has vdda_* following vdds18v_* to ensure circuit components and pcb design do not cause an inadvertent violation. (5) vdds_ddr1 should not ramp-up before vdds18v_*. the preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit components and pcb design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr1 and vdda_* domains. ? for ddr2 mode of operation (1.8v), vdds_ddr1 supplies can be combined with all vdds18v_* supplies and ramped up together for simplified pdn and power sequencing. ? if vdds_ddr1 is combined with vdds18v_ddr1 but kept separate from vdds18v on board, then this combined 1.8v ddr supply can come up together or after the vdds18v supply. the 1.8v ddr supply should never ramp up before the vdds18v. (6) vdd should not ramp-up before vdds18v_* or vdds_ddr1 domains have reached v opr min . (7) vdd_dsp could ramp concurrently with vdd if design ensures: ? final vdd_dsp operational voltage will not be reached until after vdd. ? vdd_dsp maintains a voltage level at least 150mv less than vdd during entire ramp time. the preferred sequence has vdd_dsp following vdd to ensure circuit components and pcb design do not cause an inadvertent violation. (8) vdda_phy group: ? should ramp up concurrently or after vdda33v_usb[1-2] to avoid unintended current path between vdda_pcie to vdda33v_usb1 during power sequencing. ? could ramp up concurrently with vdda_pll group only if the vdda33v_usb1 power resource has an ? off impedance ? greater than 100 ? . (9) vddshv[1, 3-4, 7, 9-11] domains: ? if 1.8v i/o signaling is needed, then 1.8v must be sourced from common vdds18v supply and ramp up concurrently with vdds18v. ? if any 3.3v i/o signaling is needed, then the desired 3.3v vddshv[1, 3-4, 7, 9-11] rails must ramp up after vdd_dsp. (10) vdda33v_usb[1-2] domain should: ? ramp up before or concurrently with vdda_phy group if usb signaling is needed and to avoid unintended current path between vdda_pcie to vdda33v_usb[1-2] during power sequencing. ? connect to 3.3v vddshv[1, 3-4, 7, 9-11] common supply if usb signaling is not needed since usb analog power ball also supplies digital io buffers that must be powered during operation. (11) vddshv8 shows two ramp up options for 1.8v i/o or 3.3v i/o or sd card operation: ? if 1.8v i/o signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3v vddshv* rails. ? if 3.3v i/o signaling is needed, then vddshv8 must be combined with other 3.3v vddshv* rails. ? if sd card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3/1.8v) power source per sdio specifications and ramp up concurrently with 3.3v vddshv* rails. (12) porz must remain asserted low until both of the following conditions are met: ? minimum of 12 *p, where p = 1 / (sys_clk1/610), units in ns. ? all device supply rails reach stable operational levels. (13) setup time: sysboot[15:0] pins must be valid 2p (12) before porz is de-asserted high. (14) hold time: sysboot[15:0] pins must be valid 15p (12) after porz is de-asserted high. (15) rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3 reaches an operational level. if used as a peripheral component reset, it should be and gated with porz to avoid possible reset glitches during power up. 162 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-6. recommended power-down sequencing (1) t1 100 s; t2 = 500 s; t3 = 1.0 ms; t4 = 1.5ms; v1 = 2.7 v. all "tn" markers are intended to show total elapsed time, not interval times. (2) terminology: ? v opr min = minimum operational voltage level that ensures device functionality and specified performance in section 5.4 , recommended operating conditions . ? v off = off voltage level is defined to be less than 0.6 v where any current draw has no impact to poh. ? ramp down = transition time from v opr min to v off and is slew rate independent. (3) general timing diagram items: ? grey shaded areas show valid transition times for supplies between v opr min and v off . ? blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note. ? dashed vertical lines show approximate elapse times based upon ti recommended pmic power-down sequencer circuit performance. (4) porz must be asserted low for 100 s min to ensure soc is set to a safe functional state before any voltage begins to ramp down. (5) vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 v: ? must remain greater than 2.7 v to enable dual voltage gpio selector circuit operation for 100 s min after porz is asserted low. ? must be in first group of supplies ramping down after porz has been asserted low for 100 s min. ? must not exceed vdds18v by more than 2 v during ramp down, see figure 5-7 , "vdds18v versus vddshv[1, 3-4, 7, 9-11] discharge relationship". (6) vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 v must ramp down concurrently with vdds18v and be sourced from common vdds18v supply. (7) vddshv8 supporting sd card: vdda33v_usb1, vdda33v_usb2 vdda_usb1, vdda_usb2, vdda_hdmi, vdda_csi, vdda_pcie, vdda_usb3 (vdda_phy group) vdd_dsp vdd vdds18v, vdds_mlbp, vdds18v_ddr1 vdda_per, vdda_ddr, vdda_debug, vdda_core_gmac, vdda_gpu, vdda_video, vdda_osc, vdda_mpu_abe (vdda_pll group) vdds_ddr1, ddr1_vref0 xi_osc0 sprs960_elch_05 note 6 vddshv8 vddshv1, vddshv3, vddshv4, vddshv7, vddshv9,vddshv10, vddshv11 t0 t1 t2 t3 t4 v1 porz note 5 note 8note 9 note 12 note 13 note 14 note 10 note 11 note 7 note 4 note 13 163 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated ? must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 v) operation as required to be compliant to sdio specification ? must be in first group of supplies to ramp down after porz has been asserted low for 100 s min. ? if sdio operation is not needed, must be grouped and ramped down with other vddshv[1, 3-4, 7, 9-11] domains as noted above. (8) vdda33v_usb[1-2] domains: ? can start ramping down 100 s after low assertion of porz ? can ramp down concurrently or before vdda_phy group (9) vdda_phy domain group must ramp down concurrently or after vdda33v_usb[1-2]. (10) vdd_dsp domain can ramp down before or concurrently with vdd. (11) vdd must ramp down after or concurrently with vdd_dsp. (12) vdds_ddr1 domain: ? should ramp down after vdd begins ramping down. ? if ddr2 memory is used (requiring 1.8v supply), ? then vdds_ddr1 can be combined with vdds18v and vdds18v_ddr1 domains and sourced from a common supply. accordingly, all domains can ramp down concurrently with vdds18v. ? if vdds_ddr1 and vdds18v_ddr1 are combined but kept separate from vdds18v, then the combined 1.8v ddr supply can ramp down before or concurrently with vdds18v. (13) vdda_* domains: ? can ramp down before, concurrently or after vdds_ddr1, there is no dependency between these supplies. ? can ramp down before or concurrently with vdds18v. ? must satisfy the vdds18v versus vdda_* discharge relationship (see figure 5-9 ) if any of the vdda_* disable point is later or discharge rate is slower than vdds18v. (14) vdds18v domain: ? should maintain v opr min (v nom -5% = 1.71 v) until all other supplies start to ramp down. ? must satisfy the vdds18v versus vddshv[1, 3-4, 7, 9-11] discharge relationship (see figure 5-7 ) if any of the vddshv[1, 3-4, 7, 9-11] is operating at 3.3 v. ? must satisfy the vdds18v versus vdds_ddr1 discharge relationship ( see figure 5-8 ) if vdds_ddr1 discharge rate is slower than vdds18v. figure 5-7 describes vddshv[1, 3-4, 7, 9-11] supplies falling before vdds18v supplies delta. figure 5-7. vdds18v versus vddshv[1, 3-4, 7, 9-11] discharge relationship (1) v delta max = 2v. (2) if vddshv8 is powered by the same supply source as the other vddshv[1, 3-4, 7, 9-11] rails. vddshv1, vddshv3,vddshv4, vddshv7, vddshv9, vddshv10, vddshv11, vddshv8 (2) vdds18v vdelta (note1) sprs85v_elch_06 164 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated if vdds18v and vdds_ddr1 are disabled at the same time due to a loss of input power event or if vdds_ddr1 discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 v and ending with vdds_ddr1 dropping below 0.6 v is less than 10 ms ( figure 5-8 ). figure 5-8. vdds18v and vdds_ddr1 discharge relationship (1) (1) v1 > 1.0 v; v2 < 0.6 v; t1 < 10ms. figure 5-9. vdds18v and vdda_* discharge relationship (3) (1) vdda_* can be vdds18v, until vdds18v drops below 1.62 v. (2) vdds18v must be vdda_*, until vdds18v reaches 0.6 v. (3) v1 = 1.62 v; v2 < 0.6 v. sprs85v_elch_08 vdds18v v2 v1 note 1 note 2 vdda_* vdds18v vdds_ddr1 sprs85v_elch_07 v1 v2 t1 165 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-7 through figure 5-10 and associated notes described the device abrupt power down sequence. a ? loss of input power event ? occurs when the system ? s input power is unexpectedly removed. normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. this is the typical range of elapsed time available following a loss of power event, see section 7.3.7 for design recommendations. if sufficient elapse time is not provided, then an ? abrupt ? power-down sequence can be supported without impacting poh reliability if all of the following conditions are met ( figure 5-10 ). figure 5-10. abrupt power-down sequencing (1) (1) v1 = 2.7 v; v2 = 3.3 v; v3 = 2.0 v; v4 = v5 = v6 = 0.6 v; v7 = v8 = 1.62 v; v9 = 1.3 v; v10 = 1.0 v; v11 = 0.0 v; t delta1 > 100 s; t delta2 < 10 ms. (2) terminology: ? v opr min = minimum operational voltage level that ensures device functionality and specified performance in section 5.4 , recommended operating conditions . ? v off = off voltage level is defined to be less than 0.6 v, where any current draw has no impact to poh. ? ramp down = transition time from v opr min to v off and is slew rate independent. (3) general timing diagram items: ? grey shaded areas show valid transition times for supplies between v opr min and v off . ? dashed vertical lines show approximate elapse times based upon ti recommended pmic power-down sequencer circuit performance. (4) porz must be asserted low for 100 s min to ensure soc is set to a safe functional state before any voltage begins to ramp down. (5) vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 v: ? must remain greater than 2.7 v to enable dual voltage gpio selector circuit operation for 100 s min, after porz is asserted low. ? must not exceed vdds18v voltage level by more than 2v during ramp down, until vdds18v drops below v off (0.6 v). (6) vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 v must ramp down concurrently with vdds18v and be sourced from common vdds18v supply. (7) vddshv8 supporting sd card: ? must be in first group of supplies to ramp down after porz has been asserted low for 100 s min. ? must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 v) operation as required to be compliant to sdio specification. ? if sdio operation is not needed, must be grouped with other vddshv[1, 3-4, 7, 9-11] domains. sprs960_elch_09 vdd, vdd_dsp vdda_per, vdda_ddr, vdda_debug, vdda_core_gmac, vdda_gpu, vdda_video, vdda_osc, vdda_mpu_abe, vdda_usb[1-3], vdda_hdmi,vdda_csi, vdda_pcie, xi_osc0 porz v1 v3 v2 v7 v5 v10 v4 v11 v6 v9 v8 t delta2 vdds_ddr1, ddr1_vref0 t delta1 vddshv[ ] vddshv8 1, 3-4, 7, 9-11 (5)(7) (8) vdda33v_usb[1-2] vddshv[ ] 1, 3-4, 7, 9-11 (6) vdds18v, vdds_mlbp, vdds18v_ddr1 note 9, note 11 note 4 note 9note 9, note 10 note 12 166 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (8) vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after porz has been asserted low for 100 s min. (9) vdd_dsp, vdd, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 s low assertion of porz. (10) vdds_ddr1 domain: ? can remain at v opr min or a level greater than vdds18v during ramp down. ? elapsed time from vdds18v dropping below 1.0 v to vdds_ddr1 dropping below 0.6 v must not exceed 10 ms. (11) vdda_* domains: ? can start to ramp down before or concurrently with vdds18v. ? must not exceed vdds18v voltage level after vdds18v drops below 1.62 v until vdds18v drops below v off (0.6 v). (12) vdds18v domain should maintain a minimum level of 1.62 v (v nom ? 10%) until vdd_dsp and vdd start to ramp down. 5.10.4 clock specifications note for more information, see power reset and clock management / prcm environment / external clock signal and power reset / prcm functional description / prcm clock manager functional description section of the device trm. note audio back end (abe) module is not supported for this family of devices, but ? abe ? name is still present in some clock or dpll names. the device operation requires the following clocks: ? the system clocks, sys_clk1 (mandatory) and sys_clk2 (optional) are the main clock sources of the device. they supply the reference clock to the dplls as well as functional clock to several modules. the device also embeds an internal free-running 32-khz oscillator that is always active as long as the the wake-up (wkup) domain is supplied. figure 5-11 shows the external input clock sources and the output clocks to peripherals. 167 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-11. clock interface 5.10.4.1 input clocks / oscillators ? the source of the internal system clock (sys_clk1) could be either: ? a cmos clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the cmos clock case). ? a crystal oscillator clock managed by xi_osc0 and xo_osc0. ? the source of the internal system clock (sys_clk2) could be either: ? a cmos clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the cmos clock case). ? a crystal oscillator clock managed by xi_osc1 and xo_osc1. sys_clk1 is received directly from oscillator osc0. for more information about sys_clk1 see device trm, chapter: power, reset, and clock management. 5.10.4.1.1 osc0 external crystal an external crystal is connected to the device pins. figure 5-12 describes the crystal implementation. device clkout1 to quartz (from oscillator output). resetn rstoutn external reference clock [3:0]. for audio and other peripherals xref_clk1 sysboot[15:0] from quartz (19.2, 20 or 27 mhz)or from cmos square clock source (19.2, 20 or 27mhz). boot mode configuration xi_osc1 warm reset output. device reset input. porz power on reset. xi_osc0 xo_osc0 xo_osc1 from quartz (range from mhz) or from cmos square clock source(range from mhz). 19.2 to 32 12 to 38.4 to quartz (from oscillator output). clkout2 clkout3 xref_clk0 xref_clk2 xref_clk3 output clkout[3:1] clocks come from: ? either the input system clock and alternate clock (xi_osc0 or xi_osc1) ? or a core clock (from core output) ? or a 192-mhz clock (from per dpll output). 168 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-12. osc0 crystal implementation note the load capacitors, c f1 and c f2 in figure 5-12 , should be chosen such that the below equation is satisfied. c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins. figure 5-13. load capacitance equation the crystal must be in the fundamental mode of operation and parallel resonant. table 5-17 summarizes the required electrical constraints and table 5-21 table 5-17. osc0 crystal electrical characteristics name description min typ max unit f p parallel resonance crystal frequency 19.2, 20, 27 mhz c f1 c f1 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf c f2 c f2 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf esr(c f1 ,c f2 ) (1) crystal esr 100 c o crystal shunt capacitance esr = 30 esr = 40 19.2 mhz, 20 mhz, 27 mhz 7 pf esr = 50 19.2 mhz, 20 mhz 7 pf 27 mhz 5 pf esr = 60 19.2 mhz, 20 mhz 7 pf 27 mhz not supported - esr = 80 19.2 mhz, 20 mhz 5 pf 27 mhz not supported - esr = 100 19.2 mhz, 20 mhz 3 pf 27 mhz not supported - l m crystal motional inductance for f p = 20 mhz 10.16 mh c m crystal motional capacitance 3.42 ff vssa_osc0 device xo_osc0 xi_osc0 c f1 crystal rd c f2 (optional) sprs906_clk_03 c l = c c f1 2f (c +c ) 2 f1 f 169 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-17. osc0 crystal electrical characteristics (continued) name description min typ max unit t j(xiosc0) frequency accuracy (1) , xi_osc0 ethernet and mlb not used 200 ppm ethernet rgmii and rmii using derived clock 50 ethernet mii using derived clock 100 mlb using derived clock 50 (1) crystal characteristics should account for tolerance+stability+aging. when selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. table 5-18 details the switching characteristics of the oscillator and the requirements of the input clock. table 5-18. oscillator switching characteristics ? crystal mode name description min typ max unit f p oscillation frequency 19.2, 20, 27 mhz mhz t sx start-up time 4 ms 5.10.4.1.2 osc0 input clock a 1.8-v lvcmos-compatible clock input can be used instead of the internal oscillator to provide the sys_clk1 clock input to the system. the external connections to support this are shown in figure 5-14 . the xi_osc0 pin is connected to the 1.8-v lvcmos-compatible clock source. the xi_osc0 pin is left unconnected. the vssa_osc0 pin is connected to board ground (vss). figure 5-14. 1.8-v lvcmos-compatible clock input table 5-19 summarizes the osc0 input clock electrical characteristics. table 5-19. osc0 input clock electrical characteristics ? bypass mode name description min typ max unit f frequency 19.2, 20, 27 mhz c in input capacitance 2.184 2.384 2.584 pf i in input current (3.3v mode) 4 6 10 a vssa_osc0 device xo_osc0 xi_osc0 nc sprs906_clk_04 170 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-20 details the osc0 input clock timing requirements. table 5-20. osc0 input clock timing requirements name description min typ max unit ck0 1 / t c(xiosc0) frequency, xi_osc0 19.2, 20, 27 mhz ck1 t w(xiosc0) pulse duration, xi_osc0 low or high 0.45 t c(xiosc0) 0.55 t c(xiosc0) ns t j(xiosc0) period jitter (1) , xi_osc0 0.01 t c(xiosc0) ns t r(xiosc0) rise time, xi_osc0 5 ns t f(xiosc0) fall time, xi_osc0 5 ns t j(xiosc0) frequency accuracy (2) , xi_osc0 ethernet and mlb not used 200 ppm ethernet rgmii and rmii using derived clock 50 ethernet mii using derived clock 100 mlb using derived clock 50 (1) period jitter is meant here as follows: ? the maximum value is the difference between the longest measured clock period and the expected clock period ? the minimum value is the difference between the shortest measured clock period and the expected clock period (2) crystal characteristics should account for tolerance+stability+aging. figure 5-15. xi_osc0 input clock 5.10.4.1.3 auxiliary oscillator osc1 input clock sys_clk2 is received directly from oscillator osc1. for more information about sys_clk2 see device trm, chapter: power, reset, and clock management. 5.10.4.1.3.1 osc1 external crystal an external crystal is connected to the device pins. figure 5-16 describes the crystal implementation. figure 5-16. crystal implementation xi_osc0 ck0 ck1 ck1 sprs906_clk_05 xi_osc1 vssa_osc1 device xo_osc1 c f1 crystal rd c f2 (optional) sprs906_clk_06 171 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note the load capacitors, c f1 and c f2 in figure 5-16 , should be chosen such that the below equation is satisfied. c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins. figure 5-17. load capacitance equation the crystal must be in the fundamental mode of operation and parallel resonant. table 5-21 summarizes the required electrical constraints. table 5-21. osc1 crystal electrical characteristics name description min typ max unit f p parallel resonance crystal frequency range from 19.2 to 32 mhz c f1 c f1 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf c f2 c f2 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf esr(c f1 ,c f2 ) crystal esr 100 c o crystal shunt capacitance esr = 30 19.2 mhz f p 32 mhz 7 pf esr = 40 19.2 mhz f p 32 mhz 5 pf esr = 50 19.2 mhz f p 25 mhz 7 pf 25 mhz < f p 27 mhz 5 pf 27 mhz < f p 32 mhz not supported - esr = 60 19.2 mhz f p 23 mhz 7 pf 23 mhz < f p 25 mhz 5 pf 25 mhz < f p 32 mhz not supported - esr = 80 19.2 mhz f p 23 mhz 5 pf 23 mhz f p 25 mhz 3 pf 25 mhz < f p 32 mhz not supported - esr = 100 19.2 mhz f p 20 mhz 3 pf 20 mhz < f p 32 mhz not supported - l m crystal motional inductance for f p = 20 mhz 10.16 mh c m crystal motional capacitance 3.42 ff t j(xiosc1) frequency accuracy (1) , xi_osc1 ethernet and mlb not used 200 ppm ethernet rgmii and rmii using derived clock 50 ethernet mii using derived clock 100 mlb using derived clock 50 (1) crystal characteristics should account for tolerance+stability+aging. when selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. table 5-22 details the switching characteristics of the oscillator and the requirements of the input clock. table 5-22. oscillator switching characteristics ? crystal mode name description min typ max unit f p oscillation frequency range from 19.2 to 32 mhz c l = c c f1 2f (c +c ) 2 f1 f 172 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-22. oscillator switching characteristics ? crystal mode (continued) name description min typ max unit t sx start-up time 4 ms 5.10.4.1.3.2 osc1 input clock a 1.8-v lvcmos-compatible clock input can be used instead of the internal oscillator to provide the sys_clk2 clock input to the system. the external connections to support this are shown in, figure 5-18 . the xi_osc1 pin is connected to the 1.8-v lvcmos-compatible clock sources. the xo_osc1 pin is left unconnected. the vssa_osc1 pin is connected to board ground (vss). figure 5-18. 1.8-v lvcmos-compatible clock input table 5-23 summarizes the osc1 input clock electrical characteristics. table 5-23. osc1 input clock electrical characteristics ? bypass mode name description min typ max unit f frequency range from 12 to 38.4 mhz c in input capacitance 2.819 3.019 3.219 pf i in input current (3.3v mode) 4 6 10 a t sx start-up time (1) see (2) ms (1) to switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 s; however, if the chip comes from bypass mode to crystal mode the crystal will start-up after time mentioned in table 5-22 , t sx parameter. (2) before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in application mode and receives a wave. the switching time in this case is about 100 s. table 5-24 details the osc1 input clock timing requirements. table 5-24. osc1 input clock timing requirements name description min typ max unit ck0 1 / t c(xiosc1) frequency, xi_osc1 range from 12 to 38.4 mhz ck1 t w(xiosc1) pulse duration, xi_osc1 low or high 0.45 t c(xiosc1) 0.55 t c(xiosc1) ns t j(xiosc1) period jitter (1) , xi_osc1 0.01 t c(xiosc1) (3) ns t r(xiosc1) rise time, xi_osc1 5 ns t f(xiosc1) fall time, xi_osc1 5 ns vssa_osc1 device xo_osc1 xi_osc1 nc sprs906_clk_07 173 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-24. osc1 input clock timing requirements (continued) name description min typ max unit t j(xiosc1) frequency accuracy (2) , xi_osc1 ethernet and mlb not used 200 ppm ethernet rgmii and rmii using derived clock 50 ethernet mii using derived clock 100 mlb using derived clock 50 (1) period jitter is meant here as follows: ? the maximum value is the difference between the longest measured clock period and the expected clock period ? the minimum value is the difference between the shortest measured clock period and the expected clock period (2) crystal characteristics should account for tolerance+stability+aging. (3) the period jitter requirement for osc1 can be relaxed to 0.02 tc(xiosc1) under the following constraints: a.the osc1/sys_clk2 clock bypasses all device plls b.the osc1/sys_clk2 clock is only used to source the dss pixel clock outputs figure 5-19. xi_osc1 input clock 5.10.4.1.4 rc on-die oscillator clock note the osc_32k_clk clock, provided by the on-die 32k rc oscillator, inside of the soc, is not accurate 32khz clock. the frequency may significantly vary with temperature and silicon characteristics. for more information about osc_32k_clk see the device trm, chapter: power, reset, and clock management . 5.10.4.2 output clocks the device provides three output clocks. summary of these output clocks are as follows: ? clkout1 - device clock output 1. can be used as a system clock for other devices. the source of the clkout1 could be either: ? the input system clock and alternate clock (xi_osc0 or xi_osc1) ? core clock (from core output) ? 192-mhz clock (from per dpll output) ? clkout2 - device clock output 2. can be used as a system clock for other devices. the source of the clkout2 could be either: ? the input system clock and alternate clock (xi_osc0 or xi_osc1) ? core clock (from core output) ? 192-mhz clock (from per dpll output) ? clkout3 - device clock output 3. can be used as a system clock for other devices. the source of the clkout3 could be either: ? the input system clock and alternate clock (xi_osc0 or xi_osc1) ? core clock (from core output) ? 192-mhz clock (from per dpll output) for more information about output clocks see device trm, chapter: power, reset, and clock management . xi_osc1 ck0 ck1 ck1 sprs906_clk_08 174 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.4.3 dplls, dlls note for more information, see: ? power, reset, and clock management / clock management functional / internal clock sources / generators / generic dpll overview section and ? display subsystem / display subsystem overview section of the device trm. to generate high-frequency clocks, the device supports multiple on-chip dplls controlled directly by the prcm module. they are of two types: type a and type b dplls. ? they have their own independent power domain (each one embeds its own switch and can be controlled as an independent functional power domain) ? they are fed with always on system clock, with independent control per dpll. the different dplls managed by the prcm are listed below: ? dpll_mpu: it supplies the mpu subsystem clocking internally. ? dpll_iva: it feeds the iva subsystem clocking. ? dpll_core: it supplies all interface clocks and also few module functional clocks. ? dpll_per: it supplies several clock sources: a 192-mhz clock for the display functional clock, a 96-mhz functional clock to subsystems and peripherals. ? dpll_abe: it provides clocks to various modules within the device. ? dpll_usb: it provides 960m clock for usb modules (usb1/2/3/4). ? dpll_gmac: it supplies several clocks for the gigabit ethernet switch (gmac_sw). ? dpll_dsp: it feeds the dsp subsystem clocking. ? dpll_gpu: it supplies clock for the gpu subsystem. ? dpll_ddr: it generates clocks for the two external memory interface (emif) controllers and their associated emif phys. ? dpll_pcie_ref: it provides reference clock for the apll_pcie in pcie subsystem. ? apll_pcie: it feeds clocks for the device peripheral component interconnect express (pcie) controllers. note the following dplls are controlled by the clock manager located in the always-on core power domain (cm_core_aon): ? dpll_mpu, dpll_iva, dpll_core, dpll_abe, dpll_ddr, dpll_gmac, dpll_pcie_ref, dpll_per, dpll_usb, dpll_dsp, dpll_gpu, apll_pcie_ref. for more information on cm_core_aon and cm_core or prcm dplls, see the power, reset, and clock management (prcm) chapter of the device trm. the following dplls are not managed by the prcm: ? dpll_video1; (it is controlled from dss) ? dpll_hdmi; (it is controlled from dss) ? dpll_debug; (it is controlled from debugss) ? dpll_usb_otg_ss; (it is controlled from ocp2scp1) note for more information for not controlled from prcm dpll ? s see the related chapters in trm. 175 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.4.3.1 dpll characteristics the dpll has three relevant input clocks. one of them is the reference clock (clkinp) used to generated the synthesized clock but can also be used as the bypass clock whenever the dpll enters a bypass mode. it is therefore mandatory. the second one is a fast bypass clock (clkinpulow) used when selected as the bypass clock and is optional. the third clock (clkinphif) is explained in the next paragraph. the dpll has three output clocks (namely clkout, clkoutx2, and clkouthif). clkout and clkoutx2 run at the bypass frequency whenever the dpll enters a bypass mode. both of them are generated from the lock frequency divided by a post-divider (namely m2 post-divider). the third clock, clkouthif, has no automatic bypass capability. it is an output of a post-divider (m3 post-divider) with the input clock selectable between the internal lock clock (fdpll) and clkinphif input of the pll through an asynchronous multplexing. for more information, see the power reset controller management chapter of the device trm. table 5-25 summarizes dpll type described in section 5.10.4.3 , dplls, dlls specifications introduction. table 5-25. dpll control type dpll name type controlled by prcm dpll_abe table 5-26 (type a) yes (1) dpll_core table 5-26 (type a) yes (1) dpll_debugss table 5-26 (type a) no (2) dpll_dsp table 5-26 (type a) yes (1) dpll_gmac table 5-26 (type a) yes (1) dpll_hdmi table 5-27 (type b) no (2) dpll_iva table 5-26 (type a) yes (1) dpll_mpu table 5-26 (type a) yes (1) dpll_per table 5-26 (type a) yes (1) apll_pcie table 5-26 (type a) yes (1) dpll_pcie_ref table 5-27 (type b) yes (1) dpll_usb table 5-27 (type b) yes (1) dpll_usb_otg_ss table 5-27 (type b) no (2) dpll_video1 table 5-26 (type a) no (2) dpll_ddr table 5-26 (type a) yes (1) dpll_gpu table 5-26 (type a) yes (1) (1) dpll is in the always-on domain. (2) dpll is not controlled by the prcm. table 5-26 and table 5-27 summarize the dpll characteristics and assume testing over recommended operating conditions. table 5-26. dpll type a characteristics name description min typ max unit comments f input clkinp input frequency 0.032 52 mhz f inp f internal internal reference frequency 0.15 52 mhz refclk f clkinphif clkinphif input frequency 10 1400 mhz f inphif f clkinpulow clkinpulow input frequency 0.001 600 mhz bypass mode: f clkout = f clkinpulow / (m1 + 1) if ulowclken = 1 (6) f clkout clkout output frequency 20 (1) 1800 (2) mhz [m / (n + 1)] f inp [1 / m2] (in locked condition) 176 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-26. dpll type a characteristics (continued) name description min typ max unit comments f clkoutx2 clkoutx2 output frequency 40 (1) 2200 (2) mhz 2 [m / (n + 1)] f inp [1 / m2] (in locked condition) f clkouthif clkouthif output frequency 20 (3) 1400 (4) mhz f inphif / m3 if clkinphifsel = 1 40 (3) 2200 (4) mhz 2 [m / (n + 1)] f inp [1 / m3] if clkinphifsel = 0 f clkdcoldo dcoclkldo output frequency 40 2800 mhz 2 [m / (n + 1)] f inp (in locked condition) t lock frequency lock time 6 + 350 refclk s p lock phase lock time 6 + 500 refclk s t relock-l relock time ? frequency lock (5) (lp relock time from bypass) 6 + 70 refclk s dpll in lp relock time: lowcurrstdby = 1 p relock-l relock time ? phase lock (5) (lp relock time from bypass) 6 + 120 refclk s dpll in lp relock time: lowcurrstdby = 1 t relock-f relock time ? frequency lock (5) (fast relock time from bypass) 3.55 + 70 refclk s dpll in fast relock time: lowcurrstdby = 0 p relock-f relock time ? phase lock (5) (fast relock time from bypass) 3.55 + 120 refclk s dpll in fast relock time: lowcurrstdby = 0 (1) the minimum frequencies on clkout and clkoutx2 are assuming m2 = 1. for m2 > 1, the minimum frequency on these clocks will further scale down by factor of m2. (2) the maximum frequencies on clkout and clkoutx2 are assuming m2 = 1. (3) the minimum frequency on clkouthif is assuming m3 = 1. for m3 > 1, the minimum frequency on this clock will further scale down by factor of m3. (4) the maximum frequency on clkouthif is assuming m3 = 1. (5) relock time assumes typical operating conditions, 10 c maximum temperature drift. (6) bypass mode: f clkout = f inp if ulowclken = 0. for more information, see the device trm. table 5-27. dpll type b characteristics name description min typ max unit comments f input clkinp input clock frequency 0.62 60 mhz f inp f internal refclk internal reference clock frequency 0.62 2.5 mhz [1 / (n + 1)] f inp f clkinpulow clkinpulow bypass input clock frequency 0.001 600 mhz bypass mode: f clkout = f clkinpulow / (m1 + 1) if ulowclken = 1 (4) f clkldoout clkoutldo output clock frequency 20 (1) (5) 2500 (2) (5) mhz m / (n + 1)] f inp [1 / m2] (in locked condition) f clkout clkout output clock frequency 20 (1) (5) 1450 (2) (5) mhz [m / (n + 1)] f inp [1 / m2] (in locked condition) f clkdcoldo internal oscillator (dco) output clock frequency 750 (5) 1500 (5) mhz [m / (n + 1)] f inp (in locked condition) 1250 (5) 2500 (5) mhz t j clkoutldo period jitter ? 2.5% 2.5% the period jitter at the output clocks is 2.5% peak to peak clkout period jitter clkdcoldo period jitter t lock frequency lock time 350 refclks s p lock phase lock time 500 refclks s t relock-l relock time ? frequency lock (3) (lp relock time from bypass) 9 + 30 refclks s 177 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-27. dpll type b characteristics (continued) name description min typ max unit comments p relock-l relock time ? phase lock (3) (lp relock time from bypass) 9 + 125 refclks s (1) the minimum frequency on clkout is assuming m2 = 1. for m2 > 1, the minimum frequency on this clock will further scale down by factor of m2. (2) the maximum frequency on clkout is assuming m2 = 1. (3) relock time assumes typical operating conditions, 10 c maximum temperature drift. (4) bypass mode: f clkout = f inp if ulowclken = 0. for more information, see the device trm. (5) for output clocks, there are two frequency ranges according to the selfreqdco setting. for more information, see the device trm. 5.10.4.3.2 dll characteristics table 5-28 summarizes the dll characteristics and assumes testing over recommended operating conditions. table 5-28. dll characteristics name description min typ max unit f input input clock frequency (emif_dll_fclk) 266 mhz t lock lock time 50k cycles t relock relock time (a change of the dll frequency implies that dll must relock) 50k cycles 5.10.4.3.3 dpll and dll noise isolation note for more information on dpll and dll decoupling capacitor requirements, see the external capacitors / voltage decoupling capacitors / i/o and analog voltage decoupling / vdda power domain section. 5.10.5 recommended clock and control signal transition behavior all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. monotonic transitions are more easily guaranteed with faster switching signals. slower input transitions are more susceptible to glitches due to noise and special care should be taken for slow input clocks. 5.10.6 peripherals 5.10.6.1 timing test conditions all timing requirements and switching characteristics are valid over the recommended operating conditions unless otherwise specified. 5.10.6.2 virtual and manual i/o timing modes some of the timings described in the following sections require the use of virtual or manual i/o timing modes. table 5-29 provides a summary of the virtual and manual i/o timing modes across all device interfaces. the individual interface timing sections found later in this document provide the full description of each applicable virtual and manual i/o timing mode. refer to the "pad configuration" section of the trm for the procedure on implementing the virtual and manual timing modes in a system. table 5-29. modes summary virtual or manual io mode name data manual timing mode dpi video output 178 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-29. modes summary (continued) virtual or manual io mode name data manual timing mode no virtual or manual io timing mode required dpi3 video output default timings - rising-edge clock reference dss_virtual1 dpi3 video output default timings - falling-edge clock reference vout2_ioset1_manual1 dpi2 video output ioset1 alternate timings vout2_ioset1_manual2 dpi2 video output ioset1 default timings - rising-edge clock reference vout2_ioset1_manual3 dpi2 video output ioset1 default timings - falling-edge clock reference vout2_ioset1_manual4 dpi2 video output ioset1 manual4 timings vout2_ioset1_manual5 dpi2 video output ioset1 manual5 timings vout3_manual1 dpi3 video output alternate timings vout3_manual4 dpi3 video output manual4 timings vout3_manual5 dpi3 video output manual5 timings gpmc no virtual or manual io timing mode required gpmc asynchronous mode timings and synchronous mode - default timings gpmc_virtual1 gpmc synchronous mode - alternate timings mcasp no virtual or manual io timing mode required mcasp1 asynchronous and synchronous transmit timings mcasp1_virtual1_sync_rx see table 5-77 mcasp1_virtual2_async_rx see table 5-77 no virtual or manual io timing mode required mcasp2 asynchronous and synchronous transmit timings mcasp2_virtual1_sync_rx_80m see table 5-78 mcasp2_virtual2_async_rx see table 5-78 mcasp2_virtual3_sync_rx see table 5-78 mcasp2_virtual4_async_rx_80m see table 5-78 no virtual or manual io timing mode required mcasp3 synchronous transmit timings mcasp3_virtual2_sync_rx see table 5-79 no virtual or manual io timing mode required mcasp4 synchronous transmit timings mcasp4_virtual1_sync_rx see table 5-80 no virtual or manual io timing mode required mcasp5 synchronous transmit timings mcasp5_virtual1_sync_rx see table 5-81 no virtual or manual io timing mode required mcasp6 synchronous transmit timings mcasp6_virtual1_sync_rx see table 5-82 no virtual or manual io timing mode required mcasp7 synchronous transmit timings mcasp7_virtual2_sync_rx see table 5-83 no virtual or manual io timing mode required mcasp8 synchronous transmit timings mcasp8_virtual1_sync_rx see table 5-84 emmc/sd/sdio no virtual or manual io timing mode required mmc1 ds (pad loopback), hs (internal loopback and pad loopback), sdr12 (internal loopback and pad loopback), and sdr25 timings (internal loopback and pad loopback) timings mmc1_virtual1 mmc1 sdr50 (pad loopback) timings mmc1_virtual4 mmc1 ds (internal loopback) timings mmc1_virtual5 mmc1 sdr50 (internal loopback) timings mmc1_virtual6 mmc1 ddr50 (internal loopback) timings mmc1_manual1 mmc1 ddr50 (pad loopback) timings mmc1_manual2 mmc1 sdr104 timings no virtual or manual io timing mode required mmc2 standard (pad loopback), high speed (pad loopback) timings mmc2_virtual2 mmc2 standard (internal loopback), high speed (internal loopback) timings mmc2_manual1 mmc2 ddr (pad loopback) timings mmc2_manual2 mmc2 ddr (internal loopback manual) timings 179 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-29. modes summary (continued) virtual or manual io mode name data manual timing mode mmc2_manual3 mmc2 hs200 timings no virtual or manual io timing mode required mmc3 ds, sdr12, hs, sdr25 timings mmc3_manual1 mmc3 sdr50 timings no virtual or manual io timing mode required mmc4 ds, sdr12, hs, sdr25 timings qspi no virtual or manual io timing mode required qspi mode 3 timings qspi1_manual1 qspi mode 0 timings gmac no virtual or manual io timing mode required gmac mii0/1 timings gmac_rgmii0_manual1 gmac rgmii0 with transmit clock internal delay enabled gmac_rgmii1_manual1 gmac rgmii1 with transmit clock internal delay enabled gmac_rmii0_manual1 gmac rmii0 timings gmac_rmii1_manual1 gmac rmii1 timings vip vip_manual3 vin2a (ioset4/5/6) rise-edge capture mode timings vip_manual4 vin2b (ioset7/8/9) rise-edge capture mode timings vip_manual5 vin2a (ioset4/5/6) fall-edge capture mode timings vip_manual6 vin2b (ioset7/8/9) fall-edge capture mode timings vip_manual7 vin1a (ioset2) and vin2b (ioset1/10) rise-edge capture mode timings vip_manual9 vin1b (ioset6/7) rise-edge capture mode timings vip_manual10 vin2b (ioset2/11) rise-edge capture mode timings vip_manual11 vin2b (ioset2/11) fall-edge capture mode timings vip_manual12 vin1a (ioset2) and vin2b (ioset1/10) fall-edge capture mode timings vip_manual14 vin1b (ioset6/7) fall-edge capture mode timings vip_manual15 vin1a (ioset8/9/10) rise-edge capture mode timings vip_manual16 vin1a (ioset8/9/10) fall-edge capture mode timings pru-icss no virtual or manual io timing mode required all pru_icss modes not covered below pr1_pru1_dir_in_manual pru-icss1 pru1 direct input mode timings pr1_pru1_dir_out_manual pru-icss1 pru1 direct output mode timings pr1_pru1_par_cap_manual pru-icss1 pru1 parallel capture mode timings pr2_pru0_dir_in_manual2 pru-icss2 pru0 ioset2 direct input mode timings pr2_pru0_dir_out_manual2 pru-icss2 pru0 ioset2 direct output mode timings pr2_pru1_dir_in_manual1 pru-icss2 pru1 ioset1 direct input mode timings pr2_pru1_dir_in_manual2 pru-icss2 pru1 ioset2 direct input mode timings pr2_pru1_dir_out_manual1 pru-icss2 pru1 ioset1 direct output mode timings pr2_pru1_dir_out_manual2 pru-icss2 pru1 ioset2 direct output mode timings pr2_pru0_par_cap_manual2 pru-icss2 pru0 ioset2 parallel capture mode timings pr2_pru1_par_cap_manual1 pru-icss2 pru1 ioset1 parallel capture mode timings pr2_pru1_par_cap_manual2 pru-icss2 pru1 ioset2 parallel capture mode timings hdmi, emif, timers, i2c, hdq/1-wire, uart, mcspi, usb, pcie, dcan, gpio, kbd, pwm, jtag, tpiu, sdma, intc, mlb no virtual or manual io timing mode required all modes 5.10.6.3 vip the device includes 1 video input port (vip). table 5-30 , figure 5-20 and figure 5-21 present timings and switching characteristics of the vip. 180 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated caution the i/o timings provided in this section are valid only for vin1 and vin2 if signals within a single ioset are used. the iosets are defined in table 5-31 . table 5-30. timing requirements for vip (3) (4) (5) no. parameter description min max unit v1 t c(clk) cycle time, vinx_clki (3) (5) 6.06 (2) ns v2 t w(clkh) pulse duration, vinx_clki high (3) (5) 0.45 p (2) ns v3 t w(clkl) pulse duration, vinx_clki low (3) (5) 0.45 p (2) ns v4 t su(ctl/data-clk) input setup time, control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and data (vinx_dn) valid to vinx_clki transition (3) (4) (5) 3.11 (2) ns v6 t h(clk-ctl/data) input hold time, control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci) and data (vinx_dn) valid from vinx_clki transition (3) (4) (5) -0.05 (2) ns (1) for maximum frequency of 165 mhz. (2) p = vinx_clki period. (3) x in vinx = 1a, 1b, 2a, 2b. (4) n in dn = 0 to 7 when x = 1b, 2b. n = 0 to 23 when x = 1a, 2a. (5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1. figure 5-20. video input ports clock signal figure 5-21. video input ports timings vinx_clki v2 v1 v3 sprs906_timing_vip_01 vinx_clki (positive-edge clocking) v4 vinx_d[23:0]/sig v5 vinx_clki (negative-edge clocking) sprs8xx_vip_02 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 181 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 in table 5-31 and table 5-32 are presented the specific groupings of signals (ioset) for use with vin1 and vin2. table 5-31. vin1 iosets signals ioset2 ioset6 (1) ioset7 (1) ioset8 ioset9 ioset10 ball mux ball mux ball mux ball mux ball mux ball mux vin1a vin1a_clk0 g3 2 y5 9 j24 7 j24 7 vin1a_hsync0 k4 2 aa4 9 b14 7 b14 7 vin1a_vsync0 h1 2 ab1 9 d14 7 d14 7 vin1a_fld0 l3 2 c16 7 c16 7 vin1a_de0 j2 2 y6 9 c17 7 c17 7 vin1a_d0 f1 2 aa1 9 j25 7 b23 7 vin1a_d1 e2 2 y3 9 b22 7 b22 7 vin1a_d2 e1 2 w2 9 a23 7 a23 7 vin1a_d3 c1 2 aa3 9 a22 7 a22 7 vin1a_d4 d1 2 aa2 9 b21 7 b21 7 vin1a_d5 d2 2 y4 9 a21 7 a21 7 vin1a_d6 b1 2 y1 9 d19 7 d19 7 vin1a_d7 b2 2 y2 9 e19 7 e19 7 vin1a_d8 c2 2 f16 7 f16 7 vin1a_d9 d3 2 e16 7 e16 7 vin1a_d10 a2 2 e17 7 e17 7 vin1a_d11 b3 2 a19 7 a19 7 vin1a_d12 c3 2 b18 7 b18 7 vin1a_d13 c4 2 b16 7 b16 7 vin1a_d14 a3 2 b17 7 b17 7 vin1a_d15 b4 2 a18 7 a18 7 vin1a_d16 m1 2 vin1a_d17 m2 2 vin1a_d18 l2 2 vin1a_d19 l1 2 vin1a_d20 k3 2 vin1a_d21 k2 2 vin1a_d22 j1 2 vin1a_d23 k1 2 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 182 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-31. vin1 iosets (continued) signals ioset2 ioset6 (1) ioset7 (1) ioset8 ioset9 ioset10 ball mux ball mux ball mux ball mux ball mux ball mux vin1b vin1b_clk1 l5 5 j2 6 vin1b_hsync1 p3 5 k4 6 vin1b_vsync1 r2 5 h1 6 vin1b_fld1 n4 5 g1 6 vin1b_de1 p4 5 l3 6 vin1b_d0 l6 5 m1 6 vin1b_d1 n5 5 m2 6 vin1b_d2 n6 5 l2 6 vin1b_d3 t4 5 l1 6 vin1b_d4 t5 5 k3 6 vin1b_d5 n2 5 k2 6 vin1b_d6 p2 5 j1 6 vin1b_d7 n1 5 k1 6 (1) the ioset under this column is only applicable for pins with alternate functionality which allows either vin1 or vin2 signals to be mapped to the pins. these alternate functions are controlled via ctrl_core_vip_mux_select register. for more information on how to use these options, please refer to device trm, chapter control module, section pad configuration registers. table 5-32. vin2 iosets signals ioset1 ioset2 ioset4 ioset5 ioset6 ioset7 (1) ioset8 (1) ioset9 (1) ball mux ball mux ball mux ball mux ball mux ball mux ball mux ball mux vin2a vin2a_clk0 d8 0 d8 0 l5 4 vin2a_hsync0 e8 0 e8 0 p3 4 vin2a_vsync0 b8 0 b8 0 r2 4 vin2a_fld0 c7 0 b7 1 n4 4 vin2a_de0 b7 0 p4 4 vin2a_d0 c8 0 c8 0 l6 4 vin2a_d1 b9 0 b9 0 n5 4 vin2a_d2 a7 0 a7 0 n6 4 vin2a_d3 a9 0 a9 0 t4 4 vin2a_d4 a8 0 a8 0 t5 4 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 183 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-32. vin2 iosets (continued) signals ioset1 ioset2 ioset4 ioset5 ioset6 ioset7 (1) ioset8 (1) ioset9 (1) ball mux ball mux ball mux ball mux ball mux ball mux ball mux ball mux vin2a_d5 a11 0 a11 0 n2 4 vin2a_d6 f10 0 f10 0 p2 4 vin2a_d7 a10 0 a10 0 n1 4 vin2a_d8 b10 0 b10 0 p1 4 vin2a_d9 e10 0 e10 0 n3 4 vin2a_d10 d10 0 d10 0 r1 4 vin2a_d11 c10 0 c10 0 p5 4 vin2a_d12 b11 0 b11 0 vin2a_d13 d11 0 d11 0 vin2a_d14 c11 0 c11 0 vin2a_d15 b12 0 b12 0 vin2a_d16 a12 0 a12 0 vin2a_d17 a13 0 a13 0 vin2a_d18 e11 0 e11 0 vin2a_d19 f11 0 f11 0 vin2a_d20 b13 0 b13 0 vin2a_d21 e13 0 e13 0 vin2a_d22 c13 0 c13 0 vin2a_d23 d13 0 d13 0 vin2b vin2b_clk1 l4 6 h6 4 c7 2 c7 2 ab1 4 vin2b_hsync1 b6 6 b6 6 e8 3 e8 3 y5 4 vin2b_vsync1 a6 6 a6 6 b8 3 b8 3 y6 4 vin2b_fld1 h6 6 b7 2 vin2b_de1 h2 6 h2 6 b7 3 aa4 4 vin2b_d0 a4 6 a4 6 d13 2 d13 2 aa1 4 vin2b_d1 e7 6 e7 6 c13 2 c13 2 y3 4 vin2b_d2 d6 6 d6 6 e13 2 e13 2 w2 4 vin2b_d3 c5 6 c5 6 b13 2 b13 2 aa3 4 vin2b_d4 b5 6 b5 6 f11 2 f11 2 aa2 4 vin2b_d5 d7 6 d7 6 e11 2 e11 2 y4 4 vin2b_d6 c6 6 c6 6 a13 2 a13 2 y1 4 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 184 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-32. vin2 iosets (continued) signals ioset1 ioset2 ioset4 ioset5 ioset6 ioset7 (1) ioset8 (1) ioset9 (1) ball mux ball mux ball mux ball mux ball mux ball mux ball mux ball mux vin2b_d7 a5 6 a5 6 a12 2 a12 2 y2 4 (1) the ioset under this column is only applicable for pins with alternate functionality which allows either vin1 or vin2 signals to be mapped to the pins. these alternate functions are controlled via ctrl_core_vip_mux_select register. for more information on how to use these options, please refer to device trm, chapter control module, section pad configuration registers. note to configure the desired manual io timing mode the user must follow the steps described in section " manual io timing modes " of the device trm. the associated registers to configure are listed in the cfg register column. for more information please see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-33 manual functions mapping for vin2a (ioset4/5/6) for a definition of the manual modes. table 5-33 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-33. manual functions mapping for vin2a (ioset4/5/6) ball ball name vip_manual3 vip_manual5 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 0 1 4 p5 rmii_mhz_50_cl k 2616 1379 2798 1294 cfg_rmii_mhz_50_clk_in - - vin2a_d11 l6 mdio_d 2558 1105 2790 954 cfg_mdio_d_in - - vin2a_d0 l5 mdio_mclk 998 463 1029 431 cfg_mdio_mclk_in - - vin2a_clk0 n2 rgmii0_rxc 2658 862 2896 651 cfg_rgmii0_rxc_in - - vin2a_d5 p2 rgmii0_rxctl 2658 1628 2844 1518 cfg_rgmii0_rxctl_in - - vin2a_d6 n4 rgmii0_rxd0 2638 1123 2856 888 cfg_rgmii0_rxd0_in - - vin2a_fld0 n3 rgmii0_rxd1 2641 1737 2804 1702 cfg_rgmii0_rxd1_in - - vin2a_d9 p1 rgmii0_rxd2 2641 1676 2801 1652 cfg_rgmii0_rxd2_in - - vin2a_d8 n1 rgmii0_rxd3 2644 1828 2807 1790 cfg_rgmii0_rxd3_in - - vin2a_d7 t4 rgmii0_txc 2638 1454 2835 1396 cfg_rgmii0_txc_in - - vin2a_d3 t5 rgmii0_txctl 2672 1663 2831 1640 cfg_rgmii0_txctl_in - - vin2a_d4 r1 rgmii0_txd0 2604 1442 2764 1417 cfg_rgmii0_txd0_in - - vin2a_d10 r2 rgmii0_txd1 2683 1598 2843 1600 cfg_rgmii0_txd1_in - - vin2a_vsync0 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 185 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-33. manual functions mapping for vin2a (ioset4/5/6) (continued) ball ball name vip_manual3 vip_manual5 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 0 1 4 p3 rgmii0_txd2 2563 1483 2816 1344 cfg_rgmii0_txd2_in - - vin2a_hsync0 p4 rgmii0_txd3 2717 1461 2913 1310 cfg_rgmii0_txd3_in - - vin2a_de0 n5 uart3_rxd 2445 1145 2743 923 cfg_uart3_rxd_in - - vin2a_d1 n6 uart3_txd 2650 1197 2842 1080 cfg_uart3_txd_in - - vin2a_d2 d8 vin2a_clk0 0 0 0 0 cfg_vin2a_clk0_in vin2a_clk0 - - c8 vin2a_d0 1812 102 1936 0 cfg_vin2a_d0_in vin2a_d0 - - b9 vin2a_d1 1701 439 2229 10 cfg_vin2a_d1_in vin2a_d1 - - d10 vin2a_d10 1720 215 2031 0 cfg_vin2a_d10_in vin2a_d10 - - c10 vin2a_d11 1622 0 1702 0 cfg_vin2a_d11_in vin2a_d11 - - b11 vin2a_d12 1350 412 1819 0 cfg_vin2a_d12_in vin2a_d12 - - d11 vin2a_d13 1613 147 1476 260 cfg_vin2a_d13_in vin2a_d13 - - c11 vin2a_d14 1149 516 1701 0 cfg_vin2a_d14_in vin2a_d14 - - b12 vin2a_d15 1530 450 2021 0 cfg_vin2a_d15_in vin2a_d15 - - a12 vin2a_d16 1512 449 2044 11 cfg_vin2a_d16_in vin2a_d16 - - a13 vin2a_d17 1293 488 1839 5 cfg_vin2a_d17_in vin2a_d17 - - e11 vin2a_d18 2140 371 2494 0 cfg_vin2a_d18_in vin2a_d18 - - f11 vin2a_d19 2041 275 1699 611 cfg_vin2a_d19_in vin2a_d19 - - a7 vin2a_d2 1675 35 1736 0 cfg_vin2a_d2_in vin2a_d2 - - b13 vin2a_d20 1972 441 2412 88 cfg_vin2a_d20_in vin2a_d20 - - e13 vin2a_d21 1957 556 2391 161 cfg_vin2a_d21_in vin2a_d21 - - c13 vin2a_d22 2011 433 2446 102 cfg_vin2a_d22_in vin2a_d22 - - d13 vin2a_d23 1962 523 2395 145 cfg_vin2a_d23_in vin2a_d23 - - a9 vin2a_d3 1457 361 1943 0 cfg_vin2a_d3_in vin2a_d3 - - a8 vin2a_d4 1535 0 1601 0 cfg_vin2a_d4_in vin2a_d4 - - a11 vin2a_d5 1676 271 2052 0 cfg_vin2a_d5_in vin2a_d5 - - f10 vin2a_d6 1513 0 1571 0 cfg_vin2a_d6_in vin2a_d6 - - a10 vin2a_d7 1616 141 1855 0 cfg_vin2a_d7_in vin2a_d7 - - b10 vin2a_d8 1286 437 1224 618 cfg_vin2a_d8_in vin2a_d8 - - e10 vin2a_d9 1544 265 1373 509 cfg_vin2a_d9_in vin2a_d9 - - b7 vin2a_de0 1732 208 1949 0 cfg_vin2a_de0_in vin2a_de0 vin2a_fld0 - c7 vin2a_fld0 1461 562 1983 151 cfg_vin2a_fld0_in vin2a_fld0 - - e8 vin2a_hsync0 1877 0 1943 0 cfg_vin2a_hsync0_in vin2a_hsync0 - - copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 186 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-33. manual functions mapping for vin2a (ioset4/5/6) (continued) ball ball name vip_manual3 vip_manual5 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 0 1 4 b8 vin2a_vsync0 1566 0 1612 0 cfg_vin2a_vsync0_in vin2a_vsync0 - - manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-34 manual functions mapping for vin2b (ioset7/8/9) for a definition of the manual modes. table 5-34 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-34. manual functions mapping for vin2b (ioset7/8/9) ball ball name vip_manual4 vip_manual6 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 2 3 4 y5 gpio6_10 2829 884 3009 892 cfg_gpio6_10_in - - vin2b_hsync1 y6 gpio6_11 2648 1033 2890 1096 cfg_gpio6_11_in - - vin2b_vsync1 y2 mmc3_clk 2794 1074 2997 1089 cfg_mmc3_clk_in - - vin2b_d7 y1 mmc3_cmd 2789 1162 2959 1210 cfg_mmc3_cmd_in - - vin2b_d6 y4 mmc3_dat0 2689 1180 2897 1269 cfg_mmc3_dat0_in - - vin2b_d5 aa2 mmc3_dat1 2605 1219 2891 1219 cfg_mmc3_dat1_in - - vin2b_d4 aa3 mmc3_dat2 2616 703 2947 590 cfg_mmc3_dat2_in - - vin2b_d3 w2 mmc3_dat3 2760 1235 2931 1342 cfg_mmc3_dat3_in - - vin2b_d2 y3 mmc3_dat4 2757 880 2979 891 cfg_mmc3_dat4_in - - vin2b_d1 aa1 mmc3_dat5 2688 1177 2894 1262 cfg_mmc3_dat5_in - - vin2b_d0 aa4 mmc3_dat6 2638 1165 2894 1187 cfg_mmc3_dat6_in - - vin2b_de1 ab1 mmc3_dat7 995 182 1202 107 cfg_mmc3_dat7_in - - vin2b_clk1 a12 vin2a_d16 1423 0 1739 0 cfg_vin2a_d16_in vin2b_d7 - - a13 vin2a_d17 1253 0 1568 0 cfg_vin2a_d17_in vin2b_d6 - - e11 vin2a_d18 2080 0 2217 0 cfg_vin2a_d18_in vin2b_d5 - - f11 vin2a_d19 1849 0 2029 0 cfg_vin2a_d19_in vin2b_d4 - - b13 vin2a_d20 1881 50 2202 0 cfg_vin2a_d20_in vin2b_d3 - - e13 vin2a_d21 1917 167 2313 0 cfg_vin2a_d21_in vin2b_d2 - - c13 vin2a_d22 1955 79 2334 0 cfg_vin2a_d22_in vin2b_d1 - - d13 vin2a_d23 1899 145 2288 0 cfg_vin2a_d23_in vin2b_d0 - - b7 vin2a_de0 1568 261 2048 0 cfg_vin2a_de0_in vin2b_fld1 vin2b_de1 - c7 vin2a_fld0 0 0 0 0 cfg_vin2a_fld0_in vin2b_clk1 - - copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 187 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-34. manual functions mapping for vin2b (ioset7/8/9) (continued) ball ball name vip_manual4 vip_manual6 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 2 3 4 e8 vin2a_hsync0 1793 0 2011 0 cfg_vin2a_hsync0_in - vin2b_hsync1 - b8 vin2a_vsync0 1382 0 1632 0 cfg_vin2a_vsync0_in - vin2b_vsync1 - manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-35 manual functions mapping for vin1a (ioset2) and vin2b (ioset1/10) for a definition of the manual modes. table 5-35 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-35. manual functions mapping for vin1a (ioset2) and vin2b (ioset1/10) ball ball name vip_manual7 vip_manual12 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 2 6 m1 gpmc_a0 3080 1792 3376 1632 cfg_gpmc_a0_in vin1a_d16 - m2 gpmc_a1 2958 1890 3249 1749 cfg_gpmc_a1_in vin1a_d17 - j2 gpmc_a10 3073 1653 3388 1433 cfg_gpmc_a10_in vin1a_de0 - l3 gpmc_a11 3014 1784 3290 1693 cfg_gpmc_a11_in vin1a_fld0 - a4 gpmc_a19 1385 0 1246 0 cfg_gpmc_a19_in - vin2b_d0 l2 gpmc_a2 3041 1960 3322 1850 cfg_gpmc_a2_in vin1a_d18 - e7 gpmc_a20 859 0 720 0 cfg_gpmc_a20_in - vin2b_d1 d6 gpmc_a21 1465 0 1334 0 cfg_gpmc_a21_in - vin2b_d2 c5 gpmc_a22 1210 0 1064 0 cfg_gpmc_a22_in - vin2b_d3 b5 gpmc_a23 1111 0 954 0 cfg_gpmc_a23_in - vin2b_d4 d7 gpmc_a24 1137 0 1051 0 cfg_gpmc_a24_in - vin2b_d5 c6 gpmc_a25 1402 0 1283 0 cfg_gpmc_a25_in - vin2b_d6 a5 gpmc_a26 1298 0 1153 0 cfg_gpmc_a26_in - vin2b_d7 b6 gpmc_a27 934 0 870 0 cfg_gpmc_a27_in - vin2b_hsync1 l1 gpmc_a3 3019 2145 3296 2050 cfg_gpmc_a3_in vin1a_d19 - k3 gpmc_a4 3063 1981 3357 1829 cfg_gpmc_a4_in vin1a_d20 - k2 gpmc_a5 3021 1954 3304 1840 cfg_gpmc_a5_in vin1a_d21 - j1 gpmc_a6 3062 1716 3348 1592 cfg_gpmc_a6_in vin1a_d22 - k1 gpmc_a7 3260 1889 3583 1631 cfg_gpmc_a7_in vin1a_d23 - k4 gpmc_a8 3033 1702 3328 1547 cfg_gpmc_a8_in vin1a_hsync0 - h1 gpmc_a9 2991 1905 3281 1766 cfg_gpmc_a9_in vin1a_vsync0 - f1 gpmc_ad0 2907 1342 3181 1255 cfg_gpmc_ad0_in vin1a_d0 - copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 188 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-35. manual functions mapping for vin1a (ioset2) and vin2b (ioset1/10) (continued) ball ball name vip_manual7 vip_manual12 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 2 6 e2 gpmc_ad1 2858 1321 3132 1234 cfg_gpmc_ad1_in vin1a_d1 - a2 gpmc_ad10 2920 1384 3223 1204 cfg_gpmc_ad10_in vin1a_d10 - b3 gpmc_ad11 2719 1310 3019 1198 cfg_gpmc_ad11_in vin1a_d11 - c3 gpmc_ad12 2845 1135 3160 917 cfg_gpmc_ad12_in vin1a_d12 - c4 gpmc_ad13 2765 1225 3045 1119 cfg_gpmc_ad13_in vin1a_d13 - a3 gpmc_ad14 2845 1150 3153 952 cfg_gpmc_ad14_in vin1a_d14 - b4 gpmc_ad15 2766 1453 3044 1355 cfg_gpmc_ad15_in vin1a_d15 - e1 gpmc_ad2 2951 1296 3226 1209 cfg_gpmc_ad2_in vin1a_d2 - c1 gpmc_ad3 2825 1154 3121 997 cfg_gpmc_ad3_in vin1a_d3 - d1 gpmc_ad4 2927 1245 3246 1014 cfg_gpmc_ad4_in vin1a_d4 - d2 gpmc_ad5 2923 1251 3217 1098 cfg_gpmc_ad5_in vin1a_d5 - b1 gpmc_ad6 2958 1342 3238 1239 cfg_gpmc_ad6_in vin1a_d6 - b2 gpmc_ad7 2900 1244 3174 1157 cfg_gpmc_ad7_in vin1a_d7 - c2 gpmc_ad8 2845 1585 3125 1482 cfg_gpmc_ad8_in vin1a_d8 - d3 gpmc_ad9 2779 1343 3086 1223 cfg_gpmc_ad9_in vin1a_d9 - h2 gpmc_ben0 1555 0 1425 0 cfg_gpmc_ben0_in - vin2b_de1 h6 gpmc_ben1 1501 0 1397 0 cfg_gpmc_ben1_in - vin2b_fld1 l4 gpmc_clk 0 0 0 0 cfg_gpmc_clk_in - vin2b_clk1 a6 gpmc_cs1 1192 0 1102 0 cfg_gpmc_cs1_in - vin2b_vsync1 g3 gpmc_cs3 1324 374 1466 353 cfg_gpmc_cs3_in vin1a_clk0 - manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-36 manual functions mapping for vin1b (ioset6/7) for a definition of the manual modes. table 5-36 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-36. manual functions mapping for vin1b (ioset6/7) ball ball name vip_manual9 vip_manual14 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 5 6 m1 gpmc_a0 1873 702 2202 441 cfg_gpmc_a0_in - vin1b_d0 m2 gpmc_a1 1629 772 2057 413 cfg_gpmc_a1_in - vin1b_d1 j2 gpmc_a10 0 0 0 0 cfg_gpmc_a10_in - vin1b_clk1 l3 gpmc_a11 1851 1011 2126 856 cfg_gpmc_a11_in - vin1b_de1 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 189 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-36. manual functions mapping for vin1b (ioset6/7) (continued) ball ball name vip_manual9 vip_manual14 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 5 6 g1 gpmc_a12 2009 601 2289 327 cfg_gpmc_a12_in - vin1b_fld1 l2 gpmc_a2 1734 898 2131 573 cfg_gpmc_a2_in - vin1b_d2 l1 gpmc_a3 1757 1076 2106 812 cfg_gpmc_a3_in - vin1b_d3 k3 gpmc_a4 1794 893 2164 559 cfg_gpmc_a4_in - vin1b_d4 k2 gpmc_a5 1726 853 2120 523 cfg_gpmc_a5_in - vin1b_d5 j1 gpmc_a6 1792 612 2153 338 cfg_gpmc_a6_in - vin1b_d6 k1 gpmc_a7 2117 610 2389 304 cfg_gpmc_a7_in - vin1b_d7 k4 gpmc_a8 1758 653 2140 308 cfg_gpmc_a8_in - vin1b_hsync1 h1 gpmc_a9 1705 899 2067 646 cfg_gpmc_a9_in - vin1b_vsync1 l6 mdio_d 1945 671 2265 414 cfg_mdio_d_in vin1b_d0 - l5 mdio_mclk 255 119 337 0 cfg_mdio_mclk_in vin1b_clk1 - n2 rgmii0_rxc 2057 909 2341 646 cfg_rgmii0_rxc_in vin1b_d5 - p2 rgmii0_rxctl 2121 1139 2323 988 cfg_rgmii0_rxctl_in vin1b_d6 - n4 rgmii0_rxd0 2070 655 2336 340 cfg_rgmii0_rxd0_in vin1b_fld1 - n1 rgmii0_rxd3 2092 1357 2306 1216 cfg_rgmii0_rxd3_in vin1b_d7 - t4 rgmii0_txc 2088 1205 2328 1079 cfg_rgmii0_txc_in vin1b_d3 - t5 rgmii0_txctl 2143 1383 2312 1311 cfg_rgmii0_txctl_in vin1b_d4 - r2 rgmii0_txd1 2078 1189 2324 1065 cfg_rgmii0_txd1_in vin1b_vsync1 - p3 rgmii0_txd2 1928 1125 2306 763 cfg_rgmii0_txd2_in vin1b_hsync1 - p4 rgmii0_txd3 2255 971 2401 846 cfg_rgmii0_txd3_in vin1b_de1 - n5 uart3_rxd 1829 747 2220 400 cfg_uart3_rxd_in vin1b_d1 - n6 uart3_txd 2030 837 2324 568 cfg_uart3_txd_in vin1b_d2 - manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-37 manual functions mapping for vin2b (ioset2/11) for a definition of the manual modes. table 5-37 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-37. manual functions mapping for vin2b (ioset2/11) ball ball name vip_manual10 vip_manual11 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 4 6 a4 gpmc_a19 1600 943 2023 477 cfg_gpmc_a19_in - vin2b_d0 e7 gpmc_a20 1440 621 1875 136 cfg_gpmc_a20_in - vin2b_d1 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 190 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-37. manual functions mapping for vin2b (ioset2/11) (continued) ball ball name vip_manual10 vip_manual11 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 4 6 d6 gpmc_a21 1602 1066 2021 604 cfg_gpmc_a21_in - vin2b_d2 c5 gpmc_a22 1395 983 1822 519 cfg_gpmc_a22_in - vin2b_d3 b5 gpmc_a23 1571 716 2045 200 cfg_gpmc_a23_in - vin2b_d4 d7 gpmc_a24 1463 832 1893 396 cfg_gpmc_a24_in - vin2b_d5 c6 gpmc_a25 1426 1166 1842 732 cfg_gpmc_a25_in - vin2b_d6 a5 gpmc_a26 1362 1094 1797 584 cfg_gpmc_a26_in - vin2b_d7 b6 gpmc_a27 1283 809 1760 338 cfg_gpmc_a27_in - vin2b_hsync1 h2 gpmc_ben0 1978 780 2327 389 cfg_gpmc_ben0_in - vin2b_de1 h6 gpmc_ben1 0 0 0 0 cfg_gpmc_ben1_in vin2b_clk1 - a6 gpmc_cs1 1411 982 1857 536 cfg_gpmc_cs1_in - vin2b_vsync1 manual io timings modes must be used to guaranteed some io timings for vip1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-38 manual functions mapping for vin1a (ioset8/9/10) for a definition of the manual modes. table 5-38 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-38. manual functions mapping for vin1a (ioset8/9/10) ball ball name vip_manual15 vip_manual16 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 7 9 y5 gpio6_10 2131 2198 2170 2180 cfg_gpio6_10_in - vin1a_clk0 y6 gpio6_11 3720 2732 4106 2448 cfg_gpio6_11_in - vin1a_de0 c16 mcasp1_aclkx 2447 0 3042 0 cfg_mcasp1_aclkx_in vin1a_fld0 - d14 mcasp1_axr0 3061 0 3380 292 cfg_mcasp1_axr0_in vin1a_vsync0 - b14 mcasp1_axr1 3113 0 3396 304 cfg_mcasp1_axr1_in vin1a_hsync0 - b16 mcasp1_axr10 2803 0 3362 0 cfg_mcasp1_axr10_in vin1a_d13 - b18 mcasp1_axr11 3292 0 3357 546 cfg_mcasp1_axr11_in vin1a_d12 - a19 mcasp1_axr12 2854 0 3145 320 cfg_mcasp1_axr12_in vin1a_d11 - e17 mcasp1_axr13 2813 0 3229 196 cfg_mcasp1_axr13_in vin1a_d10 - e16 mcasp1_axr14 2471 0 3053 0 cfg_mcasp1_axr14_in vin1a_d9 - f16 mcasp1_axr15 2815 0 3225 201 cfg_mcasp1_axr15_in vin1a_d8 - a18 mcasp1_axr8 2965 0 3427 83 cfg_mcasp1_axr8_in vin1a_d15 - b17 mcasp1_axr9 3082 0 3253 440 cfg_mcasp1_axr9_in vin1a_d14 - c17 mcasp1_fsx 2898 0 3368 139 cfg_mcasp1_fsx_in vin1a_de0 - copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 191 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-38. manual functions mapping for vin1a (ioset8/9/10) (continued) ball ball name vip_manual15 vip_manual16 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 7 9 e19 mcasp2_aclkx 2413 0 2972 0 cfg_mcasp2_aclkx_in vin1a_d7 - a21 mcasp2_axr2 2478 0 3062 0 cfg_mcasp2_axr2_in vin1a_d5 - b21 mcasp2_axr3 2806 0 3175 242 cfg_mcasp2_axr3_in vin1a_d4 - d19 mcasp2_fsx 2861 78 2936 599 cfg_mcasp2_fsx_in vin1a_d6 - a22 mcasp3_aclkx 1583 0 1878 0 cfg_mcasp3_aclkx_in vin1a_d3 - b22 mcasp3_axr0 2873 0 3109 375 cfg_mcasp3_axr0_in vin1a_d1 - b23 mcasp3_axr1 1625 1400 2072 1023 cfg_mcasp3_axr1_in vin1a_d0 - a23 mcasp3_fsx 2792 0 3146 257 cfg_mcasp3_fsx_in vin1a_d2 - y2 mmc3_clk 3907 2744 4260 2450 cfg_mmc3_clk_in - vin1a_d7 y1 mmc3_cmd 3892 2768 4242 2470 cfg_mmc3_cmd_in - vin1a_d6 y4 mmc3_dat0 3786 2765 4156 2522 cfg_mmc3_dat0_in - vin1a_d5 aa2 mmc3_dat1 3673 2961 4053 2667 cfg_mmc3_dat1_in - vin1a_d4 aa3 mmc3_dat2 3818 2447 4209 2096 cfg_mmc3_dat2_in - vin1a_d3 w2 mmc3_dat3 3902 2903 4259 2672 cfg_mmc3_dat3_in - vin1a_d2 y3 mmc3_dat4 3905 2622 4259 2342 cfg_mmc3_dat4_in - vin1a_d1 aa1 mmc3_dat5 3807 2824 4167 2595 cfg_mmc3_dat5_in - vin1a_d0 aa4 mmc3_dat6 3724 2818 4123 2491 cfg_mmc3_dat6_in - vin1a_hsync0 ab1 mmc3_dat7 3775 2481 4159 2161 cfg_mmc3_dat7_in - vin1a_vsync0 j25 xref_clk0 1971 0 2472 0 cfg_xref_clk0_in vin1a_d0 - j24 xref_clk1 0 192 0 603 cfg_xref_clk1_in vin1a_clk0 - 192 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.4 dss two display parallel interfaces (dpi) channels are available in dss named dpi video output 2 and dpi video output 3. note the dpi video output i (i = 2, 3) interface is also referred to as vouti. every vout interface consists of: ? 24-bit data bus (data[23:0]) ? horizontal synchronization signal (hsync) ? vertical synchronization signal (vsync) ? data enable (de) ? field id (fid) ? pixel clock (clk) note for more information, see the display subsystem chapter of the device trm. caution the i/o timings provided in this section are valid only if signals within a single ioset are used. the iosets are defined in table 5-43 . caution the i/o timings provided in this section are valid only for some dss usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. caution all pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding ctrl_core_pad_*[slewcontrol] register field to slow (0b1). table 5-39 , table 5-40 through table 5-42 assume testing over the recommended operating conditions and electrical characteristic conditions. table 5-39. dpi video output i (i = 2, 3) default switching characteristics (1) (2) no. paramete r description mode min max unit d1 t c(clk) cycle time, output pixel clock vouti_clk dpi2/3 11.76 ns d2 t w(clkl) pulse duration, output pixel clock vouti_clk low p 0.5- 1 (1) ns d3 t w(clkh) pulse duration, output pixel clock vouti_clk high p 0.5- 1 (1) ns 193 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-39. dpi video output i (i = 2, 3) default switching characteristics (1) (2) (continued) no. paramete r description mode min max unit d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (vin2a_fld0 clock reference) -2.5 2.5 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (vin2a_fld0 clock reference) -2.5 2.5 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi3 -2.5 2.5 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi3 -2.5 2.5 ns (1) p = output vouti_clk period in ns. (2) all pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding ctrl_core_pad_*[slewcontrol] register field to slow (0b1). (3) serdes transceivers may be sensitive to the jitter profile of vouti_clk. see application note sprac62 for additional guidance. table 5-40. dpi video output i (i = 2, 3) alternate switching characteristics (2) no. paramete r description mode min max unit d1 t c(clk) cycle time, output pixel clock vouti_clk dpi2/3 6.06 ns d2 t w(clkl) pulse duration, output pixel clock vouti_clk low p 0.5- 1 (1) ns d3 t w(clkh) pulse duration, output pixel clock vouti_clk high p 0.5- 1 (1) ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (vin2a_fld0 clock reference) 1.51 4.55 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (vin2a_fld0 clock reference) 1.51 4.55 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi3 1.51 4.55 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi3 1.51 4.55 ns (1) p = output vouti_clk period in ns. (2) all pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding ctrl_core_pad_*[slewcontrol] register field to slow (0b1). (3) serdes transceivers may be sensitive to the jitter profile of vouti_clk. see application note sprac62 for additional guidance. table 5-41. dpi video output i (i = 2, 3) manual4 switching characteristics (2) no. parameter description mode min max unit d1 t c(clk) cycle time, output pixel clock vouti_clk dpi2/3 6.06 (3) ns d2 t w(clkl) pulse duration, output pixel clock vouti_clk low p*0.5-1 (1) ns d3 t w(clkh) pulse duration, output pixel clock vouti_clk high p*0.5-1 (1) ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi1 2.85 5.56 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi1 2.85 5.56 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (vin2a_fld0 clock reference) 2.85 5.56 ns 194 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-41. dpi video output i (i = 2, 3) manual4 switching characteristics (2) (continued) no. parameter description mode min max unit d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (vin2a_fld0 clock reference) 2.85 5.56 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (xref_clk2 clock reference) 2.85 5.56 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (xref_clk2 clock reference) 2.85 5.56 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi3 2.85 5.56 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi3 2.85 5.56 ns (1) p = output vouti_clk period in ns. (2) all pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding ctrl_core_pad_*[slewcontrol] register field to slow (0b1). (3) serdes transceivers may be sensitive to the jitter profile of vouti_clk. see application note sprac62 for additional guidance. table 5-42. dpi video output i (i = 2, 3) manual5 switching characteristics (2) no. parameter description mode min max unit d1 t c(clk) cycle time, output pixel clock vouti_clk dpi2/3 6.06 (3) ns d2 t w(clkl) pulse duration, output pixel clock vouti_clk low p*0.5-1 (1) ns d3 t w(clkh) pulse duration, output pixel clock vouti_clk high p*0.5-1 (1) ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi1 3.55 6.61 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi1 3.55 6.61 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (vin2a_fld0 clock reference) 3.55 6.61 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (vin2a_fld0 clock reference) 3.55 6.61 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi2 (xref_clk2 clock reference) 3.55 6.61 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi2 (xref_clk2 clock reference) 3.55 6.61 ns d5 t d(clk-ctlv) delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid dpi3 3.55 6.61 ns d6 t d(clk-dv) delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid dpi3 3.55 6.61 ns 195 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = output vouti_clk period in ns. (2) all pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding ctrl_core_pad_*[slewcontrol] register field to slow (0b1). (3) serdes transceivers may be sensitive to the jitter profile of vouti_clk. see application note sprac62 for additional guidance. figure 5-22. dpi video output (1) (2) (3) (1) the configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. (2) the polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the dss section of the device trm. (3) the vouti_clk frequency can be configured, refer to the dss section of the device trm. in table 5-43 are presented the specific groupings of signals (ioset) for use with vout2. table 5-43. vout2 iosets signals ioset1 ball mux vout2_d23 c8 4 vout2_d22 b9 4 vout2_d21 a7 4 vout2_d20 a9 4 vout2_d19 a8 4 vout2_d18 a11 4 vout2_d17 f10 4 vout2_d16 a10 4 vout2_d15 b10 4 vout2_d14 e10 4 vout2_d13 d10 4 vout2_d12 c10 4 vout2_d11 b11 4 vout2_d10 d11 4 vouti_clk vouti_vsync vouti_hsync vouti_d[23:0] vouti_de vouti_fld data_1 data_2 data_n odd even d1 d2 d3 d6 d6 d5 d6 d6 swps049-018 d4 vouti_clk falling-edge clock reference rising-edge clock reference 196 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-43. vout2 iosets (continued) signals ioset1 ball mux vout2_d9 c11 4 vout2_d8 b12 4 vout2_d7 a12 4 vout2_d6 a13 4 vout2_d5 e11 4 vout2_d4 f11 4 vout2_d3 b13 4 vout2_d2 e13 4 vout2_d1 c13 4 vout2_d0 d13 4 vout2_vsync b8 4 vout2_hsync e8 4 vout2_clk c7 4 vout2_fld d8 4 vout2_de b7 4 note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . virtual io timings modes must be used to guaranteed some io timings for vout3. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-44 virtual functions mapping for vout3 for a definition of the virtual modes. table 5-44 presents the values for delaymode bitfield. table 5-44. virtual functions mapping for dss vout3 ball ball name delay mode value muxmode dss_virtual1 3 b4 gpmc_ad15 14 vout3_d15 k4 gpmc_a8 15 vout3_hsync d1 gpmc_ad4 14 vout3_d4 f1 gpmc_ad0 14 vout3_d0 c4 gpmc_ad13 14 vout3_d13 l2 gpmc_a2 15 vout3_d18 e2 gpmc_ad1 14 vout3_d1 k3 gpmc_a4 15 vout3_d20 j1 gpmc_a6 15 vout3_d22 a3 gpmc_ad14 14 vout3_d14 m2 gpmc_a1 15 vout3_d17 g3 gpmc_cs3 15 vout3_clk h1 gpmc_a9 15 vout3_vsync b3 gpmc_ad11 14 vout3_d11 b1 gpmc_ad6 14 vout3_d6 e1 gpmc_ad2 14 vout3_d2 197 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-44. virtual functions mapping for dss vout3 (continued) ball ball name delay mode value muxmode dss_virtual1 3 c1 gpmc_ad3 14 vout3_d3 k1 gpmc_a7 15 vout3_d23 l1 gpmc_a3 15 vout3_d19 a2 gpmc_ad10 14 vout3_d10 b2 gpmc_ad7 14 vout3_d7 j2 gpmc_a10 15 vout3_de k2 gpmc_a5 15 vout3_d21 c2 gpmc_ad8 14 vout3_d8 d2 gpmc_ad5 14 vout3_d5 m1 gpmc_a0 15 vout3_d16 c3 gpmc_ad12 14 vout3_d12 l3 gpmc_a11 15 vout3_fld d3 gpmc_ad9 14 vout3_d9 note to configure the desired manual io timing mode the user must follow the steps described in section " manual io timing modes " of the device trm. the associated registers to configure are listed in the cfg register column. for more information please see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for vout2. see table 5-29 , modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-45 , manual functions mapping for dss vout2 ioset1 for a definition of the manual modes. table 5-45 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 198 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-45. manual functions mapping for dss vout2 ioset1 ball ball name vout2_ioset1 _manual1 vout2_ioset1 _manual2 vout2_ioset1 _manual3 vout2_ioset1 _manual4 vout2_ioset1 _manual5 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 4 d8 vin2a_clk0 2571 0 1059 0 1025 0 4110 0 4980 0 cfg_vin2a_clk0_out vout2_fld c8 vin2a_d0 2124 0 589 0 577 0 3613 0 4483 0 cfg_vin2a_d0_out vout2_d23 b9 vin2a_d1 2103 0 568 0 557 0 3442 0 4312 0 cfg_vin2a_d1_out vout2_d22 d10 vin2a_d10 2091 0 557 0 545 0 3430 0 4200 0 cfg_vin2a_d10_out vout2_d13 c10 vin2a_d11 2142 0 608 0 596 0 3481 0 4251 0 cfg_vin2a_d11_out vout2_d12 b11 vin2a_d12 2920 385 1816 255 1783 276 3943 601 4713 601 cfg_vin2a_d12_out vout2_d11 d11 vin2a_d13 2776 322 1872 192 1838 213 3799 538 4669 538 cfg_vin2a_d13_out vout2_d10 c11 vin2a_d14 2904 0 1769 0 1757 0 3869 174 4739 174 cfg_vin2a_d14_out vout2_d9 b12 vin2a_d15 2670 257 1665 127 1632 148 3792 473 4662 473 cfg_vin2a_d15_out vout2_d8 a12 vin2a_d16 2814 155 1908 31 1878 43 3837 371 4707 371 cfg_vin2a_d16_out vout2_d7 a13 vin2a_d17 3002 199 1897 69 1865 89 4024 415 4894 415 cfg_vin2a_d17_out vout2_d6 e11 vin2a_d18 1893 0 358 0 347 0 3432 0 4302 0 cfg_vin2a_d18_out vout2_d5 f11 vin2a_d19 1698 0 163 0 151 0 3237 0 4007 0 cfg_vin2a_d19_out vout2_d4 a7 vin2a_d2 2193 0 658 0 646 0 3531 0 4401 0 cfg_vin2a_d2_out vout2_d21 b13 vin2a_d20 1736 0 202 0 190 0 3075 0 3945 0 cfg_vin2a_d20_out vout2_d3 e13 vin2a_d21 1636 0 101 0 89 0 3074 0 3944 0 cfg_vin2a_d21_out vout2_d2 c13 vin2a_d22 1628 0 93 0 81 0 3266 0 4036 0 cfg_vin2a_d22_out vout2_d1 d13 vin2a_d23 1538 0 0 0 0 0 2968 0 3838 0 cfg_vin2a_d23_out vout2_d0 a9 vin2a_d3 1997 0 462 0 450 0 3335 0 4205 0 cfg_vin2a_d3_out vout2_d20 a8 vin2a_d4 2528 0 993 0 982 0 3867 0 4537 0 cfg_vin2a_d4_out vout2_d19 a11 vin2a_d5 2038 0 503 0 492 0 3577 0 4347 0 cfg_vin2a_d5_out vout2_d18 f10 vin2a_d6 1746 0 211 0 200 0 3285 0 4055 0 cfg_vin2a_d6_out vout2_d17 a10 vin2a_d7 2213 0 678 0 666 0 3552 0 4272 0 cfg_vin2a_d7_out vout2_d16 b10 vin2a_d8 2268 0 733 0 721 0 3607 0 4277 0 cfg_vin2a_d8_out vout2_d15 e10 vin2a_d9 2170 0 635 0 623 0 3509 0 4379 0 cfg_vin2a_d9_out vout2_d14 b7 vin2a_de0 2102 0 568 0 556 0 3841 0 4611 0 cfg_vin2a_de0_out vout2_de c7 vin2a_fld0 0 983 1398 1185 1385 1202 0 994 0 994 cfg_vin2a_fld0_out vout2_clk e8 vin2a_hsy nc0 2482 0 974 0 936 0 4021 0 4891 0 cfg_vin2a_hsync0_ out vout2_hsync b8 vin2a_vsy nc0 2296 0 784 0 750 0 3935 0 4805 0 cfg_vin2a_vsync0_o ut vout2_vsync copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 199 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 200 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated manual io timings modes must be used to guaranteed some io timings for vout3. see table 5-29 , modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-46 , manual functions mapping for dss vout3 for a definition of the manual modes. table 5-46 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-46. manual functions mapping for dss vout3 ball ball name vout3_manual1 vout3_manual4 vout3_manual5 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 3 m1 gpmc_a0 2395 0 3909 0 4779 0 cfg_gpmc_a0_out vout3_d16 m2 gpmc_a1 2412 0 3957 0 4827 0 cfg_gpmc_a1_out vout3_d17 j2 gpmc_a10 2473 0 3980 0 4850 0 cfg_gpmc_a10_out vout3_de l3 gpmc_a11 2906 0 4253 0 5123 0 cfg_gpmc_a11_out vout3_fld l2 gpmc_a2 2360 0 3873 0 4743 0 cfg_gpmc_a2_out vout3_d18 l1 gpmc_a3 2391 0 4112 0 4982 0 cfg_gpmc_a3_out vout3_d19 k3 gpmc_a4 2626 0 4336 0 5206 0 cfg_gpmc_a4_out vout3_d20 k2 gpmc_a5 2338 0 3840 0 4710 0 cfg_gpmc_a5_out vout3_d21 j1 gpmc_a6 2374 0 3913 0 4783 0 cfg_gpmc_a6_out vout3_d22 k1 gpmc_a7 2432 0 3947 0 4817 0 cfg_gpmc_a7_out vout3_d23 k4 gpmc_a8 3155 0 4309 105 5179 105 cfg_gpmc_a8_out vout3_hsync h1 gpmc_a9 2309 0 3842 0 4712 0 cfg_gpmc_a9_out vout3_vsync f1 gpmc_ad0 2360 0 3652 0 4522 0 cfg_gpmc_ad0_out vout3_d0 e2 gpmc_ad1 2420 0 3762 0 4632 0 cfg_gpmc_ad1_out vout3_d1 a2 gpmc_ad10 2235 0 3456 0 4326 0 cfg_gpmc_ad10_out vout3_d10 b3 gpmc_ad11 2253 0 3584 0 4454 0 cfg_gpmc_ad11_out vout3_d11 c3 gpmc_ad12 1949 427 3589 0 4459 0 cfg_gpmc_ad12_out vout3_d12 c4 gpmc_ad13 2318 0 3547 0 4417 0 cfg_gpmc_ad13_out vout3_d13 a3 gpmc_ad14 2123 0 3302 0 4172 0 cfg_gpmc_ad14_out vout3_d14 b4 gpmc_ad15 2195 29 3532 0 4402 0 cfg_gpmc_ad15_out vout3_d15 e1 gpmc_ad2 2617 0 3859 0 4729 0 cfg_gpmc_ad2_out vout3_d2 c1 gpmc_ad3 2350 0 3590 0 4460 0 cfg_gpmc_ad3_out vout3_d3 d1 gpmc_ad4 2324 0 3534 0 4404 0 cfg_gpmc_ad4_out vout3_d4 d2 gpmc_ad5 2371 0 3609 0 4479 0 cfg_gpmc_ad5_out vout3_d5 b1 gpmc_ad6 2231 0 3416 0 4286 0 cfg_gpmc_ad6_out vout3_d6 b2 gpmc_ad7 2440 0 3661 0 4531 0 cfg_gpmc_ad7_out vout3_d7 c2 gpmc_ad8 2479 0 3714 0 4584 0 cfg_gpmc_ad8_out vout3_d8 d3 gpmc_ad9 2355 0 3593 0 4463 0 cfg_gpmc_ad9_out vout3_d9 g3 gpmc_cs3 0 641 0 905 0 905 cfg_gpmc_cs3_out vout3_clk 5.10.6.5 hdmi the high-definition multimedia interface is provided for transmitting digital television audiovisual signals from dvd players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. the hdmi interface is aligned with the hdmi tmds single stream standard v1.4a (720p @60hz to 1080p @24hz) and the hdmi v1.3 (1080p @60hz): 3 data channels, plus 1 clock channel is supported (differential). in are presented the specific groupings of signals (ioset) for use with hdmi. 201 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note for more information, see the high-definition multimedia interface chapter of the device trm 5.10.6.6 csi2 note for more information, see the camera serial interface 2 cal bridge chapter of the device trm the camera adaptation layer (cal) deals with the processing of the pixel data coming from an external image sensor, data from memory. the cal is a key component for the following multimedia applications: camera viewfinder, video record, and still image capture. the cal has two serial camera interfaces (primary and secondary): ? the primary serial interface (csi2 port a) is compliant with mipi csi-2 protocol with four data lanes. 5.10.6.6.1 csi-2 mipi d-phy the csi-2 port a is compliant with the mipi d-phy rx specification v1.00.00 and the mipi csi-2 specification v1.00, with 2 data differential lanes plus 1 clock differential lane in synchronous mode, double data rate: ? 1.5 gbps (750 mhz) @opp_nom for each lane. 5.10.6.7 emif the device has a dedicated interface to ddr3 and ddr3l sdram. it supports jedec standard compliant ddr3 and ddr3l sdram devices with the following features: ? 16-bit or 32-bit data path to external sdram memory ? memory device capacity: 128mb, 256mb, 512mb, 1gb, 2gb, 4gb and 8gb devices ? one interface with associated ddr3/ddr3l phys note for more information, see the emif controller section of the device trm. 5.10.6.8 gpmc the gpmc is the unified memory controller that interfaces external memory devices such as: ? asynchronous sram-like memories and asic devices ? asynchronous page mode and synchronous burst nor flash ? nand flash note for more information, see the general-purpose memory controller section of the device trm. 202 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.8.1 gpmc/nor flash interface synchronous timing caution the i/o timings provided in this section are valid only for some gpmc usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-47 and table 5-48 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-23 , figure 5-24 , figure 5-25 , figure 5-26 , figure 5-27 and figure 5-28 ). table 5-47. gpmc/nor flash interface timing requirements - synchronous mode - default no. parameter description min max unit f12 t su(dv-clkh) setup time, read gpmc_ad[15:0] valid before gpmc_clk high 3 ns f13 t h(clkh-dv) hold time, read gpmc_ad[15:0] valid after gpmc_clk high 1.1 ns f21 t su(waitv-clkh) setup time, gpmc_wait[1:0] valid before gpmc_clk high 2.5 ns f22 t h(clkh-waitv) hold time, gpmc_wait[1:0] valid after gpmc_clk high 1.3 ns note wait monitoring support is limited to a waitmonitoringtime value > 0. for a full description of wait monitoring feature, see the device trm. table 5-48. gpmc/nor flash interface switching characteristics - synchronous mode - default no. parameter description min max unit f0 t c(clk) cycle time, output clock gpmc_clk period 11.3 ns f2 t d(clkh-ncsv) delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition f-1.7 (7) f+4.3 (7) ns f3 t d(clkh-ncsiv) delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid e-1.7 (6) e+4.2 (6) ns f4 t d(addv-clk) delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge b-1.8 (3) b+4.3 (3) ns f5 t d(clkh-addiv) delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid -1.8 ns f6 t d(nbev-clk) delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge b-4.3 (3) b+1.5 (3) ns f7 t d(clkh-nbeiv) delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid d-1.5 (5) d+4.3 (5) ns f8 t d(clkh-nadv) delay time, gpmc_clk rising edge to gpmc_advn_ale transition g-1.3 (8) g+4.2 (8) ns f9 t d(clkh-nadviv) delay time, gpmc_clk rising edge to gpmc_advn_ale invalid d-1.3 (5) g+4.2 (5) ns f10 t d(clkh-noe) delay time, gpmc_clk rising edge to gpmc_oen_ren transition h-1.0 (9) h+3.2 (9) ns f11 t d(clkh-noeiv) delay time, gpmc_clk rising edge to gpmc_oen_ren invalid e-1.0 (6) e+3.2 (6) ns f14 t d(clkh-nwe) delay time, gpmc_clk rising edge to gpmc_wen transition i-0.9 (10) i+4.2 (10) ns f15 t d(clkh-data) delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition j-2.1 (11) j+4.6 (11) ns f17 t d(clkh-nbe) delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition j-1.5 (11) j+4.3 (11) ns f18 t w(ncsv) pulse duration, gpmc_cs[7:0] low a (2) ns f19 t w(nbev) pulse duration, gpmc_ben[1:0] low c (4) ns f20 t w(nadvv) pulse duration, gpmc_advn_ale low k (12) ns f23 t d(clk-gpio) delay time, gpmc_clk transition to gpio6_16 transition 0.5 7.5 ns 203 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-49. gpmc/nor flash interface timing requirements - synchronous mode - alternate no. parameter description min max unit f12 t su(dv-clkh) setup time, read gpmc_ad[15:0] valid before gpmc_clk high 2.5 ns f13 t h(clkh-dv) hold time, read gpmc_ad[15:0] valid after gpmc_clk high 1.9 ns f21 t su(waitv-clkh) setup time, gpmc_wait[1:0] valid before gpmc_clk high 2.5 ns f22 t h(clkh-waitv) hold time, gpmc_wait[1:0] valid after gpmc_clk high 1.9 ns table 5-50. gpmc/nor flash interface switching characteristics - synchronous mode - alternate no. parameter description min max unit f0 t c(clk) cycle time, output clock gpmc_clk period (13) 15.04 ns f2 t d(clkh-ncsv) delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition f+0.6 (7) f+7.0 (7) ns f3 t d(clkh-ncsiv) delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid e+0.6 (6) e+7.0 (6) ns f4 t d(addv-clk) delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge b-0.7 (3) b+7.0 (3) ns f5 t d(clkh-addiv) delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid -0.7 ns f6 t d(nbev-clk) delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge b-7.0 b+0.4 ns f7 t d(clkh-nbeiv) delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid d-0.4 d+7.0 ns f8 t d(clkh-nadv) delay time, gpmc_clk rising edge to gpmc_advn_ale transition g+0.7 (8) g+6.1 (8) ns f9 t d(clkh-nadviv) delay time, gpmc_clk rising edge to gpmc_advn_ale invalid d+0.7 (5) d+6.1 (5) ns f10 t d(clkh-noe) delay time, gpmc_clk rising edge to gpmc_oen_ren transition h+0.7 (9) h+5.1 (9) ns f11 t d(clkh-noeiv) delay time, gpmc_clk rising edge to gpmc_oen_ren invalid e+0.7 (6) e+5.1 (6) ns f14 t d(clkh-nwe) delay time, gpmc_clk rising edge to gpmc_wen transition i+0.7 (10) i+6.1 (10) ns f15 t d(clkh-data) delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition j-0.4 (11) j+4.9 (11) ns f17 t d(clkh-nbe) delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition j-0.4 (11) j+4.9 (11) ns f18 t w(ncsv) pulse duration, gpmc_cs[7:0] low a (2) ns f19 t w(nbev) pulse duration, gpmc_ben[1:0] low c (4) ns f20 t w(nadvv) pulse duration, gpmc_advn_ale low k (12) ns f23 t d(clk-gpio) delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14) 0.5 7.5 ns (1) total gpmc load on any signal at 3.3v must not exceed 10pf. (2) for single read: a = (csrdofftime - csontime) (timeparagranularity + 1) gpmc_fclk period for burst read: a = (csrdofftime - csontime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk period for burst write: a = (cswrofftime - csontime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk period with n the page burst access number. (3) b = clkactivationtime gpmc_fclk (4) for single read: c = rdcycletime (timeparagranularity + 1) gpmc_fclk for burst read: c = (rdcycletime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk for burst write: c = (wrcycletime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk with n the page burst access number. (5) for single read: d = (rdcycletime - accesstime) (timeparagranularity + 1) gpmc_fclk for burst read: d = (rdcycletime - accesstime) (timeparagranularity + 1) gpmc_fclk for burst write: d = (wrcycletime - accesstime) (timeparagranularity + 1) gpmc_fclk (6) for single read: e = (csrdofftime - accesstime) (timeparagranularity + 1) gpmc_fclk for burst read: e = (csrdofftime - accesstime) (timeparagranularity + 1) gpmc_fclk for burst write: e = (cswrofftime - accesstime) (timeparagranularity + 1) gpmc_fclk (7) for ncs falling edge (cs activated): case gpmcfclkdivider = 0 : f = 0.5 csextradelay gpmc_fclk case gpmcfclkdivider = 1: f = 0.5 csextradelay gpmc_fclk if (clkactivationtime and csontime are odd) or (clkactivationtime and csontime are even) f = (1 + 0.5 csextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: f = 0.5 csextradelay gpmc_fclk if ((csontime - clkactivationtime) is a multiple of 3) f = (1 + 0.5 csextradelay) gpmc_fclk if ((csontime - clkactivationtime - 1) is a multiple of 3) f = (2 + 0.5 csextradelay) gpmc_fclk if ((csontime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: f = 0.5 csextradelay gpmc_fclk if ((csontime - clkactivationtime) is a multiple of 4) 204 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated f = (1 + 0.5 csextradelay) gpmc_fclk if ((csontime - clkactivationtime - 1) is a multiple of 4) f = (2 + 0.5 csextradelay) gpmc_fclk if ((csontime - clkactivationtime - 2) is a multiple of 4) f = (3 + 0.5 csextradelay) gpmc_fclk if ((csontime - clkactivationtime - 3) is a multiple of 4) (8) for adv falling edge (adv activated): case gpmcfclkdivider = 0 : g = 0.5 advextradelay gpmc_fclk case gpmcfclkdivider = 1: g = 0.5 advextradelay gpmc_fclk if (clkactivationtime and advontime are odd) or (clkactivationtime and advontime are even) g = (1 + 0.5 advextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: g = 0.5 advextradelay gpmc_fclk if ((advontime - clkactivationtime) is a multiple of 3) g = (1 + 0.5 advextradelay) gpmc_fclk if ((advontime - clkactivationtime - 1) is a multiple of 3) g = (2 + 0.5 advextradelay) gpmc_fclk if ((advontime - clkactivationtime - 2) is a multiple of 3) for adv rising edge (adv desactivated) in reading mode: case gpmcfclkdivider = 0: g = 0.5 advextradelay gpmc_fclk case gpmcfclkdivider = 1: g = 0.5 advextradelay gpmc_fclk if (clkactivationtime and advrdofftime are odd) or (clkactivationtime and advrdofftime are even) g = (1 + 0.5 advextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: g = 0.5 advextradelay gpmc_fclk if ((advrdofftime - clkactivationtime) is a multiple of 3) g = (1 + 0.5 advextradelay) gpmc_fclk if ((advrdofftime - clkactivationtime - 1) is a multiple of 3) g = (2 + 0.5 advextradelay) gpmc_fclk if ((advrdofftime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: g = 0.5 advextradelay gpmc_fclk if ((advrdofftime - clkactivationtime) is a multiple of 4) g = (1 + 0.5 advextradelay) gpmc_fclk if ((advrdofftime - clkactivationtime - 1) is a multiple of 4) g = (2 + 0.5 advextradelay) gpmc_fclk if ((advrdofftime - clkactivationtime - 2) is a multiple of 4) g = (3 + 0.5 advextradelay) gpmc_fclk if ((advrdofftime - clkactivationtime - 3) is a multiple of 4) for adv rising edge (adv desactivated) in writing mode: case gpmcfclkdivider = 0: g = 0.5 advextradelay gpmc_fclk case gpmcfclkdivider = 1: g = 0.5 advextradelay gpmc_fclk if (clkactivationtime and advwrofftime are odd) or (clkactivationtime and advwrofftime are even) g = (1 + 0.5 advextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: g = 0.5 advextradelay gpmc_fclk if ((advwrofftime - clkactivationtime) is a multiple of 3) g = (1 + 0.5 advextradelay) gpmc_fclk if ((advwrofftime - clkactivationtime - 1) is a multiple of 3) g = (2 + 0.5 advextradelay) gpmc_fclk if ((advwrofftime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: g = 0.5 advextradelay gpmc_fclk if ((advwrofftime - clkactivationtime) is a multiple of 4) g = (1 + 0.5 advextradelay) gpmc_fclk if ((advwrofftime - clkactivationtime - 1) is a multiple of 4) g = (2 + 0.5 advextradelay) gpmc_fclk if ((advwrofftime - clkactivationtime - 2) is a multiple of 4) g = (3 + 0.5 advextradelay) gpmc_fclk if ((advwrofftime - clkactivationtime - 3) is a multiple of 4) (9) for oe falling edge (oe activated): case gpmcfclkdivider = 0: - h = 0.5 oeextradelay gpmc_fclk case gpmcfclkdivider = 1: - h = 0.5 oeextradelay gpmc_fclk if (clkactivationtime and oeontime are odd) or (clkactivationtime and oeontime are even) - h = (1 + 0.5 oeextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: - h = 0.5 oeextradelay gpmc_fclk if ((oeontime - clkactivationtime) is a multiple of 3) - h = (1 + 0.5 oeextradelay) gpmc_fclk if ((oeontime - clkactivationtime - 1) is a multiple of 3) - h = (2 + 0.5 oeextradelay) gpmc_fclk if ((oeontime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: - h = 0.5 oeextradelay gpmc_fclk if ((oeontime - clkactivationtime) is a multiple of 4) - h = (1 + 0.5 oeextradelay) gpmc_fclk if ((oeontime - clkactivationtime - 1) is a multiple of 4) - h = (2 + 0.5 oeextradelay) gpmc_fclk if ((oeontime - clkactivationtime - 2) is a multiple of 4) - h = (3 + 0.5 oeextradelay)) gpmc_fclk if ((oeontime - clkactivationtime - 3) is a multiple of 4) for oe rising edge (oe desactivated): case gpmcfclkdivider = 0: - h = 0.5 oeextradelay gpmc_fclk case gpmcfclkdivider = 1: - h = 0.5 oeextradelay gpmc_fclk if (clkactivationtime and oeofftime are odd) or (clkactivationtime and oeofftime are even) - h = (1 + 0.5 oeextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: - h = 0.5 oeextradelay gpmc_fclk if ((oeofftime - clkactivationtime) is a multiple of 3) - h = (1 + 0.5 oeextradelay) gpmc_fclk if ((oeofftime - clkactivationtime - 1) is a multiple of 3) 205 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated - h = (2 + 0.5 oeextradelay) gpmc_fclk if ((oeofftime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: - h = 0.5 oeextradelay gpmc_fclk if ((oeofftime - clkactivationtime) is a multiple of 4) - h = (1 + 0.5 oeextradelay) gpmc_fclk if ((oeofftime - clkactivationtime - 1) is a multiple of 4) - h = (2 + 0.5 oeextradelay) gpmc_fclk if ((oeofftime - clkactivationtime - 2) is a multiple of 4) - h = (3 + 0.5 oeextradelay) gpmc_fclk if ((oeofftime - clkactivationtime - 3) is a multiple of 4) (10) for we falling edge (we activated): case gpmcfclkdivider = 0: - i = 0.5 weextradelay gpmc_fclk case gpmcfclkdivider = 1: - i = 0.5 weextradelay gpmc_fclk if (clkactivationtime and weontime are odd) or (clkactivationtime and weontime are even) - i = (1 + 0.5 weextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: - i = 0.5 weextradelay gpmc_fclk if ((weontime - clkactivationtime) is a multiple of 3) - i = (1 + 0.5 weextradelay) gpmc_fclk if ((weontime - clkactivationtime - 1) is a multiple of 3) - i = (2 + 0.5 weextradelay) gpmc_fclk if ((weontime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: - i = 0.5 weextradelay gpmc_fclk if ((weontime - clkactivationtime) is a multiple of 4) - i = (1 + 0.5 weextradelay) gpmc_fclk if ((weontime - clkactivationtime - 1) is a multiple of 4) - i = (2 + 0.5 weextradelay) gpmc_fclk if ((weontime - clkactivationtime - 2) is a multiple of 4) - i = (3 + 0.5 weextradelay) gpmc_fclk if ((weontime - clkactivationtime - 3) is a multiple of 4) for we rising edge (we desactivated): case gpmcfclkdivider = 0: - i = 0.5 weextradelay gpmc_fclk case gpmcfclkdivider = 1: - i = 0.5 weextradelay gpmc_fclk if (clkactivationtime and weofftime are odd) or (clkactivationtime and weofftime are even) - i = (1 + 0.5 weextradelay) gpmc_fclk otherwise case gpmcfclkdivider = 2: - i = 0.5 weextradelay gpmc_fclk if ((weofftime - clkactivationtime) is a multiple of 3) - i = (1 + 0.5 weextradelay) gpmc_fclk if ((weofftime - clkactivationtime - 1) is a multiple of 3) - i = (2 + 0.5 weextradelay) gpmc_fclk if ((weofftime - clkactivationtime - 2) is a multiple of 3) case gpmcfclkdivider = 3: - i = 0.5 weextradelay gpmc_fclk if ((weofftime - clkactivationtime) is a multiple of 4) - i = (1 + 0.5 weextradelay) gpmc_fclk if ((weofftime - clkactivationtime - 1) is a multiple of 4) - i = (2 + 0.5 weextradelay) gpmc_fclk if ((weofftime - clkactivationtime - 2) is a multiple of 4) - i = (3 + 0.5 weextradelay) gpmc_fclk if ((weofftime - clkactivationtime - 3) is a multiple of 4) (11) j = gpmc_fclk period, where gpmc_fclk is the general purpose memory controller internal functional clock (12) for read: k = (advrdofftime - advontime) (timeparagranularity + 1) gpmc_fclk for write: k = (advwrofftime - advontime) (timeparagranularity + 1) gpmc_fclk (13) the gpmc_clk output clock maximum and minimum frequency is programmable in the i/f module by setting the gpmc_config1_csx configuration register bit fields gpmcfclkdivider (14) gpio6_16 programmed to muxmode=9 (clkout1), cm_clksel_clkoutmux1 programmed to 7 (core_dpll_out_dclk), cm_clksel_core_dpll_out_clk_clkoutmux programmed to 1. (15) csextradelay = 0, advextradelay = 0, weextradelay = 0, oeextradelay = 0. extra half-gpmc_fclk cycle delay mode is not timed. 206 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-23. gpmc / multiplexed 16bits nor flash - synchronous single read - (gpmcfclkdivider = 0) (1) (2) (1) in gpmc_cs i , i = 0 to 7. (2) in gpmc_waitj, j = 0 to 1. gpmc_clk gpmc_cs i gpmc_a[ :1] 1027 gpmc_a[ ] gpmc_be 1n gpmc_ben0 gpmc_adv _ale n gpmc_oen_ren gpmc_ad[15:0] gpmc_wait j address (msb) address (lsb) d 0 f0 f12 f13 f6 f2 f8 f3 f7 f9 f11 f1 f1 f8 f19 f18 f20 f10 f4 f5 f6 f7 f19 f4 f22 f21 f23 gpmc_01 gpio6_16.clkout1 f23 207 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-24. gpmc / nonmultiplexed 16bits nor flash - synchronous single read - (gpmcfclkdivider = 0) (1) (2) (1) in gpmc_cs i , i = 0 to 7. (2) in gpmc_waitj, j = 0 to 1. gpmc_clk gpmc_cs i gpmc_a[2 :1]7 gpmc_be 1n gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_ad[15:0] gpmc_wait j address d 0 f0 f12 f13 f6 f2 f8 f3 f7 f9 f11 f1 f1 f8 f19 f18 f20 f10 f6 f7 f19 f4 f22 f21 f23 gpmc_02 gpio6_16.clkout1 f23 208 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-25. gpmc / multiplexed 16bits nor flash - synchronous burst read 4x16 bits - (gpmcfclkdivider = 0) (1) (2) (1) in gpmc_cs i , i= 0 to 7. (2) in gpmc_waitj, j = 0 to 1. gpmc_clk gpmc_cs i gpmc_a[ :1] 1027 gpmc_a[ ] gpmc_ 1 ben gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_ad[15:0] gpmc_wait j address (msb) valid valid address (lsb) d0 d1 d2 d3 f6 f4 f2 f8 f8 f10 f13 f12 f12 f11 f9 f7 f3 f0 f1 f1 f5 f6 f7 f22 f21 f4 f18 f20 f19 f19 f23 gpmc_03 gpio6_16.clkout1 f23 209 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-26. gpmc / nonmultiplexed 16bits nor flash - synchronous burst read 4x16 bits - (gpmcfclkdivider = 0) (1) (2) (1) in gpmc_cs i , i = 0 to 7. (2) in gpmc_waitj, j = 0 to 1. gpmc_clk gpmc_cs i gpmc_a[2 :1]7 gpmc_be 1n gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_ad[15:0] gpmc_wait j address valid valid d0 d1 d2 d3 f6 f2 f8 f8 f10 f13 f12 f12 f11 f9 f7 f3 f0 f1 f1 f6 f7 f22 f21 f4 f18 f20 f19 f19 f23 gpmc_04 gpio6_16.clkout1 f23 210 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-27. gpmc / multiplexed 16bits nor flash - synchronous burst write 4x16bits - (gpmcfclkdivider = 0) (1) (2) (1) in ? gpmc_cs i ? , i = 0 to 7. (2) in ? gpmc_waitj ? , j = 0 to 1. gpmc_clk gpmc_cs i gpmc_a[ :1] 1027 gpmc_a[ ] gpmc_ 1 ben gpmc_ben0 gpmc_ _ale advn gpmc_wen gpmc_ad[15:0] gpmc_wait j address (msb) address (lsb) d 0 d 1 d 2 d 3 f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f3 f17 f17 f17 f9 f6 f17 f17 f17 f18 f20 f14 f14 f22 f21 gpmc_05 gpio6_16.clkout1 f23 f23 211 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-28. gpmc / nonmultiplexed 16bits nor flash - synchronous burst write 4x16bits - (gpmcfclkdivider = 0) (1) (2) (1) in ? gpmc_cs i ? , i = 1 to 7. (2) in ? gpmc_waitj ? , j = 0 to 1. 5.10.6.8.2 gpmc/nor flash interface asynchronous timing caution the i/o timings provided in this section are valid only for some gpmc usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-51 and table 5-52 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-29 , figure 5-30 , figure 5-31 , figure 5-32 , figure 5-33 and figure 5-34 ). table 5-51. gpmc/nor flash interface timing requirements - asynchronous mode no. parameter description min max unit fa5 t acc(dat) data maximum access time (gpmc_fclk cycles) h (1) cycles gpmc_clk gpmc_cs i gpmc_a[2 :1]7 gpmc_ 1 ben gpmc_ben0 gpmc_ _ale advn gpmc_wen gpmc_ad[15:0] gpmc_wait j address d 0 d 1 d 2 d 3 f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f3 f17 f17 f17 f9 f6 f17 f17 f17 f18 f20 f14 f14 f22 f21 gpmc_06 gpio6_16.clkout1 f23 f23 212 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-51. gpmc/nor flash interface timing requirements - asynchronous mode (continued) no. parameter description min max unit fa20 t acc1-pgmode(dat) page mode successive data maximum access time (gpmc_fclk cycles) p (2) cycles fa21 t acc2-pgmode(dat) page mode first data maximum access time (gpmc_fclk cycles) h (1) cycles - t su(dv-oeh) setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high 1.9 ns - t h(oeh-dv) hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high 1 ns (1) h = access time (timeparagranularity + 1) (2) p = pageburstaccesstime (timeparagranularity + 1) table 5-52. gpmc/nor flash interface switching characteristics - asynchronous mode no. parameter description min max unit - t r(do) rising time, gpmc_ad[15:0] output data 0.447 4.067 ns - t f(do) fallling time, gpmc_ad[15:0] output data 0.43 4.463 ns fa0 t w(nbev) pulse duration, gpmc_ben[1:0] valid time n (1) ns fa1 t w(ncsv) pulse duration, gpmc_cs[7:0] low a (2) ns fa3 t d(ncsv-nadviv) delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid b - 2 (3) b + 4 (3) ns fa4 t d(ncsv-noeiv) delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (single read) c - 2 (4) c + 4 (4) ns fa9 t d(av-ncsv) delay time, address bus valid to gpmc_cs[7:0] valid j - 2 (5) j + 4 (5) ns fa10 t d(nbev-ncsv) delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid j - 2 (5) j + 4 (5) ns fa12 t d(ncsv-nadvv) delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid k - 2 (6) k + 4 (6) ns fa13 t d(ncsv-noev) delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid l - 2 (7) l + 4 (7) ns fa16 t w(aiv) pulse duration, address invalid between 2 successive r/w accesses g (8) ns fa18 t d(ncsv-noeiv) delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (burst read) i - 2 (9) i + 4 (9) ns fa20 t w(av) pulse duration, address valid : 2nd, 3rd and 4th accesses d (10) ns fa25 t d(ncsv-nwev) delay time, gpmc_cs[7:0] valid to gpmc_wen valid e - 2 (11) e + 4 (11) ns fa27 t d(ncsv-nweiv) delay time, gpmc_cs[7:0] valid to gpmc_wen invalid f - 2 (12) f + 4 (12) ns fa28 t d(nwev-dv) delay time, gpmc_ wen valid to data bus valid 2 ns fa29 t d(dv-ncsv) delay time, data bus valid to gpmc_cs[7:0] valid j - 2 (5) j + 4 (5) ns fa37 t d(noev-aiv) delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus phase end 2 ns (1) for single read: n = rdcycletime (timeparagranularity + 1) gpmc_fclk for single write: n = wrcycletime (timeparagranularity + 1) gpmc_fclk for burst read: n = (rdcycletime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk for burst write: n = (wrcycletime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk (2) for single read: a = (csrdofftime - csontime) (timeparagranularity + 1) gpmc_fclk for single write: a = (cswrofftime - csontime) (timeparagranularity + 1) gpmc_fclk for burst read: a = (csrdofftime - csontime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk for burst write: a = (cswrofftime - csontime + (n - 1) pageburstaccesstime) (timeparagranularity + 1) gpmc_fclk (3) for reading: b = ((advrdofftime - csontime) (timeparagranularity + 1) + 0.5 (advextradelay - csextradelay)) gpmc_fclk for writing: b = ((advwrofftime - csontime) (timeparagranularity + 1) + 0.5 (advextradelay - csextradelay)) gpmc_fclk (4) c = ((oeofftime - csontime) (timeparagranularity + 1) + 0.5 (oeextradelay - csextradelay)) gpmc_fclk (5) j = (csontime (timeparagranularity + 1) + 0.5 csextradelay) gpmc_fclk (6) k = ((advontime - csontime) (timeparagranularity + 1) + 0.5 (advextradelay - csextradelay)) gpmc_fclk (7) l = ((oeontime - csontime) (timeparagranularity + 1) + 0.5 (oeextradelay - csextradelay)) gpmc_fclk (8) g = cycle2cycledelay gpmc_fclk (timeparagranularity +1) (9) i = ((oeofftime + (n - 1) pageburstaccesstime - csontime) (timeparagranularity + 1) + 0.5 (oeextradelay - csextradelay)) gpmc_fclk (10) d = pageburstaccesstime (timeparagranularity + 1) gpmc_fclk (11) e = ((weontime - csontime) (timeparagranularity + 1) + 0.5 (weextradelay - csextradelay)) gpmc_fclk (12) f = ((weofftime - csontime) (timeparagranularity + 1) + 0.5 (weextradelay - csextradelay)) gpmc_fclk 213 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-29. gpmc / nor flash - asynchronous read - single word timing (1) (2) (3) (1) in gpmc_cs i , i = 0 to 7. in gpmc_waitj, j = 0 to 1. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bits field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. (4) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. gpmc_fclk gpmc_clk gpmc_cs i gpmc_a[ :1] 27 gpmc_ben0 gpmc_be 1n gpmc_ _ale advn gpmc_oen_ren gpmc_ d[15:0] a gpmc_wait j dir valid address valid valid data in 0 data in 0 out out in out fa0 fa9 fa10 fa3 fa1 fa4 fa12 fa13 fa0 fa10 fa5 fa14 fa15 gpmc_07 214 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-30. gpmc / nor flash - asynchronous read - 32-bit timing (1) (2) (3) (1) in ? gpmc_cs i ? , i = 0 to 7. in ? gpmc_waitj ? , j = 0 to 1. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value should be stored inside accesstime register bits field (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally (4) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. gpmc_fclk gpmc_clk gpmc_cs i gpmc_a[ :1] 27 gpmc_ben0 gpmc_be 1n gpmc_ _ale advn gpmc_oen_ren gpmc_ d[15:0] a gpmc_wait j dir address 0 address 1 valid valid valid valid data upper out out in out in fa9 fa10 fa3 fa9 fa3 fa13 fa13 fa1 fa1 fa4 fa4 fa12 fa12 fa10 fa0 fa0 fa16 fa0 fa0 fa10 fa10 fa5 fa5 fa14 fa15 fa14 fa15 gpmc_08 215 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-31. gpmc / nor flash - asynchronous read - page mode 4x16-bit timing (1) (2) (3) (4) (1) in ? gpmc_cs i ? , i = 0 to 7. in ? gpmc_waitj ? , j = 0 to 1 (2) fa21 parameter illustrates amount of time required to internally sample first input page data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. fa21 calculation is detailled in a separated application note and should be stored inside accesstime register bits field. (3) fa20 parameter illustrates amount of time required to internally sample successive input page data. it is expressed in number of gpmc functional clock cycles. after each access to input page data, next input page data will be internally sampled by active functional clock edge after fa20 functional clock cycles. fa20 is also the duration of address phases for successive input page data (excluding first input page data). fa20 value should be stored in pageburstaccesstime register bits field. (4) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally (5) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. gpmc_fclk gpmc_clk gpmc_cs i gpmc_a[ :1] 27 gpmc_ben0 gpmc_be 1n gpmc_ _ale advn gpmc_oen_ren gpmc_ d[15:0] a gpmc_wait j dir add0 add1 add2 add3 add4 d0 d1 d2 d3 d3 out out in out fa1 fa0 fa18 fa13 fa12 fa0 fa9 fa10 fa10 fa21 fa20 fa20 fa20 fa14 fa15 sprs91v_gpmc_09 216 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-32. gpmc / nor flash - asynchronous write - single word timing (1) (1) in ? gpmc_cs i ? , i = 0 to 7. in ? gpmc_waitj ? , j = 0 to 1. (2) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. gpmc_fclk gpmc_clk gpmc_cs i gpmc_a[ :1] 27 gpmc_ben0 gpmc_be 1n gpmc_ _ale advn gpmc_wen gpmc_ d[15:0] a gpmc_wait j dir valid address data out out fa0 fa1 fa10 fa3 fa25 fa29 fa9 fa12 fa27 fa0 fa10 gpmc_10 217 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-33. gpmc / multiplexed nor flash - asynchronous read - single word timing (1) (2) (3) (1) in ? gpmc_cs i ? , i = 0 to 7. in ? gpmc_waitj ? , j = 0 to 1 (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value should be stored inside accesstime register bits field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally (4) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. gpmc_fclk gpmc_clk gpmc_cs i gpmc_a27 gpmc_ben0 gpmc_ 1 ben gpmc_ _ale advn gpmc_oen_ren gpmc_a [15:0] d dir gpmc_wait j address (msb) valid valid address (lsb) data in data in out out in out fa0 fa9 fa10 fa3 fa13 fa29 fa1 fa37 fa12 fa4 fa10 fa0 fa5 fa14 fa15 gpmc_11 gpmc_a[10:1] 218 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-34. gpmc / multiplexed nor flash - asynchronous write - single word timing (1) (1) in ? gpmc_cs i ? , i = 0 to 7. in ? gpmc_waitj ? , j = 0 to 1. (2) the "dir" (direction control) output signal is not pinned out on any of the device pads. it is an internal signal only representing a signal direction on the gpmc data bus. 5.10.6.8.3 gpmc/nand flash interface asynchronous timing caution the i/o timings provided in this section are valid only for some gpmc usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-53 and table 5-54 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-35 , figure 5-36 , figure 5-37 and figure 5-38 ). table 5-53. gpmc/nand flash interface timing requirements no. parameter description min max unit gnf12 t acc(dat) data maximum access time (gpmc_fclk cycles) j (1) cycles - t su(dv-oeh) setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high 1.9 ns - t h(oeh-dv) hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high 1 ns gpmc_fclk gpmc_clk gpmc_cs i gpmc_ben0 gpmc_ 1 ben gpmc_ _ale advn gpmc_wen gpmc_ad[15:0] gpmc_wait j dir address (msb) valid address (lsb) data out out fa0 fa1 fa9 fa10 fa3 fa25 fa29 fa12 fa27 fa28 fa0 fa10 gpmc_12 gpmc_a27 gpmc_a[10:1] 219 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) j = accesstime (timeparagranularity + 1) table 5-54. gpmc/nand flash interface switching characteristics no. parameter description min max unit - t r(do) rising time, gpmc_ad[15:0] output data 0.447 4.067 ns - t f(do) fallling time, gpmc_ad[15:0] output data 0.43 4.463 ns gnf0 t w(nwev) pulse duration, gpmc_wen valid time a (1) ns gnf1 t d(ncsv-nwev) delay time, gpmc_cs[7:0] valid to gpmc_wen valid b - 2 (2) b + 4 (2) ns gnf2 t d(cleh-nwev) delay time, gpmc_ben[1:0] high to gpmc_wen valid c - 2 (3) c + 4 (3) ns gnf3 t d(nwev-dv) delay time, gpmc_ad[15:0] valid to gpmc_wen valid d - 2 (4) d + 4 (4) ns gnf4 t d(nweiv-div) delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid e - 2 (5) e + 4 (5) ns gnf5 t d(nweiv-cleiv) delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid f - 2 (6) f + 4 (6) ns gnf6 t d(nweiv-ncsiv) delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid g - 2 (7) g + 4 (7) ns gnf7 t d(aleh-nwev) delay time, gpmc_advn_ale high to gpmc_wen valid c - 2 (3) c + 4 (3) ns gnf8 t d(nweiv-aleiv) delay time, gpmc_wen invalid to gpmc_advn_ale invalid f - 2 (6) f + 4 (6) ns gnf9 t c(nwe) cycle time, write cycle time h (8) ns gnf10 t d(ncsv-noev) delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid i - 2 (9) i + 4 (9) ns gnf13 t w(noev) pulse duration, gpmc_oen_ren valid time k (10) ns gnf14 t c(noe) cycle time, read cycle time l (11) ns gnf15 t d(noeiv-ncsiv) delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid m - 2 (12) m + 4 (12) ns (1) a = (weofftime ? weontime) (timeparagranularity + 1) gpmc_fclk (2) b = ((weontime ? csontime) (timeparagranularity + 1) + 0.5 (weextradelay ? csextradelay)) gpmc_fclk (3) c = ((weontime ? advontime) (timeparagranularity + 1) + 0.5 (weextradelay ? advextradelay)) gpmc_fclk (4) d = (weontime (timeparagranularity + 1) + 0.5 weextradelay ) gpmc_fclk (5) e = (wrcycletime ? weofftime (timeparagranularity + 1) ? 0.5 weextradelay ) gpmc_fclk (6) f = (advwrofftime ? weofftime (timeparagranularity + 1) + 0.5 (advextradelay ? weextradelay ) gpmc_fclk (7) g = (cswrofftime ? weofftime (timeparagranularity + 1) + 0.5 (csextradelay ? weextradelay ) gpmc_fclk (8) h = wrcycletime (1 + timeparagranularity) gpmc_fclk (9) i = ((oeofftime + (n ? 1) pageburstaccesstime ? csontime) (timeparagranularity + 1) + 0.5 (oeextradelay ? csextradelay)) gpmc_fclk (10) k = (oeofftime ? oeontime) (1 + timeparagranularity) gpmc_fclk (11) l = rdcycletime (1 + timeparagranularity) gpmc_fclk (12) m = (csrdofftime ? oeofftime (timeparagranularity + 1) + 0.5 (csextradelay ? oeextradelay ) gpmc_fclk 220 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-35. gpmc / nand flash - command latch cycle timing (1) (1) in gpmc_cs i , i = 0 to 7. figure 5-36. gpmc / nand flash - address latch cycle timing (1) (1) in gpmc_cs i , i = 0 to 7. gpmc_fclk gpmc_cs i gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_wen gpmc_ad[15:0] command gnf0 gnf1 gnf2 gnf3 gnf4 gnf5 gnf6 gpmc_13 gpmc_fclk gpmc_cs i gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_wen gpmc_ad[15:0] address gnf0 gnf1 gnf7 gnf3 gnf4 gnf6 gnf8 gnf9 gpmc_14 221 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-37. gpmc / nand flash - data read cycle timing (1) (2) (3) (1) gnf12 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after gnf12 functional clock cycles, input data will be internally sampled by active functional clock edge. gnf12 value must be stored inside accesstime register bits field. (2) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. (3) in gpmc_cs i , i = 0 to 7. in gpmc_waitj, j = 0 to 1. figure 5-38. gpmc / nand flash - data write cycle timing (1) (1) in gpmc_cs i , i = 0 to 7. note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . gpmc_fclk gpmc_cs i gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_wen gpmc_ad[15:0] data gnf0 gnf1 gnf4 gnf6 gnf9 gnf3 gpmc_16 gpmc_fclk gpmc_cs i gpmc_ben0 gpmc_ _ale advn gpmc_oen_ren gpmc_ad[15:0] gpmc_wait j data gnf10 gnf13 gnf14 gnf15 gnf12 gpmc_15 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 222 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com virtual io timings modes must be used to guaranteed some io timings for gpmc. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-55 virtual functions mapping for gpmc for a definition of the virtual modes. table 5-55 presents the values for delaymode bitfield. table 5-55. virtual functions mapping for gpmc ball ball name delay mode value muxmode gpmc_virtual1 0 1 2 3 5 6 14 (1) 14 (1) h5 gpmc_advn_al e 15 gpmc_advn_al e gpmc_cs6 gpmc_wait1 gpmc_a2 gpmc_a23 b4 gpmc_ad15 13 gpmc_ad15 b1 gpmc_ad6 13 gpmc_ad6 e1 gpmc_ad2 13 gpmc_ad2 e10 vin2a_d9 9 gpmc_a25 g6 gpmc_wen 15 gpmc_wen a3 gpmc_ad14 13 gpmc_ad14 h3 gpmc_a13 15 gpmc_a13 k4 gpmc_a8 14 gpmc_a8 h4 gpmc_a14 15 gpmc_a14 d1 gpmc_ad4 13 gpmc_ad4 a5 gpmc_a26 15 gpmc_a26 gpmc_a20 f1 gpmc_ad0 13 gpmc_ad0 f6 gpmc_wait0 15 gpmc_wait0 c10 vin2a_d11 9 gpmc_a23 e2 gpmc_ad1 13 gpmc_ad1 c4 gpmc_ad13 13 gpmc_ad13 l2 gpmc_a2 14 gpmc_a2 d2 gpmc_ad5 13 gpmc_ad5 b10 vin2a_d8 9 gpmc_a26 f3 gpmc_cs0 15 gpmc_cs0 e8 vin2a_hsync0 9 gpmc_a27 k3 gpmc_a4 14 gpmc_a4 h2 gpmc_ben0 15 gpmc_ben0 gpmc_cs4 j1 gpmc_a6 14 gpmc_a6 k6 gpmc_a15 15 gpmc_a15 b3 gpmc_ad11 13 gpmc_ad11 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 223 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-55. virtual functions mapping for gpmc (continued) ball ball name delay mode value muxmode gpmc_virtual1 0 1 2 3 5 6 14 (1) 14 (1) k5 gpmc_a16 15 gpmc_a16 m2 gpmc_a1 14 gpmc_a1 d7 gpmc_a24 15 gpmc_a24 gpmc_a18 b5 gpmc_a23 15 gpmc_a23 gpmc_a17 c2 gpmc_ad8 13 gpmc_ad8 a2 gpmc_ad10 13 gpmc_ad10 c3 gpmc_ad12 13 gpmc_ad12 e7 gpmc_a20 15 gpmc_a20 gpmc_a14 d10 vin2a_d10 9 gpmc_a24 g3 gpmc_cs3 14 gpmc_cs3 gpmc_a1 g5 gpmc_oen_ren 15 gpmc_oen_ren h1 gpmc_a9 14 gpmc_a9 a6 gpmc_cs1 15 gpmc_cs1 gpmc_a22 c1 gpmc_ad3 13 gpmc_ad3 b2 gpmc_ad7 13 gpmc_ad7 k1 gpmc_a7 14 gpmc_a7 l1 gpmc_a3 14 gpmc_a3 h6 gpmc_ben1 15 gpmc_ben1 gpmc_cs5 gpmc_a3 l4 gpmc_clk 15 gpmc_clk gpmc_cs7 gpmc_wait1 c5 gpmc_a22 15 gpmc_a22 gpmc_a16 g4 gpmc_cs2 15 gpmc_cs2 c7 vin2a_fld0 11 gpmc_a27 gpmc_a18 j2 gpmc_a10 14 gpmc_a10 g1 gpmc_a12 15 gpmc_a12 gpmc_a0 g2 gpmc_a17 15 gpmc_a17 k2 gpmc_a5 14 gpmc_a5 d6 gpmc_a21 15 gpmc_a21 gpmc_a15 b6 gpmc_a27 15 gpmc_a27 gpmc_a21 d3 gpmc_ad9 13 gpmc_ad9 a4 gpmc_a19 15 gpmc_a19 gpmc_a13 c6 gpmc_a25 15 gpmc_a25 gpmc_a19 m1 gpmc_a0 14 gpmc_a0 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 224 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-55. virtual functions mapping for gpmc (continued) ball ball name delay mode value muxmode gpmc_virtual1 0 1 2 3 5 6 14 (1) 14 (1) d8 vin2a_clk0 11 gpmc_a27 gpmc_a17 f2 gpmc_a18 15 gpmc_a18 l3 gpmc_a11 14 gpmc_a11 225 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) some signals listed are virtual functions that present alternate multiplexing options. these virtual functions are controlled via ctrl_core_alt_select_mux or ctrl_core_vip_mux_select registers. for more information on how to use these options, please refer to device trm, chapter control module, section pad configuration registers. 5.10.6.9 timers the device has 16 general-purpose (gp) timers (timer1 - timer16), two watchdog timers, and a 32-khz synchronized timer (counter_32k) that have the following features: ? dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (pwm) signal ? interrupts generated on overflow, compare, and capture ? free-running 32-bit upward counter ? supported modes: ? compare and capture modes ? auto-reload mode ? start-stop mode ? on-the-fly read/write register (while counting) the device has two system watchdog timer (wd_timer1 and wd_timer2) that have the following features: ? free-running 32-bit upward counter ? on-the-fly read/write register (while counting) ? reset upon occurrence of a timer overflow condition the device includes one instance of the 32-bit watchdog timer: wd_timer2, also called the mpu watchdog timer. the watchdog timer is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. in are presented the specific groupings of signals (ioset) for use with timers. note for additional information on the timer module, see the device trm. 5.10.6.10 i2c the device includes 6 inter-integrated circuit (i2c) modules which provide an interface to other devices compliant with philips semiconductors inter-ic bus (i2c-bus ? ) specification version 2.1. external components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the i2c module. note note that, on i2c1 and i2c2, due to characteristics of the open drain io cells, hs mode is not supported. note inter-integrated circuit i (i=1 to 6) module is also referred to as i2ci. 226 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note for more information, see the multimaster high-speed i2c controller section of the device trm. table 5-56 , table 5-57 and figure 5-39 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-56. timing requirements for i2c input timings (1) no. parameter description standard mode fast mode unit min max min max 1 t c(scl) cycle time, scl 10 2.5 s 2 t su(sclh-sdal) setup time, scl high before sda low (for a repeated start condition) 4.7 0.6 s 3 t h(sdal-scll) hold time, scl low after sda low (for a start and a repeated start condition) 4 0.6 s 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sclh) setup time, sda valid before scl high 250 100 (2) ns 7 t h(scll-sdav) hold time, sda valid after scl low 0 (3) 3.45 (4) 0 (3) 0.9 (4) s 8 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 9 t r(sda) rise time, sda 1000 20 + 0.1c b (5) 300 (3) ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b (5) 300 (3) ns 11 t f(sda) fall time, sda 300 20 + 0.1c b (5) 300 (3) ns 12 t f(scl) fall time, scl 300 20 + 0.1c b (5) 300 (3) ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b (5) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) a fast-mode i 2 c-bus ? device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda-sclh) 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. (3) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. (4) the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. table 5-57. timing requirements for i 2 c hs-mode (i 2 c3/4/5/6 only) (1) no. parameter description c b = 100 pf max c b = 400 pf (2) unit min max min max 1 t c(scl) cycle time, scl 0.294 0.588 s 2 t su(sclh-sdal) set-up time, scl high before sda low (for a repeated start condition) 160 160 ns 3 t h(sdal-scll) hold time, scl low after sda low (for a repeated start condition) 160 160 ns 227 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-57. timing requirements for i 2 c hs-mode (i 2 c3/4/5/6 only) (1) (continued) no. parameter description c b = 100 pf max c b = 400 pf (2) unit min max min max 4 t w(scll) low period of the sclh clock 160 320 ns 5 t w(sclh) high period of the sclh clock 60 120 ns 6 t su(sdav-sclh) setup time, sda valid vefore scl high 10 10 ns 7 t h(scll-sdav) hold time, sda valid after scl low 0 (3) 70 0 (3) 150 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for a stop condition) 160 160 ns 14 t w(sp) pulse duration, spike (must be suppressed) 0 10 0 10 ns 15 c b (2) capacitive load for sdah and sclh lines 100 400 pf 16 c b capacitive load for sdah + sda line and sclh + scl line 400 400 pf (1) i 2 c hs-mode is only supported on i 2 c3/4/5/6. i2c hs-mode is not supported on i 2 c1/2. (2) for bus line loads c b between 100 and 400 pf the timing parameters must be linearly interpolated. (3) a device must internally provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the sclh signal. an input circuit with a threshold as low as possible for the falling edge of the sclh signal minimizes this hold time. figure 5-39. i2c receive timing table 5-58 and figure 5-40 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-58. switching characteristics over recommended operating conditions for i2c output timings (2) no. parameter description standard mode fast mode unit min max min max 16 t c(scl) cycle time, scl 10 2.5 s 17 t su(sclh-sdal) setup time, scl high before sda low (for a repeated start condition) 4.7 0.6 s 18 t h(sdal-scll) hold time, scl low after sda low (for a start and a repeated start condition) 4 0.6 s 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t su(sdav-sclh) setup time, sda valid before scl high 250 100 ns 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop i2ci_sda i2ci_scl 1 11 9 sprs906_timing_i2c_01 228 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-58. switching characteristics over recommended operating conditions for i2c output timings (2) (continued) no. parameter description standard mode fast mode unit min max min max 22 t h(scll-sdav) hold time, sda valid after scl low (for i2c bus devices) 0 3.45 0 0.9 s 23 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 24 t r(sda) rise time, sda 1000 20 + 0.1c b (1) (3) 300 (3) ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b (1) (3) 300 (3) ns 26 t f(sda) fall time, sda 300 20 + 0.1c b (1) (3) 300 (3) ns 27 t f(scl) fall time, scl 300 20 + 0.1c b (1) (3) 300 (3) ns 28 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf (1) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. (2) software must properly configure the i2c module registers to achieve the timings shown in this table. see the device trm for details. (3) these timings apply only to i2c1 and i2c2. i2c3, i2c4, i2c5 and i2c6 use standard lvcmos buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device ibis model. note i2c emulation is achieved by configuring the lvcmos buffers to output hi-z instead of driving high when transmitting logic-1. figure 5-40. i2c transmit timing in are presented the specific groupings of signals (ioset) for use with i2c1/2/3/4/5. 5.10.6.11 hdq1w the module is intended to work with both hdq and 1-wire protocols. the protocols use a single wire to communicate between the master and the slave. the protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high. 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop i2ci_sda i2ci_scl 16 26 24 sprs906_timing_i2c_02 229 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note for more information, see the hdq / 1-wire section of the device trm. 5.10.6.11.1 hdq / 1-wire ? hdq mode table 5-59 and table 5-60 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-41 , figure 5-42 , figure 5-43 and figure 5-44 ). table 5-59. hdq/1-wire timing requirements ? hdq mode no. parameter description min max unit 1 t cych read bit window timing 190 250 s 2 t hw1 read one data valid after hdq low 32 (2) 66 (2) s 3 t hw0 read zero data hold after hdq low 70 (2) 145 (2) s 4 t rsps response time from hdq slave device (1) 190 320 s (1) defined by software. (2) if the hdq slave device drives a logic-low state after thw0 maximum, it can be interpreted as a break pulse. for more information see "hdq / 1-wire switching characteristics - hdq mode" and the hdq/1-wire chapter of the trm. table 5-60. hdq / 1-wire switching characteristics - hdq mode no. parameter description min max unit 5 t b break timing 190 s 6 t br break recovery time 40 s 7 t cycd write bit windows timing 190 s 8 t dw1 write one data valid after hdq low 0.5 50 s 9 t dw0 write zero data hold after hdq low 86 145 s figure 5-41. hdq break and break recovery timing ? hdq interface writing to slave figure 5-42. device hdq interface bit read timing (data) figure 5-43. device hdq interface bit write timing (command / address or data) hdq t dw1 t dw0 t cycd sprs906_timing_hdq1w_03 hdq t hw1 t hw0 t cych sprs906_timing_hdq1w_02 hdq t b t br sprs906_timing_hdq1w_01 230 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-44. hdq communication timing 5.10.6.11.2 hdq/1-wire ? 1-wire mode table 5-61 and table 5-62 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-45 , figure 5-46 and figure 5-47 ). table 5-61. hdq / 1-wire timing requirements - 1-wire mode no. parameter description min max unit 10 t pdh presence pulse delay high 15 60 s 11 t pdl presence pulse delay low 60 240 s 12 t rdv read data valid time t lowr 15 s 13 t rel read data release time 0 45 s table 5-62. hdq / 1-wire switching characteristics - 1-wire mode no. parameter description min max unit 14 t rstl reset time low 480 960 s 15 t rsth reset time high 480 s 16 t slot bit cycle time 60 120 s 17 t low1 write bit-one time 1 15 s 18 t low0 write bit-zero time (2) 60 120 s 19 t rec recovery time 1 s 20 t lowr read bit strobe time (1) 1 15 s (1) t lowr (low pulse sent by the master) must be short as possible to maximize the master sampling window. (2) t lowr must be less than t slot . figure 5-45. 1-wire ? break (reset) figure 5-46. 1-wire ? read bit (data) 1-wire t rsth t pdl t pdh t rtsl sprs906_timing_hdq1w_05 hdq break 0_(lsb) 1 6 7_(msb) t rsps 1 6 command_byte_written data_byte_received 0_(lsb) sprs906_timing_hdq1w_04 1-wire t lowr t rdv and_ _ t rel t slot _ _ and t rec sprs906_timing_hdq1w_06 231 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-47. 1-wire ? write bit-one timing (command / address or data) 5.10.6.12 uart the uart performs serial-to-parallel conversions on data received from a peripheral device and parallel- to-serial conversion on data received from the cpu. there are 10 uart modules in the device. only one uart supports irda features. each uart can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices the uarti (where i = 1 to 10) include the following features: ? 16c750 compatibility ? 64-byte fifo buffer for receiver and 64-byte fifo for transmitter ? baud generation based on programmable divisors n (where n = 1 ? 16 384) operating from a fixed functional clock of 48 mhz or 192 mhz ? break character detection and generation ? configurable data format: ? data bit: 5, 6, 7, or 8 bits ? parity bit: even, odd, none ? stop-bit: 1, 1.5, 2 bit(s) ? flow control: hardware (rts/cts) or software (xon/xoff) ? only uart1 module has extended modem control signals (cd, ri, dtr, dsr) ? only uart3 supports irda note for more information, see the uart section of the device trm. table 5-63 , table 5-64 and figure 5-48 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-63. timing requirements for uart no. parameter description min max unit 4 t w(rx) pulse width, receive data bit, 15/30/100pf high or low 0.96u (1) 1.05u (1) ns 5 t w(cts) pulse width, receive start bit, 15/30/100pf high or low 0.96u (1) 1.05u (1) ns t d(rts-tx) delay time, transmit start bit to transmit data p (2) ns t d(cts-tx) delay time, receive start bit to transmit data p (2) ns (1) u = uart baud time = 1/programmed baud rate (2) p = clock period of the reference clock (fclk, usually 48 mhz or 192mhz). table 5-64. switching characteristics over recommended operating conditions for uart no. parameter description min max unit f (baud) maximum programmable baud rate 15 pf 12 mhz 30 pf 0.23 100 pf 0.115 2 t w(tx) pulse width, transmit data bit, 15/30/100 pf high or low u - 2 (1) u + 2 (1) ns 1-wire t low1 t low0 t slot _ _ and t rec sprs906_timing_hdq1w_07 232 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-64. switching characteristics over recommended operating conditions for uart (continued) no. parameter description min max unit 3 t w(rts) pulse width, transmit start bit, 15/30/100 pf high or low u - 2 (1) u + 2 (1) ns (1) u = uart baud time = 1/programmed baud rate figure 5-48. uart timing in are presented the specific groupings of signals (ioset) for use with uart. 5.10.6.13 mcspi the mcspi is a master/slave synchronous serial bus. there are four separate mcspi modules (spi1, spi2, spi3, and spi4) in the device. all these four modules support up to four external devices (four chip selects) and are able to work as both master and slave. the mcspi modules include the following main features: ? serial clock with programmable frequency, polarity, and phase for each channel ? wide selection of spi word lengths, ranging from 4 to 32 bits ? up to four master channels, or single channel in slave mode ? master multichannel mode: ? full duplex/half duplex ? transmit-only/receive-only/transmit-and-receive modes ? flexible input/output (i/o) port controls per channel ? programmable clock granularity ? spi configuration per channel. this means, clock definition, polarity enabling and word width ? power management through wake-up capabilities ? programmable timing control between chip select and external clock generation ? built-in fifo available for a single channel. ? each spi module supports multiple chip select pins spim_cs[i], whete i = 1 to 4. note for more information, see the serial communication interface section of the device trm. note the mcspim module (m = 1 to 4) is also referred to as spim. 3 2 start bit data bits uarti_txd 5 data bits bit start 4 uarti_rxd sprs906_timing_uart_01 233 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated caution the i/o timings provided in this section are applicable for all combinations of signals for spi1 and spi2. however, the timings are valid only for spi3 and spi4 if signals within a single ioset are used. the iosets are defined in table 5-67 . table 5-65 , figure 5-49 and figure 5-50 present timing requirements for mcspi - master mode. table 5-65. timing requirements for spi - master mode (1) no. parameter description mode min max unit sm1 t c(spiclk) cycle time, spi_sclk (1) (2) spi1/2/3/ 4 20.8 (3) ns sm2 t w(spiclkl) typical pulse duration, spi_sclk low (1) 0.5 p-1 (4) ns sm3 t w(spiclkh) typical pulse duration, spi_sclk high (1) 0.5 p-1 (4) ns sm4 t su(miso-spiclk) setup time, spi_d[x] valid before spi_sclk active edge (1) 3.5 ns sm5 t h(spiclk-miso) hold time, spi_d[x] valid after spi_sclk active edge (1) 3.7 ns sm6 t d(spiclk-simo) delay time, spi_sclk active edge to spi_d[x] transition (1) spi1 -3.57 4.1 ns spi2 -3.9 3.6 ns spi3 -4.9 4.7 ns spi4 -4.3 4.5 ns sm7 t d(cs-simo) delay time, spi_cs[x] active edge to spi_d[x] transition 5 ns sm8 t d(cs-spiclk) delay time, spi_cs[x] active to spi_sclk first edge (1) master _pha0 (5) b-4.2 (6) ns master _pha1 (5) a-4.2 (7) ns sm9 t d(spiclk-cs) delay time, spi_sclk last edge to spi_cs[x] inactive (1) master _pha0 (5) a-4.2 (7) ns master _pha1 (5) b-4.2 (6) ns (1) this timing applies to all configurations regardless of spi_clk polarity and which clock edges are used to drive output data and capture input data. (2) related to the spi_clk maximum frequency. (3) 20.8ns cycle time = 48mhz (4) p = spiclk period. (5) spi_clk phase is programmable with the pha bit of the spi_ch(i)conf register. (6) b = (tcs + 0.5) tspiclkref fratio, where tcs is a bit field of the spi_ch(i)conf register and fratio = even 2. (7) when p = 20.8 ns, a = (tcs + 1) tspiclkref, where tcs is a bit field of the spi_ch(i)conf register. when p > 20.8 ns, a = (tcs + 0.5) fratio tspiclkref, where tcs is a bit field of the spi_ch(i)conf register. 234 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-49. mcspi - master mode transmit spim_cs(out) spi _sclk(out) m spi _sclk m (out) spi _m d(out) spim_cs(out) spi _sclk m (out) spi _sclk m (out) spi _m d(out) bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit0 pha=0epol=1 pol=0 pol=1 pha=1epol=1 pol=0 pol=1 sm8 sm9 sm6 sm3 sm1 sm2 sm1 sm8 sm9 sm3 sm1 sm2 sm1 sm6 sm7 sm6 sm2 sm3 sm2 sm3 sm6 sm6 sm6 sprs906_timing_mcspi_01 235 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-50. mcspi - master mode receive table 5-66 , figure 5-51 and figure 5-52 present timing requirements for mcspi - slave mode. table 5-66. timing requirements for spi - slave mode no. parameter description mode min max unit ss1 (1) t c(spiclk) cycle time, spi_sclk 62.5 (2) (3) ns ss2 (1) t w(spiclkl) typical pulse duration, spi_sclk low 0.45 p (4) ns ss3 (1) t w(spiclkh) typical pulse duration, spi_sclk high 0.45 p (4) ns ss4 (1) t su(simo-spiclk) setup time, spi_d[x] valid before spi_sclk active edge 5 ns ss5 (1) t h(spiclk-simo) hold time, spi_d[x] valid after spi_sclk active edge 5 ns ss6 (1) t d(spiclk-somi) delay time, spi_sclk active edge to mcspi_somi transition spi1/2/3 2 26.6 ns spi4 2 20.1 ns spim _cs(out) spi _sclk m (out) spi _sclk m (out) spi _m d (in) spim _cs(out) spi _sclk m (out) spi _sclk m (out) spi _m d (in) bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 pha=0epol=1 pha=1 epol=1 pol=0pol=1 pol=0 pol=1 sm8 sm9 sm3 sm1 sm2 sm1 sm8 sm9 sm3 sm1 sm2 sm1 sm2 sm3 sm2 sm3 sm4 sm5 sm4 sm5 sm4 sm4 sm5 sm5 sprs906_timing_mcspi_02 236 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-66. timing requirements for spi - slave mode (continued) no. parameter description mode min max unit ss7 (5) t d(cs-somi) delay time, spi_cs[x] active edge to mcspi_somi transition 20.95 ns ss8 (1) t su(cs-spiclk) setup time, spi_cs[x] valid before spi_sclk first edge 5 ns ss9 (1) t h(spiclk-cs) hold time, spi_cs[x] valid after spi_sclk last edge spi1/2 5 ns spi3 7.5 ns spi4 6 ns (1) this timing applies to all configurations regardless of spi_clk polarity and which clock edges are used to drive output data and capture input data. (2) when operating the spi interface in rx-only mode, the minimum cycle time is 26ns (38.4mhz) (3) 62.5ns cycle time = 16 mhz (4) p = spiclk period. (5) pha = 0; spi_clk phase is programmable with the pha bit of the spi_ch(i)conf register. figure 5-51. mcspi - slave mode transmit spim _cs(in) spi _sclk m (in) spi _sclk m (in) spi _m d (out) spim _cs(in) spi _sclk m (in) spi _sclk m (in) spi _m d (out) bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 pha=0epol=1 pol=0 pol=1 pol=0 pol=1 pha=1 epol=1 ss6 ss3 ss1 ss3 ss1 ss3 ss1 ss2 ss1 ss6 ss6 ss8 ss9 ss7 ss8 ss2 ss3 ss2 ss2 ss6 ss6 ss6 ss9 sprs906_timing_mcspi_03 237 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-52. mcspi - slave mode receive in table 5-67 are presented the specific groupings of signals (ioset) for use with spi3 and spi4. table 5-67. mcspi3/4 iosets signals ioset1 ioset2 ioset3 ioset4 ioset5 ball mux ball mux ball mux ball mux ball mux mcspi3 spi3_cs0 t5 7 b18 3 d23 2 aa3 1 spi3_cs1 w2 1 a19 3 w2 1 spi3_d0 t4 7 b16 3 a24 2 aa2 1 spi3_d1 n6 7 b17 3 b25 2 y4 1 spi3_sclk n5 7 a18 3 c23 2 y1 1 mcspi4 spi4_cs0 l3 8 b9 8 r1 7 ac4 2 ab1 1 spi4_cs1 g1 8 g1 8 n6 8 n6 8 n6 8 spi4_cs2 h3 8 h3 8 t4 8 t4 8 t4 8 spim _cs(in) spi _sclk m (in) spi _sclk m (in) spi _m d (in) spim _cs(in) spi _sclk m (in) spi _sclk m (in) spi _m d (in) bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 pha=0epol=1 pol=0 pol=1 pol=0 pol=1 pha=1 epol=1 ss3 ss1 ss3 ss1 ss3 ss1 ss2 ss1 ss8 ss9 ss8 ss9 ss2 ss3 ss2 ss2 ss4 ss5 ss5 ss4 ss4 ss5 ss4 ss5 sprs906_timing_mcspi_04 238 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-67. mcspi3/4 iosets (continued) signals ioset1 ioset2 ioset3 ioset4 ioset5 ball mux ball mux ball mux ball mux ball mux spi4_cs3 h4 8 h4 8 t5 8 t5 8 t5 8 spi4_d0 j2 8 c8 8 r2 7 aa5 2 aa4 1 spi4_d1 h1 8 b8 8 p3 7 u6 2 aa1 1 spi4_sclk k4 8 e8 8 p4 7 ac3 2 y3 1 5.10.6.14 qspi the quad spi (qspi) module is a type of spi module that allows single, dual or quad read access to external spi devices. this module has a memory mapped register interface, which provides a direct interface for accessing data from external spi devices and thus simplifying software requirements. it works as a master only. there is one qspi module in the device and it is primary intended for fast booting from quad-spi flash memories. general spi features: ? programmable clock divider ? six pin interface (dclk, cs_n, dout, din, qdin1, qdin2) ? 4 external chip select signals ? support for 3-, 4- or 6-pin spi interface ? programmable cs_n to dout delay from 0 to 3 dclks ? programmable signal polarities ? programmable active clock edge ? software controllable interface allowing for any type of spi transfer note for more information, see the quad serial peripheral interface section of the device trm. caution the i/o timings provided in this section are only valid when all qspi chip selects used in a system are configured to use the same clock mode (either clock mode 0 or clock mode 3). caution the i/o timings provided in this section are valid only for some qspi usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-68 and table 5-69 present timing and switching characteristics for quad spi interface. table 5-68. switching characteristics for qspi no. parameter description mode min max unit q1 t c(sclk) cycle time, sclk default timing mode, clock mode 0 11.71 ns default timing mode, clock mode 3 20.8 ns 239 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-68. switching characteristics for qspi (continued) no. parameter description mode min max unit q2 t w(sclkl) pulse duration, sclk low y p-1 (1) ns q3 t w(sclkh) pulse duration, sclk high y p-1 (1) ns q4 t d(cs-sclk) delay time, sclk falling edge to cs active edge, cs3:0 default timing mode -m p- 1.6 (2) (3) -m p+2.6 (2) (3) ns q5 t d(sclk-cs) delay time, sclk falling edge to cs inactive edge, cs3:0 default timing mode n p- 1.6 (2) (3) n p+2.6 (2) (3) ns q6 t d(sclk-d0) delay time, sclk falling edge to d[0] transition default timing mode -1.6 2.6 ns q7 t ena(cs-d0lz) enable time, cs active edge to d[0] driven (lo-z) -p-3.5 -p+2.5 ns q8 t dis(cs-d0z) disable time, cs active edge to d[0] tri-stated (hi-z) -p-2.5 -p+2.0 ns q9 t d(sclk-d0) delay time, sclk first falling edge to first d[0] transition pha=0 only, default timing mode -1.6- p (2) 2.6-p (2) ns (1) the y parameter is defined as follows: if dclk_div is 0 or odd then, y equals 0.5. if dclk_div is even then, y equals (dclk_div/2) / (dclk_div+1). for best performance, it is recommended to use a dclk_div of 0 or odd to minimize the duty cycle distortion. the hsdivider on clkoutx2_h13 output of dpll_per can be used to achieve the desired clock divider ratio. all required details about clock division factor dclk_div can be found in the device-specific technical reference manual. (2) p = sclk period. (3) m=qspi_spi_dc_reg.ddx + 1 when clock mode 0. m=qspi_spi_dc_reg.ddx when clock mode 3. n = 2 when clock mode 0. n = 3 when clock mode 3. figure 5-53. qspi read (clock mode 3) cs sclk d[0] d[3:1] bit n-1 bit n-2 bit 1 bit 0 pha=1 pol=1 command command read data read data bit 1 bit 0 read data read data q4 q7 q6 q3 q2 q1 q6 q5 sprs91v_qspi_01 q12 q13 q14 q15 q12 q13 q15 q14 240 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-54. qspi read (clock mode 0) caution the i/o timings provided in this section are valid only for some qspi usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-69. timing requirements for qspi (3) (2) no. parameter description mode min max unit q2 t su(d-rtclk) setup time, d[3:0] valid before falling rtclk edge default timing mode, clock mode 0 4.6 ns t su(d-sclk) setup time, d[3:0] valid before falling sclk edge default timing mode, clock mode 3 12.3 ns q13 t h(rtclk-d) hold time, d[3:0] valid after falling rtclk edge default timing mode, clock mode 0 -0.1 ns t h(sclk-d) hold time, d[3:0] valid after falling sclk edge default timing mode, clock mode 3 0.1 ns q14 t su(d-sclk) setup time, final d[3:0] bit valid before final falling sclk edge default timing mode, clock mode 3 12.3-p (1) ns q15 t h(sclk-d) hold time, final d[3:0] bit valid after final falling sclk edge default timing mode, clock mode 3 0.1+p (1) ns cs sclk rtclk d[0] d[3:1] bit n-1 bit n-2 bit 1 bit 0 pha=0 pol=0 pol=0 command command read data read data bit 1 bit 0 read data read data q4 q7 q9 q2 q3 q1 q6 q5 sprs91v_qspi_02 q12 q13 q12 q13 q12 q13 q12 q13 241 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = sclk period. (2) clock modes 1 and 2 are not supported. (3) the device captures data on the falling clock edge in clock mode 0 and 3, as opposed to the traditional rising clock edge. although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard spi devices that launch data on the falling edge in clock modes 0 and 3. figure 5-55. qspi write (clock mode 3) figure 5-56. qspi write (clock mode 0) caution the i/o timings provided in this section are valid only for some qspi usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. cs sclk d[0] d[3:1] bit n-1 bit n-2 bit 1 bit 0 pha=1 pol=1 command command write data write data q4 q7 q6 q3 q2 q1 q6 q6 q5 sprs91v_qspi_03 q8 q6 cs sclk d[0] d[3:1] bit n-1 bit n-2 bit 1 bit 0 pha=0 pol=0 command command write data write data q4 q7 q2 q3 q1 q6 q6 q5 sprs91v_qspi_04 q8 q9 q6 242 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated note to configure the desired manual io timing mode the user must follow the steps described in section manual io timing modes of the device trm. the associated registers to configure are listed in the cfg register column. for more information see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for qspi. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-70 manual functions mapping for qspi for a definition of the manual modes. table 5-70 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-70. manual functions mapping for qspi ball ball name qspi1_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 1 l1 gpmc_a3 0 0 cfg_gpmc_a3_out qspi1_cs2 k3 gpmc_a4 0 0 cfg_gpmc_a4_out qspi1_cs3 h3 gpmc_a13 0 0 cfg_gpmc_a13_in qspi1_rtclk h4 gpmc_a14 2247 1186 cfg_gpmc_a14_in qspi1_d3 k6 gpmc_a15 2176 1197 cfg_gpmc_a15_in qspi1_d2 k5 gpmc_a16 2229 1268 cfg_gpmc_a16_in qspi1_d0 k5 gpmc_a16 0 0 cfg_gpmc_a16_out qspi1_d0 g2 gpmc_a17 2251 1217 cfg_gpmc_a17_in qspi1_d1 f2 gpmc_a18 0 0 cfg_gpmc_a18_out qspi1_sclk g4 gpmc_cs2 0 0 cfg_gpmc_cs2_out qspi1_cs0 g3 gpmc_cs3 0 0 cfg_gpmc_cs3_out qspi1_cs1 5.10.6.15 mcasp the multichannel audio serial port (mcasp) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. the mcasp is useful for time-division multiplexed (tdm) stream, inter-integrated sound (i2s) protocols, and intercomponent digital audio interface transmission (dit). the device have integrated 8 mcasp modules (mcasp1-mcasp8) with: ? mcasp1 and mcasp2 modules supporting 16 channels with independent tx/rx clock/sync domain ? mcasp3 through mcasp7 modules supporting 4 channels with independent tx/rx clock/sync domain ? mcasp8 module supporting 2 channels with independent tx/rx clock/sync domain note for more information, see the serial communication interface section of the device trm. caution the i/o timings provided in this section are valid only for some mcasp usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-71 , table 5-72 , table 5-73 and figure 5-57 present timing requirements for mcasp1 to mcasp8. 243 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-71. timing requirements for mcasp1 (1) no. parameter description mode min max unit 1 t c(ahclkx) cycle time, ahclkx 20 ns 2 t w(ahclkx) pulse duration, ahclkx high or low 0.35p (2) ns 3 t c(aclkrx) cycle time, aclkr/x 20 ns 4 t w(aclkrx) pulse duration, aclkr/x high or low 0.5r - 3 (3) ns 5 t su(afsrx-aclk) setup time, afsr/x input valid before aclkr/x aclkr/x int 20.5 ns aclkr/x ext in aclkr/x ext out 4 ns 6 t h(aclk-afsrx) hold time, afsr/x input valid after aclkr/x aclkr/x int -1 ns aclkr/x ext in aclkr/x ext out 1.7 ns 7 t su(axr-aclk) setup time, axr input valid before aclkr/x aclkr/x int 21.6 ns aclkr/x ext in aclkr/x ext out 11.5 ns 8 t h(aclk-axr) hold time, axr input valid after aclkr/x aclkr/x int -1 ns aclkr/x ext in aclkr/x ext out 1.8 ns (1) aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkr/x period in ns. table 5-72. timing requirements for mcasp2 (1) no. parameter description mode min max unit 1 t c(ahclkx) cycle time, ahclkx 20 ns 2 t w(ahclkx) pulse duration, ahclkx high or low 0.35p (2) ns 3 t c(aclkx) cycle time, aclkx any other conditions 20 ns aclkx/afsx (in sync mode) and axr are all inputs " 80m " virtual io timing modes 12.5 ns 4 t w(aclkx) pulse duration, aclkx high or low any other conditions 0.5r - 3 (3) ns aclkx/afsx (in sync mode) and axr are all inputs " 80m " virtual io timing modes 0.38r (3) ns 5 t su(afsx-aclk) setup time, afsx input valid before aclkx aclkx int 20.3 ns aclkx ext in aclkx ext out 4.5 ns aclkx ext in aclkx ext out " 80m " virtual io timing modes 3 ns 244 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-72. timing requirements for mcasp2 (1) (continued) no. parameter description mode min max unit 6 t h(aclk-afsx) hold time, afsx input valid after aclkx aclkx int -1 ns aclkx ext in aclkx ext out 1.8 ns aclkx ext in aclkx ext out " 80m " virtual io timing modes 3 ns 7 t su(axr-aclk) setup time, axr input valid before aclkx aclkx int 21.1 ns aclkx ext in aclkx ext out 4.5 ns aclkx ext in aclkx ext out " 80m " virtual io timing modes 3 ns 8 t h(aclk-axr) hold time, axr input valid after aclkx aclkx int -1 ns aclkx ext in aclkx ext out 1.8 ns aclkx ext in aclkx ext out " 80m " virtual io timing modes 3 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkx period in ns. table 5-73. timing requirements for mcasp3/4/5/6/7/8 (1) no. parameter description mode min max unit 1 t c(ahclkx) cycle time, ahclkx 20 ns 2 t w(ahclkx) pulse duration, ahclkx high or low 0.35p (2) ns 3 t c(aclkrx) cycle time, aclkr/x 20 ns 4 t w(aclkrx) pulse duration, aclkr/x high or low 0.5r - 3 (3) ns 5 t su(afsrx-aclk) setup time, afsr/x input valid before aclkr/x aclkr/x int 19.7 ns aclkr/x ext in aclkr/x ext out 5.6 ns 6 t h(aclk-afsrx) hold time, afsr/x input valid after aclkr/x aclkr/x int -1.1 ns aclkr/x ext in aclkr/x ext out 2.5 ns t su(axr-aclk) setup time, axr input valid before aclkx aclkx int (async=0) 20.3 ns aclkr/x ext in aclkr/x ext out 5.1 ns 8 t h(aclk-axr) hold time, axr input valid after aclkx aclkx int (async=0) -0.8 ns aclkr/x ext in aclkr/x ext out 2.5 ns (1) aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 (not supported) aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkr/x period in ns. 245 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated a. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). b. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). figure 5-57. mcasp input timing caution the i/o timings provided in this section are valid only for some mcasp usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-74 , table 5-75 , table 5-76 and figure 5-58 present switching characteristics over recommended operating conditions for mcasp1 to mcasp8. 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkx (falling edge polarity) ahclkx (rising edge polarity) afsr/x (bit width, 0 bit delay)afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) (a) aclkr/x (clkrp = clkxp = 1) (b) sprs906_timing_mcasp_01 246 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-74. switching characteristics over recommended operating conditions for mcasp1 (1) no. parameter description mode min max unit 9 t c(ahclkx) cycle time, ahclkx 20 ns 10 t w(ahclkx) pulse duration, ahclkx high or low 0.5p - 2.5 (2) ns 11 t c(aclkrx) cycle time, aclkr/x 20 ns 12 t w(aclkrx) pulse duration, aclkr/x high or low 0.5p - 2.5 (3) ns 13 t d(aclk-afsxr) delay time, aclkr/x transmit edge to afsx/r output valid aclkr/x int -0.9 6 ns aclkr/x ext in aclkr/x ext out 2 23.1 ns 14 t d(aclk-axr) delay time, aclkr/x transmit edge to axr output valid aclkr/x int -1.4 6 ns aclkr/x ext in aclkr/x ext out 2 24.2 ns (1) aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkr/x period in ns. table 5-75. switching characteristics over recommended operating conditions for mcasp2 (1) no. parameter description mode min max unit 9 t c(ahclkx) cycle time, ahclkx 20 ns 10 t w(ahclkx) pulse duration, ahclkx high or low 0.5p - 2.5 (2) ns 11 t c(aclkx) cycle time, aclkx 20 ns 12 t w(aclkx) pulse duration, aclkx high or low 0.5p - 2.5 (3) ns 13 t d(aclk-afsx) delay time, aclkx transmit edge to afsx output valid aclkx int -1 6 ns aclkx ext in aclkx ext out 2 23.2 ns 14 t d(aclk-axr) delay time, aclkx transmit edge to axr output valid aclkx int -1.3 6 ns aclkx ext in aclkx ext out 2 23.7 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkx period in ns. table 5-76. switching characteristics over recommended operating conditions for mcasp3/4/5/6/7/8 (1) no. parameter description mode min max unit 9 t c(ahclkx) cycle time, ahclkx 20 ns 10 t w(ahclkx) pulse duration, ahclkx high or low 0.5p - 2.5 (2) ns 11 t c(aclkrx) cycle time, aclkr/x 20 ns 12 t w(aclkrx) pulse duration, aclkr/x high or low 0.5p - 2.5 (3) ns 247 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-76. switching characteristics over recommended operating conditions for mcasp3/4/5/6/7/8 (1) (continued) no. parameter description mode min max unit 13 t d(aclk-afsxr) delay time, aclkr/x transmit edge to afsx/r output valid aclkr/x int -0.5 6 ns aclkr/x ext in aclkr/x ext out 1.9 24.5 ns 14 t d(aclk-axr) delay time, aclkr/x transmit edge to axr output valid aclkr/x int -1.4 7.1 ns aclkr/x ext in aclkr/x ext out 1.1 24.2 ns (1) aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 (2) p = ahclkx period in ns. (3) r = aclkr/x period in ns. 248 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated a. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). b. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). figure 5-58. mcasp output timing note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . table 5-77 through table 5-84 explain all cases with virtual mode details for mcasp1/2/3/4/5/6 /7/8 (see figure 5-59 through figure 5-66 ). 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkx (falling edge polarity) ahclkx (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay)afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/t ransmit) aclkr/x (clkrp = clkxp = 0) (b) aclkr/x (clkrp = clkxp = 1) (a) sprs906_timing_mcasp_02 249 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-77. virtual mode case details for mcasp1 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp1_virtual2_async_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp1_virtual2_async_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp1_virtual2_async_rx see figure 5-61 axr(inputs)/clkr/fsr default (no virtual mode) 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp1_virtual2_async_rx see figure 5-62 axr(inputs)/clkr/fsr default (no virtual mode) ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp1_virtual1_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp1_virtual1_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp1_virtual1_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp1_virtual1_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) table 5-78. virtual mode case details for mcasp2 no. case case description virtual mode settings notes signals virtual mode value ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp2_virtual3_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp2_virtual3_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp2_virtual3_sync_rx (1) see figure 5-65 axr(inputs)/clkx/fsx mcasp2_virtual3_sync_rx (1) axr(inputs)/clkx/fsx mcasp2_virtual1_sync_rx_80m (2) 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) (1) used up to 50mhz. should also be used in a ci-fi- mixed case where axr operate as both inputs and outputs (that is, axr are bidirectional). (2) used in 80mhz input only mode when axr, clkx and fsx are all inputs. table 5-79. virtual mode case details for mcasp3 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp3_virtual2_sync_rx 250 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-79. virtual mode case details for mcasp3 (continued) no. case case description virtual mode settings notes signals virtual mode value 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp3_virtual2_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp3_virtual2_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp3_virtual2_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp3_virtual2_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp3_virtual2_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp3_virtual2_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp3_virtual2_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp3_virtual2_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp3_virtual2_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) table 5-80. virtual mode case details for mcasp4 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp4_virtual1_sync_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp4_virtual1_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp4_virtual1_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp4_virtual1_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp4_virtual1_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp4_virtual1_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp4_virtual1_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp4_virtual1_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp4_virtual1_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp4_virtual1_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) 251 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-81. virtual mode case details for mcasp5 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp5_virtual1_sync_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp5_virtual1_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp5_virtual1_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp5_virtual1_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp5_virtual1_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp5_virtual1_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp5_virtual1_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp5_virtual1_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp5_virtual1_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp5_virtual1_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) table 5-82. virtual mode case details for mcasp6 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp6_virtual1_sync_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp6_virtual1_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp6_virtual1_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp6_virtual1_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp6_virtual1_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp6_virtual1_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp6_virtual1_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp6_virtual1_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp6_virtual1_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp6_virtual1_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) 252 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-83. virtual mode case details for mcasp7 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp7_virtual2_sync_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp7_virtual2_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp7_virtual2_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp7_virtual2_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp7_virtual2_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp7_virtual2_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp7_virtual2_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp7_virtual2_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp7_virtual2_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp7_virtual2_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) table 5-84. virtual mode case details for mcasp8 no. case case description virtual mode settings notes signals virtual mode value ip mode : async 1 coifoi clkx / fsx: output clkr / fsr: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-59 axr(inputs)/clkr/fsr mcasp8_virtual1_sync_rx 2 coifio clkx / fsr: output clkr / fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-60 axr(inputs)/clkr/fsr mcasp8_virtual1_sync_rx 3 ciofio clkr / fsr: output clkx / fsx: input axr(outputs)/clkx/fsx mcasp8_virtual1_sync_rx see figure 5-61 axr(inputs)/clkr/fsr mcasp8_virtual1_sync_rx 4 ciofoi clkr / fsx: output clkx / fsr: input axr(outputs)/clkx/fsx mcasp8_virtual1_sync_rx see figure 5-62 axr(inputs)/clkr/fsr mcasp8_virtual1_sync_rx ip mode : sync (clkr / fsr internally generated from clkx / fsx) 5 co-fo- clkx / fsx: output axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-63 axr(inputs)/clkx/fsx default (no virtual mode) 6 ci-fo- fsx: output clkx: input axr(outputs)/clkx/fsx mcasp8_virtual1_sync_rx see figure 5-64 axr(inputs)/clkx/fsx mcasp8_virtual1_sync_rx 7 ci-fi- clkx / fsx: input axr(outputs)/clkx/fsx mcasp8_virtual1_sync_rx see figure 5-65 axr(inputs)/clkx/fsx mcasp8_virtual1_sync_rx 8 co-fi- clkx: output fsx: input axr(outputs)/clkx/fsx default (no virtual mode) see figure 5-66 axr(inputs)/clkx/fsx default (no virtual mode) 253 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-59. mcasp1-8 coifoi ? async mode figure 5-60. mcasp1-8 coifio ? async mode mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_02 mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_01 254 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-61. mcasp1-8 ciofio ? async mode figure 5-62. mcasp1-8 ciofoi ? async mode mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_03 mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_04 255 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-63. mcasp1-8 co-fo- ? sync mode figure 5-64. mcasp1-8 ci-fo- ? sync mode mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_05 mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_06 256 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-65. mcasp1-8 ci-fi- ? sync mode figure 5-66. mcasp1-8 co-fi- ? sync mode mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_07 mcasp clkx fsx txdata clkr fsr rxdata soc ios sprs906_mcasp_uc_08 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 257 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 virtual io timings modes must be used to guaranteed some io timings for mcasp1. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-85 virtual functions mapping for mcasp1 for a definition of the virtual modes. table 5-85 presents the values for delaymode bitfield. table 5-85. virtual functions mapping for mcasp1 ball ball name delay mode value muxmode mcasp1_virtual1_sync_rx mcasp1_virtual2_async_rx 0 1 2 c16 mcasp1_aclkx 15 14 mcasp1_aclkx h21 gpio6_14 14 13 mcasp1_axr8 e17 mcasp1_axr13 15 14 mcasp1_axr13 a15 mcasp1_axr4 14 13 mcasp1_axr4 h24 xref_clk2 14 13 mcasp1_axr6 b17 mcasp1_axr9 15 14 mcasp1_axr9 a16 mcasp1_axr7 14 13 mcasp1_axr7 a19 mcasp1_axr12 15 14 mcasp1_axr12 k23 gpio6_16 14 13 mcasp1_axr10 k22 gpio6_15 14 13 mcasp1_axr9 h25 xref_clk3 14 13 mcasp1_axr7 a17 mcasp1_axr6 14 13 mcasp1_axr6 b16 mcasp1_axr10 15 14 mcasp1_axr10 d17 mcasp1_fsr n/a 14 mcasp1_fsr a18 mcasp1_axr8 15 14 mcasp1_axr8 b18 mcasp1_axr11 15 14 mcasp1_axr11 c14 mcasp1_axr2 14 13 mcasp1_axr2 c17 mcasp1_fsx 15 14 mcasp1_fsx e16 mcasp1_axr14 15 14 mcasp1_axr14 f16 mcasp1_axr15 15 14 mcasp1_axr15 b14 mcasp1_axr1 15 14 mcasp1_axr1 d16 mcasp1_aclkr n/a 14 mcasp1_aclkr a14 mcasp1_axr5 14 13 mcasp1_axr5 j24 xref_clk1 15 14 mcasp1_axr5 d14 mcasp1_axr0 15 14 mcasp1_axr0 b15 mcasp1_axr3 14 13 mcasp1_axr3 j25 xref_clk0 15 14 mcasp1_axr4 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 258 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com virtual io timings modes must be used to guaranteed some io timings for mcasp2. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-86 virtual functions mapping for mcasp2 for a definition of the virtual modes. table 5-86 presents the values for delaymode bitfield. table 5-86. virtual functions mapping for mcasp2 ball ball name delay mode value muxmode mcasp2_virtual1 _sync_rx_80m mcasp2_virtual2 _async_rx mcasp2_virtual3 _sync_rx mcasp2_virtual4 _async_rx_80m 0 1 2 b22 mcasp3_axr0 15 14 10 9 mcasp2_axr14 d20 mcasp2_axr6 14 13 12 11 mcasp2_axr6 c19 mcasp2_axr5 14 13 12 11 mcasp2_axr5 d19 mcasp2_fsx 15 14 10 9 mcasp2_fsx h24 xref_clk2 12 11 10 9 mcasp2_axr10 b21 mcasp2_axr3 15 14 10 9 mcasp2_axr3 a22 mcasp3_aclkx 15 14 10 9 mcasp2_axr12 e19 mcasp2_aclkx 15 14 10 9 mcasp2_aclkx c20 mcasp2_axr7 14 13 12 11 mcasp2_axr7 h25 xref_clk3 12 11 10 9 mcasp2_axr11 b23 mcasp3_axr1 15 14 10 8 mcasp2_axr15 a23 mcasp3_fsx 15 14 10 9 mcasp2_axr13 a21 mcasp2_axr2 15 14 10 9 mcasp2_axr2 b20 mcasp2_axr4 14 13 12 11 mcasp2_axr4 j24 xref_clk1 10 9 8 6 mcasp2_axr9 b19 mcasp2_axr1 14 13 12 11 mcasp2_axr1 a20 mcasp2_axr0 14 13 12 11 mcasp2_axr0 j25 xref_clk0 10 9 8 6 mcasp2_axr8 virtual io timings modes must be used to guaranteed some io timings for mcasp3/4/5/6/7/8. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-87 virtual functions mapping for mcasp3/4/5/6/7/8 for a definition of the virtual modes. table 5-87 presents the values for delaymode bitfield. copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 259 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-87. virtual functions mapping for mcasp3/4/5/6/7/8 ball ball name delay mode value muxmode 0 1 2 mcasp3_virtual2_sync_rx b21 mcasp2_axr3 8 mcasp3_axr3 a22 mcasp3_aclkx 8 mcasp3_aclkx mcasp3_aclkr b22 mcasp3_axr0 8 mcasp3_axr0 b23 mcasp3_axr1 6 mcasp3_axr1 a23 mcasp3_fsx 8 mcasp3_fsx mcasp3_fsr a21 mcasp2_axr2 8 mcasp3_axr2 mcasp4_virtual1_sync_rx b25 mcasp4_fsx 14 mcasp4_fsx mcasp4_fsr c23 mcasp4_aclkx 14 mcasp4_aclkx mcasp4_aclkr a24 mcasp4_axr0 14 mcasp4_axr0 d23 mcasp4_axr1 14 mcasp4_axr1 a14 mcasp1_axr5 12 mcasp4_axr3 a15 mcasp1_axr4 12 mcasp4_axr2 mcasp5_virtual1_sync_rx ac3 mcasp5_aclkx 14 mcasp5_aclkx mcasp5_aclkr u6 mcasp5_fsx 14 mcasp5_fsx mcasp5_fsr ac4 mcasp5_axr1 14 mcasp5_axr1 a17 mcasp1_axr6 12 mcasp5_axr2 aa5 mcasp5_axr0 14 mcasp5_axr0 a16 mcasp1_axr7 12 mcasp5_axr3 mcasp6_virtual1_sync_rx c14 mcasp1_axr2 12 mcasp6_axr2 b15 mcasp1_axr3 12 mcasp6_axr3 b16 mcasp1_axr10 10 mcasp6_aclkx mcasp6_aclkr b17 mcasp1_axr9 10 mcasp6_axr1 a18 mcasp1_axr8 10 mcasp6_axr0 b18 mcasp1_axr11 10 mcasp6_fsx mcasp6_fsr mcasp7_virtual2_sync_rx a19 mcasp1_axr12 10 mcasp7_axr0 f16 mcasp1_axr15 10 mcasp7_fsx mcasp7_fsr e16 mcasp1_axr14 10 mcasp7_aclkx mcasp7_aclkr copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 260 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com table 5-87. virtual functions mapping for mcasp3/4/5/6/7/8 (continued) ball ball name delay mode value muxmode 0 1 2 e17 mcasp1_axr13 10 mcasp7_axr1 d16 mcasp1_aclkr 13 mcasp7_axr2 d17 mcasp1_fsr 13 mcasp7_axr3 mcasp8_virtual1_sync_rx b20 mcasp2_axr4 10 mcasp8_axr0 c20 mcasp2_axr7 10 mcasp8_fsx mcasp8_fsr d20 mcasp2_axr6 10 mcasp8_aclkx mcasp8_aclkr c19 mcasp2_axr5 10 mcasp8_axr1 261 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.16 usb superspeed usb drd subsystem has four instances in the device providing the following functions: ? usb1: superspeed (ss) usb 3.0 dual-role-device (drd) subsystem with integrated ss (usb3.0) phy and hs/fs (usb2.0) phy. ? usb2: high-speed (hs) usb 2.0 dual-role-device (drd) subsystem with integrated hs/fs phy. ? usb3: hs usb 2.0 dual-role-device (drd) subsystem with ulpi (sdr) interface to external hs/fs phys. note for more information, see the superspeed usb drd section of the device trm. 5.10.6.16.1 usb1 drd phy the usb1 drd interface supports the following applications: ? usb2.0 high-speed phy port (1.8 v and 3.3 v): this asynchronous high-speed interface is compliant with the usb2.0 phy standard with an internal transceiver (usb2.0 standard v2.0), for a maximum data rate of 480 mbps. ? usb3.0 super-speed phy port (1.8 v): this asynchronous differential super-speed interface is compliant with the usb3.0 rx/tx phy standard (usb3.0 standard v1.0) for a maximum data bit rate of 5gbps. 5.10.6.16.2 usb2 phy the usb2 interface supports the following applications: ? usb2.0 high-speed phy port (1.8 v and 3.3 v): this asynchronous high-speed interface is compliant with the usb2.0 phy standard with an internal transceiver (usb2.0 standard v2.0), for a maximum data rate of 480 mbps. 5.10.6.16.3 usb3 drd ulpi ? sdr ? slave mode ? 12-pin mode theusb3 drd interfaces support the following application: ? usb ulpi port: this synchronous interface is compliant with the usb2.0 ulpi sdr standard (utmi+ v1.22), for alternative off-chip usb2.0 phy interface; that is, with external transceiver with a maximum frequency of 60 mhz (synchronous slave mode, sdr, 12-pin, 8-data-bit). note the universal serial bus k ulpi modules are also refered as usbk where k = 3, 4. table 5-88 , table 5-89 and figure 5-67 assume testing over the recommended operating conditions and electrical characteristic conditions. table 5-88. timing requirements for ulpi sdr slave mode no. parameter description min max unit us1 t c(clk) cycle time, usb_ulpi_clk period 16.66 ns us5 t su(ctrlv-clkh) setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk rising edge 6.73 ns us6 t h(clkh-ctrlv) hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk rising edge -0.41 ns us7 t su(dv-clkh) setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge 6.73 ns us8 t h(clkh-dv) hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge -0.41 ns 262 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-89. switching characteristics for ulpi sdr slave mode no. parameter description min max unit us4 t d(clkh-stpv) delay time, usb_ulpi_clk rising edge high to output usb_ulpi_stp valid 0.44 8.35 ns us9 t d(clkl-dov) delay time, usb_ulpi_clk rising edge high to output usb_ulpi_d[7:0] valid 0.44 8.35 ns figure 5-67. hs usb3 ulpi ? sdr ? slave mode ? 12-pin mode in table 5-90 are presented the specific groupings of signals (ioset) for use with usb3 signals. table 5-90. usb3 iosets signals ioset2 ioset3 ball mux ball mux usb3_ulpi_d7 y5 3 n4 6 usb3_ulpi_d6 y6 3 n3 6 usb3_ulpi_d5 y2 3 p1 6 usb3_ulpi_d4 y1 3 n1 6 usb3_ulpi_d3 y4 3 p2 6 usb3_ulpi_d2 aa2 3 n2 6 usb3_ulpi_d1 aa3 3 r1 6 usb3_ulpi_d0 w2 3 r2 6 usb3_ulpi_nxt y3 3 p3 6 usb3_ulpi_dir aa1 3 p4 6 usb3_ulpi_stp aa4 3 t5 6 usb3_ulpi_clk ab1 3 t4 6 5.10.6.17 pcie the device supports connections to pcie-compliant devices via the integrated pcie master/slave bus interface. the pcie module is comprised of a dual-mode pcie core and a serdes phy. each pcie subsystem controller has support for pcie gen-ii mode (5.0 gbps /lane) and gen-i mode (2.5 gbps/lane) (single lane and flexible dual lane configuration). the device pcie supports the following features: ? 16-bit operation @250 mhz on pipe interface (per 16-bit lane) ? supports 2 ports x 1 lane or 1 port x 2 lanes configuration ? single virtual channel (vc0), single traffic class (tc0) ? single function in end-point mode usbk_ulpi_clk usbk_ulpi_stp usbk_ulpi_dir_&_nxt usbk_ulpi_d[7:0] data_in data_out us1 us8 us7 us9 us9 us2 us3 us4 us4 us5 us6 sprs906_timing_usb_01 263 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated ? automatic width and speed negotiation ? max payload: 128 byte outbound, 256 byte inbound ? automatic credit management ? ecrc generation and checking ? configurable bar filtering ? legacy interrupt reception (rc) and generation (ep) ? msi generation and reception ? pci express active state power management (aspm) state l0s and l1 (with exceptions) ? all pci device power management d-states with the exception of d3 cold / l2 state the pcie controller on this device conforms to the pci express base 3.0 specification, revision 1.0 and the pci local bus specification, revision 3.0. note for more information, see the pcie controller section of the device trm. 5.10.6.18 dcan the device provides two dcan interfaces for supporting distributed realtime control with a high level of security. the dcan interfaces implement the following features: ? supports can protocol version 2.0 part a, b ? bit rates up to 1 mbit/s ? 64 message objects ? individual identifier mask for each message object ? programmable fifo mode for message objects ? programmable loop-back modes for self-test operation ? suspend mode for debug support ? software module reset ? automatic bus on after bus-off state by a programmable 32-bit timer ? direct access to message ram during test mode ? can rx/tx pins are configurable as general-purpose io pins ? two interrupt lines (plus additional parity-error interrupts line) ? ram initialization ? dma support note for more information, see the dcan section of the device trm. note the controller area network interface x (x = 1 to 2) is also referred to as dcanx. note refer to the can specification for calculations necessary to validate timing compliance. jitter tolerance calculations must be performed to validate the implementation. table 5-91 and table 5-92 present timing and switching characteristics for dcanx interface. 264 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-91. timing requirements for dcanx receive no. parameter description min nom max unit - f (baud) maximum programmable baud rate 1 mbps - t d(dcanrx) delay time, dcanx_rx pin to receive shift register 15 ns table 5-92. switching characteristics over recommended operating conditions for dcanx transmit no. parameter description min max unit - f (baud) maximum programmable baud rate 1 mbps - t d(dcantx) delay time, transmit shift register to dcanx_tx pin (1) 23 ns (1) these values do not include rise/fall times of the output buffer. 5.10.6.19 gmac_sw the three-port gigabit ethernet switch subsystem (gmac_sw) provides ethernet packet communication and can be configured as an ethernet switch. it provides the gigabit media independent interface (g/mii) in mii mode, reduced gigabit media independent interface (rgmii), reduced media independent interface (rmii), and the management data input/output (mdio) for physical layer device (phy) management. note for more information, see the ethernet subsystem section of the device trm. note the gigabit, reduced and media independent interface n (n = 0 to 1) are also referred to as miin, rmiin and rgmiin. caution the i/o timings provided in this section are valid only if signals within a single ioset are used. the iosets are defined in table 5-97 , table 5-100 , table 5- 105 and table 5-112 . caution the i/o timings provided in this section are valid only for some gmac usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. 5.10.6.19.1 gmac mii timings table 5-93 and figure 5-68 present timing requirements for miin in receive operation. table 5-93. timing requirements for miin_rxclk - mii operation no. parameter description speed min max unit 1 t c(rx_clk) cycle time, miin_rxclk 10 mbps 400 ns 100 mbps 40 ns 2 t w(rx_clkh) pulse duration, miin_rxclk high 10 mbps 140 260 ns 100 mbps 14 26 ns 3 t w(rx_clkl) pulse duration, miin_rxclk low 10 mbps 140 260 ns 100 mbps 14 26 ns 265 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-93. timing requirements for miin_rxclk - mii operation (continued) no. parameter description speed min max unit 4 t t(rx_clk) transition time, miin_rxclk 10 mbps 3 ns 100 mbps 3 ns figure 5-68. clock timing (gmac receive) - miin operation table 5-94 and figure 5-69 present timing requirements for miin in transmit operation. table 5-94. timing requirements for miin_txclk - mii operation no. parameter description speed min max unit 1 t c(tx_clk) cycle time, miin_txclk 10 mbps 400 ns 100 mbps 40 ns 2 t w(tx_clkh) pulse duration, miin_txclk high 10 mbps 140 260 ns 100 mbps 14 26 ns 3 t w(tx_clkl) pulse duration, miin_txclk low 10 mbps 140 260 ns 100 mbps 14 26 ns 4 t t(tx_clk) transition time, miin_txclk 10 mbps 3 ns 100 mbps 3 ns figure 5-69. clock timing (gmac transmit) - miin operation table 5-95 and figure 5-70 present timing requirements for gmac miin receive 10/100mbit/s. table 5-95. timing requirements for gmac miin receive 10/100 mbit/s no. parameter description min max unit 1 t su(rxd-rx_clk) setup time, receive selected signals valid before miin_rxclk 8 ns t su(rx_dv-rx_clk) t su(rx_er-rx_clk) 2 t h(rx_clk-rxd) hold time, receive selected signals valid after miin_rxclk 8 ns t h(rx_clk-rx_dv) t h(rx_clk-rx_er) mii _rxclk n 2 3 1 4 4 sprs906_timing_gmac_miirxclk_01 mii _txclk n 2 3 1 4 4 sprs906_timing_gmac_miitxclk_02 266 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-70. gmac receive interface timing miin operation table 5-96 and figure 5-71 present timing requirements for gmac miin transmit 10/100mbit/s. table 5-96. switching characteristics over recommended operating conditions for gmac miin transmit 10/100 mbits/s no. parameter description min max unit 1 t d(tx_clk-txd) delay time, miin_txclk to transmit selected signals valid 0 25 ns t d(tx_clk-tx_en) figure 5-71. gmac transmit interface timing miin operation in table 5-97 are presented the specific groupings of signals (ioset) for use with gmac mii signals. table 5-97. gmac mii iosets signals ioset5 ioset6 ball mux ball mux gmac mii1 mii1_txd3 e11 8 mii1_txd2 a13 8 mii1_txd1 a12 8 mii1_txd0 b12 8 mii1_rxd3 b10 8 mii1_rxd2 a10 8 mii1_rxd1 f10 8 mii1_rxd0 e10 8 mii1_col e13 8 mii1_rxer b13 8 mii1_txer f11 8 mii1_txen d13 8 mii1_crs c13 8 mii1_rxclk b11 8 mii1_txclk c11 8 mii1_rxdv d11 8 gmac mii0 mii _rxclk n (input) 1 2 mii _rxd3 n mii _rxdv miin_rxer ? , (inputs) mii _rxd0, n n sprs906_timing_gmac_miircv_03 1 mii _txclk n (input) miin_txd3 miin_txen ? , (outputs) miin_txd0 sprs906_timing_gmac_miitx_04 267 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-97. gmac mii iosets (continued) signals ioset5 ioset6 ball mux ball mux mii0_txd3 p2 3 mii0_txd2 n1 3 mii0_txd1 n3 3 mii0_txd0 n4 3 mii0_rxd3 t4 3 mii0_rxd2 t5 3 mii0_rxd1 r2 3 mii0_rxd0 r1 3 mii0_txclk n2 3 mii0_txer l6 3 mii0_rxer p3 3 mii0_rxdv n5 3 mii0_crs p4 3 mii0_col l5 3 mii0_rxclk n6 3 mii0_txen p1 3 5.10.6.19.2 gmac mdio interface timings caution the i/o timings provided in this section are valid only for some gmac usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-98 , table 5-98 and figure 5-72 present timing requirements for mdio. table 5-98. timing requirements for mdio input no parameter description min max unit mdio1 t c(mdc) cycle time, mdc 400 ns mdio2 t w(mdch) pulse duration, mdc high 160 ns mdio3 t w(mdcl) pulse duration, mdc low 160 ns mdio4 t su(mdio-mdc) setup time, mdio valid before mdc high 90 ns mdio5 t h(mdio_mdc) hold time, mdio valid from mdc high 0 ns table 5-99. switching characteristics over recommended operating conditions for mdio output no parameter description min max unit mdio6 t t(mdc) transition time, mdc 5 ns mdio7 t d(mdc-mdio) delay time, mdc high to mdio valid 10 390 ns 268 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-72. gmac mdio diagrams in table 5-100 are presented the specific groupings of signals (ioset) for use with gmac mdio signals. table 5-100. gmac mdio iosets signals ioset7 ioset8 ioset9 ioset10 ball mux ball mux ball mux ball mux mdio_d c10 3 l6 0 y6 1 e25 5 mdio_mclk d10 3 l5 0 y5 1 e24 5 5.10.6.19.3 gmac rmii timings the main reference clock ref_clk (rmii_50mhz_clk) of rmii interface is internally supplied from prcm. the source of this clock could be either externally sourced from the rmii_mhz_50_clk pin of the device or internally generated from dpll_gmac output clock gmac_rmii_hs_clk. please see the prcm chapter of the device trm for full details about rmii reference clock. caution the i/o timings provided in this section are valid only for some gmac usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-101 , table 5-102 and figure 5-73 present timing requirements for gmac rmiin receive. table 5-101. timing requirements for gmac ref_clk - rmii operation no. parameter description min max unit rmii1 t c(ref_clk) cycle time, ref_clk 20 ns rmii2 t w(ref_clkh) pulse duration, ref_clk high 7 13 ns rmii3 t w(ref_clkl) pulse duration, ref_clk low 7 13 ns rmii4 t tt(ref_clk) transistion time, ref_clk 3 ns 1 mdio4 mdio5 mdio7 mdio2 mdio3 mdio6 mdio6 mdclk mdio (input) mdio (output) sprs906_timing_gmac_mdio_05 269 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-102. timing requirements for gmac rmiin receive no. parameter description min max unit rmii5 t su(rxd-ref_clk) setup time, receive selected signals valid before ref_clk 4 ns t su(crs_dv-ref_clk) t su(rx_er-ref_clk) rmii6 t h(ref_clk-rxd) hold time, receive selected signals valid after ref_clk 2 ns t h(ref_clk-crs_dv) t h(ref_clk-rx_er) figure 5-73. gmac receive interface timing rmiin operation table 5-103 , table 5-103 and figure 5-74 present switching characteristics for gmac rmiin transmit 10/100mbit/s. table 5-103. switching characteristics over recommended operating conditions for gmac ref_clk - rmii operation no. parameter description min max unit rmii7 t c(ref_clk) cycle time, ref_clk 20 ns rmii8 t w(ref_clkh) pulse duration, ref_clk high 7 13 ns rmii9 t w(ref_clkl) pulse duration, ref_clk low 7 13 ns rmii10 t t(ref_clk) transistion time, ref_clk 3 ns table 5-104. switching characteristics over recommended operating conditions for gmac rmiin transmit 10/100 mbits/s no. parameter description rmiin min max unit rmii11 t d(ref_clk-txd) delay time, ref_clk high to selected transmit signals valid rmii0 2 13.5 ns t dd(ref_clk-txen) t d(ref_clk-txd) rmii1 2 13.8 ns t dd(ref_clk-txen) figure 5-74. gmac transmit interface timing rmiin operation ref_clk (prcm) rmiin_txd1?rmiin_txd0, rmiin_txen (outputs) sprs906_timing_gmac_rmiitx_07 rmii7 rmii8 rmii9 rmii11 rmii10 ref_clk (prcm) rmii5 rmii6 rmiin_rxd1? rmin_rxer rmiin_rxd0, rmiin_crs, (inputs) sprs906_timing_gmac_rgmiitx_09 rmii1 rmii3 rmii2 rmii4 270 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated in table 5-105 are presented the specific groupings of signals (ioset) for use with gmac rmii signals. table 5-105. gmac rmii iosets signals ioset1 ioset2 ball mux ball mux gmac rmii1 rmii_mhz_50_clk p5 0 rmii1_txd1 p2 2 rmii1_txd0 n1 2 rmii1_rxd1 t4 2 rmii1_rxd0 t5 2 rmii1_rxer n6 2 rmii1_txen n2 2 rmii1_crs n5 2 gmac rmii0 rmii_mhz_50_clk p5 0 rmii0_txd1 n3 1 rmii0_txd0 n4 1 rmii0_rxd1 r2 1 rmii0_rxd0 r1 1 rmii0_txen p1 1 rmii0_rxer p3 1 rmii0_crs p4 1 manual io timings modes must be used to guaranteed some io timings for gmac. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-106 manual functions mapping for gmac rmii0 for a definition of the manual modes. table 5-106 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-106. manual functions mapping for gmac rmii0 ball ball name gmac_rmii0_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 0 1 p5 rmii_mhz_50_clk 0 0 cfg_rmii_mhz_50_clk_in rmii_mhz_50_clk r1 rgmii0_txd0 2444 804 cfg_rgmii0_txd0_in rmii0_rxd0 r2 rgmii0_txd1 2453 981 cfg_rgmii0_txd1_in rmii0_rxd1 p3 rgmii0_txd2 2356 847 cfg_rgmii0_txd2_in rmii0_rxer p4 rgmii0_txd3 2415 993 cfg_rgmii0_txd3_in rmii0_crs manual io timings modes must be used to guaranteed some io timings for gmac. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-107 manual functions mapping for gmac rmii1 for a definition of the manual modes. table 5-107 list the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. 271 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-107. manual functions mapping for gmac rmii1 ball ball name gmac_rmii1_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 0 2 p5 rmii_mhz_50_clk 0 0 cfg_rmii_mhz_50_clk_in rmii_mhz_50_clk t5 rgmii0_txctl 2450 909 cfg_rgmii0_txctl_in rmii1_rxd0 t4 rgmii0_txc 2327 926 cfg_rgmii0_txc_in rmii1_rxd1 n6 uart3_txd 2553 443 cfg_uart3_txd_in rmii1_rxer n5 uart3_rxd 1943 1110 cfg_uart3_rxd_in rmii1_crs 5.10.6.19.4 gmac rgmii timings caution the i/o timings provided in this section are valid only for some gmac usage modes when the corresponding virtual i/o timings or manual i/o timings are configured as described in the tables found in this section. table 5-108 , table 5-109 and figure 5-75 present timing requirements for receive rgmiin operation. table 5-108. timing requirements for rgmiin_rxc - rgmiin operation no. parameter description speed min max unit 1 t c(rxc) cycle time, rgmiin_rxc 10 mbps 360 440 ns 100 mbps 36 44 ns 1000 mbps 7.2 8.8 ns 2 t w(rxch) pulse duration, rgmiin_rxc high 10 mbps 160 240 ns 100 mbps 16 24 ns 1000 mbps 3.6 4.4 ns 3 t w(rxcl) pulse duration, rgmiin_rxc low 10 mbps 160 240 ns 100 mbps 16 24 ns 1000 mbps 3.6 4.4 ns 4 t t(rxc) transition time, rgmiin_rxc 10 mbps 0.75 ns 100 mbps 0.75 ns 1000 mbps 0.75 ns table 5-109. timing requirements for gmac rgmiin input receive for 10/100/1000 mbps (1) no. parameter description mode min max unit 5 t su(rxd-rxch) setup time, receive selected signals valid before rgmiin_rxc high/low rgmii0/1 1 ns 6 t h(rxch-rxd) hold time, receive selected signals valid after rgmiin_rxc high/low rgmii0/1 1 ns 272 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) for rgmii, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl. a. rgmiin_rxc must be externally delayed relative to the data and control pins. b. data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. similarly, rgmiin_rxctl carries rxdv on rising edge of rgmiin_rxc and rxerr on falling edge of rgmiin_rxc. figure 5-75. gmac receive interface timing, rgmiin operation table 5-110 , table 5-111 and figure 5-76 present switching characteristics for transmit - rgmiin for 10/100/1000mbit/s. table 5-110. switching characteristics over recommended operating conditions for rgmiin_txctl - rgmiin operation for 10/100/1000 mbit/s no. parameter description speed min max unit 1 t c(txc) cycle time, rgmiin_txc 10 mbps 360 440 ns 100 mbps 36 44 ns 1000 mbps 7.2 8.8 ns 2 t w(txch) pulse duration, rgmiin_txc high 10 mbps 160 240 ns 100 mbps 16 24 ns 1000 mbps 3.6 4.4 ns 3 t w(txcl) pulse duration, rgmiin_txc low 10 mbps 160 240 ns 100 mbps 16 24 ns 1000 mbps 3.6 4.4 ns 4 t t(txc) transition time, rgmiin_txc 10 mbps 0.75 ns 100 mbps 0.75 ns 1000 mbps 0.75 ns table 5-111. switching characteristics for gmac rgmiin output transmit for 10/100/1000 mbps (1) no. parameter description mode min max unit 5 t osu(txd-txc) output setup time, transmit selected signals valid to rgmiin_txc high/low rgmii0, internal delay enabled, 1000 mbps 1.05 (2) ns rgmii0, internal delay enabled, 10/100 mbps 1.2 ns rgmii1, internal delay enabled, 1000 mbps 1.05 (3) ns rgmii1, internal delay enabled, 10/100 mbps 1.2 ns rgmii _rxd[3:0] n (b) rgmii _rxctl n (b) rgmii _rxc n (a) 5 rxerr rxdv 1st half-byte 2nd half-byte rgrxd[7:4] rgrxd[3:0] 2 3 1 4 4 6 sprs906_timing_gmac_rgmiirx_08 273 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-111. switching characteristics for gmac rgmiin output transmit for 10/100/1000 mbps (1) (continued) no. parameter description mode min max unit 6 t oh(txc-txd) output hold time, transmit selected signals valid after rgmiin_txc high/low rgmii0, internal delay enabled, 1000 mbps 1.05 (2) ns rgmii0, internal delay enabled, 10/100 mbps 1.2 ns rgmii1, internal delay enabled, 1000 mbps 1.05 (3) ns rgmii1, internal delay enabled, 10/100 mbps 1.2 ns (1) for rgmii, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl. (2) rgmii0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50ps of rgmii0_txc. (3) rgmii1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50ps of rgmii1_txc. a. txc is delayed internally before being driven to the rgmiin_txc pin. this internal delay is always enabled. b. data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. similarly, rgmiin_txctl carries txen on rising edge of rgmiin_txc and txerr of falling edge of rgmiin_txc. figure 5-76. gmac transmit interface timing rgmiin operation in table 5-112 are presented the specific groupings of signals (ioset) for use with gmac rgmii signals. table 5-112. gmac rgmii iosets signals ioset3 ioset4 ball mux ball mux gmac rgmii1 rgmii1_txd3 c11 3 rgmii1_txd2 b12 3 rgmii1_txd1 a12 3 rgmii1_txd0 a13 3 rgmii1_rxd3 b13 3 rgmii1_rxd2 e13 3 rgmii1_rxd1 c13 3 rgmii1_rxd0 d13 3 rgmii1_rxctl f11 3 rgmii1_txc b11 3 rgmii1_txctl d11 3 rgmii _txc n (a) rgmii _txd n [3:0] (b) rgmii _txctl n (b) 5 1st half-byte txerr txen 2nd half-byte 4 4 2 3 1 6 [internal delay enabled] sprs906_timing_gmac_rgmiitx_09 274 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-112. gmac rgmii iosets (continued) signals ioset3 ioset4 ball mux ball mux rgmii1_rxc e11 3 gmac rgmii0 rgmii0_txd3 p4 0 rgmii0_txd2 p3 0 rgmii0_txd1 r2 0 rgmii0_txd0 r1 0 rgmii0_rxd3 n1 0 rgmii0_rxd2 p1 0 rgmii0_rxd1 n3 0 rgmii0_rxd0 n4 0 rgmii0_txc t4 0 rgmii0_rxctl p2 0 rgmii0_rxc n2 0 rgmii0_txctl t5 0 note to configure the desired manual io timing mode the user must follow the steps described in section " manual io timing modes " of the device trm. the associated registers to configure are listed in the cfg register column. for more information please see the control module chapter in the device trm. copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 275 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 manual io timings modes must be used to guaranteed some io timings for gmac. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-113 manual functions mapping for gmac rgmii0 for a definition of the manual modes. table 5-113 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-113. manual functions mapping for gmac rgmii0 ball ball name gmac_rgmii0_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 0 n2 rgmii0_rxc 413 0 cfg_rgmii0_rxc_in rgmii0_rxc p2 rgmii0_rxctl 27 2296 cfg_rgmii0_rxctl_in rgmii0_rxctl n4 rgmii0_rxd0 3 1721 cfg_rgmii0_rxd0_in rgmii0_rxd0 n3 rgmii0_rxd1 134 1786 cfg_rgmii0_rxd1_in rgmii0_rxd1 p1 rgmii0_rxd2 40 1966 cfg_rgmii0_rxd2_in rgmii0_rxd2 n1 rgmii0_rxd3 0 2057 cfg_rgmii0_rxd3_in rgmii0_rxd3 t4 rgmii0_txc 0 60 cfg_rgmii0_txc_out rgmii0_txc t5 rgmii0_txctl 0 60 cfg_rgmii0_txctl_out rgmii0_txctl r1 rgmii0_txd0 0 60 cfg_rgmii0_txd0_out rgmii0_txd0 r2 rgmii0_txd1 0 0 cfg_rgmii0_txd1_out rgmii0_txd1 p3 rgmii0_txd2 0 60 cfg_rgmii0_txd2_out rgmii0_txd2 p4 rgmii0_txd3 0 120 cfg_rgmii0_txd3_out rgmii0_txd3 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 276 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com manual io timings modes must be used to guaranteed some io timings for gmac. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-114 manual functions mapping for gmac rgmii1 for a definition of the manual modes. table 5-114 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-114. manual functions mapping for gmac rgmii1 ball ball name gmac_rgmii1_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 3 e11 vin2a_d18 530 0 cfg_vin2a_d18_in rgmii1_rxc f11 vin2a_d19 71 1099 cfg_vin2a_d19_in rgmii1_rxctl b13 vin2a_d20 142 1337 cfg_vin2a_d20_in rgmii1_rxd3 e13 vin2a_d21 114 1517 cfg_vin2a_d21_in rgmii1_rxd2 c13 vin2a_d22 171 1331 cfg_vin2a_d22_in rgmii1_rxd1 d13 vin2a_d23 0 1328 cfg_vin2a_d23_in rgmii1_rxd0 b11 vin2a_d12 0 0 cfg_vin2a_d12_out rgmii1_txc d11 vin2a_d13 170 0 cfg_vin2a_d13_out rgmii1_txctl c11 vin2a_d14 150 0 cfg_vin2a_d14_out rgmii1_txd3 b12 vin2a_d15 0 0 cfg_vin2a_d15_out rgmii1_txd2 a12 vin2a_d16 60 0 cfg_vin2a_d16_out rgmii1_txd1 a13 vin2a_d17 60 0 cfg_vin2a_d17_out rgmii1_txd0 277 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.20 mlb the mlbss allows connection to a most (media oriented systems transport) network controller for transport of media and control data between multimedia nodes. the mlbss supports the following features: ? 3 pin mode compliant to medialb physical layer specification v4.0 ? 6 pin mode (3 differential pairs) compliant to medialb physical layer specification v4.0 ? supports 256/512/1024fs in 3 pin mode and 2048fs in 6 pin mode ? supports all types of transfer (sync, isoc, async/packet, control) over 64 logical channels ? 16kb buffering for synchronous /isochronous/control/packet data in the subsystem note for more information, see the media local bus (mlb) section of the device trm. note mlb in 6-pin mode may require pull ups/ downs on sig and dat bus signals. for additional details, please consult the mlb bus interface specification. table 5-115 and figure 5-77 present timing requirements for mlkclk 3-pin option. table 5-115. timing requirements for mlbclk 3-pin option (1) no. parameter description mode min max unit 1 t c(mlbclk) cycle time, mlb_clk 512fs 39 ns 1024fs 19.5 ns 2 t w(mlbclk) pulse duration, mlb_clk high 512fs 14 ns 1024fs 9.3 ns 3 t w(mlbclk) pulse duration, mlb_clk low 512fs 14 ns 1024fs 6.1 ns (1) the reference points for the rise and fall transitions are measured at v ol max and v oh min. figure 5-77. mlb_clk timing table 5-116 and table 5-117 present timing requirements and switching characteristics for mlb 3-pin option. table 5-116. timing requirements for receive data for the mlb 3-pin option no. parameter description mode min max unit 5 t su(mlbdat-mlbclkl) setup time, mlb_dat/mlb_sig input valid before mlb_clk low 512fs 1 ns 1024fs 1 ns 6 t h(mlbclkl-mlbdat) hold time, mlb_dat/mlb_sig input valid after mlb_clk low 512fs 4 ns 1024fs 2 ns mlb_clk 1 2 4 4 3 sprs906_timing_mlb_01 278 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-117. switching characteristics over recommended operating conditions for mlb 3-pin option no. parameter description mode min max unit 7 t d(mlbclkh-mlbdatv) delay time, mlbclkh rising to mlb_dat/mlb_sig valid 512fs 0 10 ns 1024fs 0 7 ns 8 t dis(mlbclkl- mlbdatz) disable time, mlbclkh falling to mlb_dat/mlb_sig hi-z 512fs 0 14 ns 1024fs 0 6.1 ns table 5-118 and figure 5-77 present timing requirements for mlkclk 6-pin option. table 5-118. timing requirements for mlbclk 6-pin option (1) no. parameter description mode min max unit 1 t c(mlbclkx) cycle time, mlb_clkp/n 2048fs, 4096fs 10 ns 2 t w(mlbclkx) pulse duration, mlb_clkp/n high 2048fs, 4096fs 4.5 ns 3 t w(mlbclkx) pulse duration, mlb_clkp/n low 2048fs, 4096fs 4.5 ns (1) the reference points for the rise and fall transitions are measured at 20%/80% of vin+/-. table 5-119 and table 5-120 present timing requirements and switching characteristics for mlb 6-pin option. table 5-119. timing requirements for receive data for the mlb 6-pin option no. parameter description mode min max unit 5 t su(datx-clkxh) setup time, mlbp_datx/mlbp_sigx input valid before mlbp_clkx rising 2048fs 1 ns 4096fs 0.5 - n p/2 (1) (2) ns 6 t h(clkxh-datx) hold time, mlbp_datx/mlbp_sigx input valid after mlbp_clkx rising 2048fs 0.5 ns 4096fs 0.6 + n p/2 (1) (2) ns (1) p= tc(mlbclkx) period. (2) n=0 or 1, corresponding to two captures per clock cycle. table 5-120. switching characteristics over recommended operating conditions for mlb 6-pin option no. parameter description mode min max unit 7 t d(clkxh-datxv) delay time, mlbpclkxh rising to mlb_datx/mlb_sigx valid 2048fs 0.5 7 ns 4096fs 0.6 + n p/2 (1) (2) 2.5 + n p/2 ns 8 t dis(clkph-datpz) disable time, mlbpclkxh rising to mlbp_datx/mlbp_sigx hi-z 2048fs 0.5 7 ns 4096fs 0.6 + n p/2 (1) (2) 3.5 + n p/2 ns (1) p= tc(mlbclkx) period. (2) n=0 or 1, corresponding to two captures per clock cycle. in are presented the specific groupings of signals (ioset) for use with mlb signals. 5.10.6.21 emmc/sd/sdio the device includes the following external memory interfaces 4 multimedia card/secure digital/secure digital input output interface (mmc/sd/sdio) note the emmc/sd/sdioi (i = 1 to 4) controller is also referred to as mmci. 279 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.21.1 mmc1 ? sd card interface mmc1 interface is compliant with the sd standard v3.01 and it supports the following sd card applications: ? default speed, 4-bit data, sdr, half-cycle ? high speed, 4-bit data, sdr, half-cycle ? sdr12, 4-bit data, half-cycle ? sdr25, 4-bit data, half-cycle ? uhs-i sdr50, 4-bit data, half-cycle ? uhs-i sdr104, 4-bit data, half-cycle ? uhs-i ddr50, 4-bit data note for more information, see the emmc/sd/sdio chapter of the device trm. 5.10.6.21.1.1 default speed, 4-bit data, sdr, half-cycle table 5-121 and table 5-122 present timing requirements and switching characteristics for mmc1 - default speed in receiver and transmitter mode (see figure 5-78 and figure 5-79 ). table 5-121. timing requirements for mmc1 - sd card default speed mode no. parameter description min max unit dssd5 t su(cmdv-clkh) setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.11 ns dssd6 t h(clkh-cmdv) hold time, mmc1_cmd valid after mmc1_clk rising clock edge 20.46 ns dssd7 t su(dv-clkh) setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.11 ns dssd8 t h(clkh-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 20.46 ns table 5-122. switching characteristics for mmc1 - sd card default speed mode no. parameter description min max unit dssd0 fop(clk) operating frequency, mmc1_clk 24 mhz dssd1 t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns dssd2 t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns dssd3 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -14.93 14.93 ns dssd4 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -14.93 14.93 ns 280 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = output mmc1_clk period in ns figure 5-78. mmc/sd/sdio in - default speed - receiver mode figure 5-79. mmc/sd/sdio in - default speed - transmitter mode 5.10.6.21.1.2 high speed, 4-bit data, sdr, half-cycle table 5-123 and table 5-124 present timing requirements and switching characteristics for mmc1 - high speed in receiver and transmitter mode (see figure 5-80 and figure 5-81 ). table 5-123. timing requirements for mmc1 - sd card high speed no. parameter description min max unit hssd3 t su(cmdv-clkh) setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.3 ns hssd4 t h(clkh-cmdv) hold time, mmc1_cmd valid after mmc1_clk rising clock edge 2.6 ns hssd7 t su(dv-clkh) setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.3 ns hssd8 t h(clkh-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 2.6 ns table 5-124. switching characteristics for mmc1 - sd card high speed no. parameter description min max unit hssd1 fop(clk) operating frequency, mmc1_clk 48 mhz hssd2h t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns hssd2l t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns hssd5 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -7.6 3.6 ns hssd6 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -7.6 3.6 ns dssd2 dssd1 dssd0 dssd6 dssd5 dssd8 dssd7 mmc1_clk mmc1_cmd mmc1_dat[3:0] sprs906_timing_mmc1_01 dssd2 dssd1 dssd0 dssd3 dssd4 mmc1_clk mmc1_cmd mmc1_dat[3:0] sprs906_timing_mmc1_02 281 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = output mmc1_clk period in ns figure 5-80. mmc/sd/sdio in - high speed - receiver mode figure 5-81. mmc/sd/sdio in - high speed - transmitter mode 5.10.6.21.1.3 sdr12, 4-bit data, half-cycle table 5-125 and table 5-126 present timing requirements and switching characteristics for mmc1 - sdr12 in receiver and transmitter mode (see figure 5-82 and figure 5-83 ). table 5-125. timing requirements for mmc1 - sd card sdr12 mode no. parameter description mode min max unit sdr12 5 t su(cmdv-clkh) setup time, mmc1_cmd valid before mmc1_clk rising clock edge 25.99 ns sdr12 6 t h(clkh-cmdv) hold time, mmc1_cmd valid after mmc1_clk rising clock edge pad loopback clock 1.6 ns internal loopback clock 1.6 ns sdr12 7 t su(dv-clkh) setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 25.99 ns sdr12 8 t h(clkh-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge pad loopback clock 1.6 ns internal loopback clock 1.6 ns table 5-126. switching characteristics for mmc1 - sd card sdr12 mode no. parameter description min max unit sdr120 fop(clk) operating frequency, mmc1_clk 24 mhz sdr121 t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns sdr122 t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns sdr123 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -19.13 16.93 ns sdr124 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -19.13 16.93 ns mmc1_clk mmc1_cmd mmc1_dat[3:0] hssd1 hssd2l hssd2h hssd3 hssd4 hssd7 hssd8 sprs906_timing_mmc1_03 mmc1_clk mmc1_cmd mmc1_dat[3:0] hssd1 hssd2l hssd2h hssd5 hssd6 hssd5 hssd6 sprs906_timing_mmc1_04 282 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = output mmc1_clk period in ns figure 5-82. mmc/sd/sdio in - high speed sdr12 - receiver mode figure 5-83. mmc/sd/sdio in - high speed sdr12 - transmitter mode 5.10.6.21.1.4 sdr25, 4-bit data, half-cycle table 5-127 and table 5-128 present timing requirements and switching characteristics for mmc1 - sdr25 in receiver and transmitter mode (see figure 5-84 and figure 5-85 ). table 5-127. timing requirements for mmc1 - sd card sdr25 mode no. parameter description mode min max unit sdr25 3 t su(cmdv-clkh) setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.3 ns sdr25 4 t h(clkh-cmdv) hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.6 ns sdr25 7 t su(dv-clkh) setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.3 ns sdr25 8 t h(clkh-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge pad loopback clock 1.6 ns internal loopback clock 1.6 ns table 5-128. switching characteristics for mmc1 - sd card sdr25 mode no. parameter description min max unit sdr251 fop(clk) operating frequency, mmc1_clk 48 mhz sdr252 h t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns sdr252l t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns sdr255 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -8.8 6.6 ns sdr122 sdr121 sdr120 sdr126 sdr125 sdr128 sdr127 mmc1_clk mmc1_cmd mmc1_dat[3:0] sprs906_timing_mmc1_05 sdr122 sdr121 sdr120 sdr123 sdr124 mmc1_clk mmc1_cmd mmc1_dat[3:0] sprs906_timing_mmc1_06 283 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-128. switching characteristics for mmc1 - sd card sdr25 mode (continued) no. parameter description min max unit sdr256 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -8.8 6.6 ns (1) p = output mmc1_clk period in ns figure 5-84. mmc/sd/sdio in - high speed sdr25 - receiver mode figure 5-85. mmc/sd/sdio in - high speed sdr25 - transmitter mode 5.10.6.21.1.5 uhs-i sdr50, 4-bit data, half-cycle table 5-129 and table 5-130 present timing requirements and switching characteristics for mmc1 - sdr50 in receiver and transmitter mode (see figure 5-86 and figure 5-87 ). table 5-129. timing requirements for mmc1 - sd card sdr50 mode no. parameter description mode min max unit sdr50 3 t su(cmdv-clkh) setup time, mmc1_cmd valid before mmc1_clk rising clock edge 1.48 ns sdr50 4 t h(clkh-cmdv) hold time, mmc1_cmd valid after mmc1_clk rising clock edge 1.7 ns sdr50 7 t su(dv-clkh) setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 1.48 ns sdr50 8 t h(clkh-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge pad loopback clock 1.7 ns internal loopback clock 1.6 ns table 5-130. switching characteristics for mmc1 - sd card sdr50 mode no. parameter description min max unit sdr501 fop(clk) operating frequency, mmc1_clk 96 mhz sdr502 h t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns sdr502l t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns sdr505 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -8.8 6.6 ns sdr506 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -3.66 1.46 ns mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr251 sdr252l sdr252h hssdr255 sdr256 sdr255 sdr256 sprs906_timing_mmc1_08 mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr254 sdr258 sdr253 sdr257 sdr251 sdr252h sdr252l sprs906_timing_mmc1_07 284 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) p = output mmc1_clk period in ns figure 5-86. mmc/sd/sdio in - high speed sdr50 - receiver mode figure 5-87. mmc/sd/sdio in - high speed sdr50 - transmitter mode 5.10.6.21.1.6 uhs-i sdr104, 4-bit data, half-cycle table 5-131 presents timing requirements and switching characteristics for mmc1 - sdr104 in receiver and transmitter mode (see figure 5-88 and figure 5-89 ). table 5-131. switching characteristics for mmc1 - sd card sdr104 mode no. parameter description min max unit sdr1041 fop(clk) operating frequency, mmc1_clk 192 mhz sdr1042 h t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns sdr1042 l t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns sdr1045 t d(clkl-cmdv) delay time, mmc1_clk falling clock edge to mmc1_cmd transition -1.09 0.49 ns sdr1046 t d(clkl-dv) delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -1.09 0.49 ns (1) p = output mmc1_clk period in ns figure 5-88. mmc/sd/sdio in - high speed sdr104 - receiver mode mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr504 sdr508 sdr503 sdr507 sdr501 sdr502h sdr502l sprs906_timing_mmc1_09 mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr501 sdr502l sdr502h sdr505 sdr506 sdr505 sdr506 sprs906_timing_mmc1_10 mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr1044 sdr1048 sdr1043 sdr1047 sdr1041 sdr1042h sdr1042l sprs906_timing_mmc1_11 285 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-89. mmc/sd/sdio in - high speed sdr104 - transmitter mode 5.10.6.21.1.7 uhs-i ddr50, 4-bit data table 5-132 and table 5-133 present timing requirements and switching characteristics for mmc1 - ddr50 in receiver and transmitter mode (see figure 5-90 and figure 5-91 ). table 5-132. timing requirements for mmc1 - sd card ddr50 mode no. parame ter description mode min max unit ddr50 5 t su(cmdv-clk) setup time, mmc1_cmd valid before mmc1_clk transition 1.79 ns ddr50 6 t h(clk-cmdv) hold time, mmc1_cmd valid after mmc1_clk transition 2 ns ddr50 7 t su(dv-clk) setup time, mmc1_dat[3:0] valid before mmc1_clk transition pad loopback 1.79 ns internal loopback 1.79 ns ddr50 8 t h(clk-dv) hold time, mmc1_dat[3:0] valid after mmc1_clk transition pad loopback 2 ns internal loopback 1.6 ns table 5-133. switching characteristics for mmc1 - sd card ddr50 mode no. parameter description min max unit ddr500 fop(clk) operating frequency, mmc1_clk 48 mhz ddr501 t w(clkh) pulse duration, mmc1_clk high 0.5 p- 0.185 (1) ns ddr502 t w(clkl) pulse duration, mmc1_clk low 0.5 p- 0.185 (1) ns ddr503 t d(clk-cmdv) delay time, mmc1_clk transition to mmc1_cmd transition 1.225 6.6 ns ddr504 t d(clk-dv) delay time, mmc1_clk transition to mmc1_dat[3:0] transition 1.225 6.6 ns (1) p = output mmc1_clk period in ns figure 5-90. sdmmc - high speed sd - ddr - data/command receive mmc1_clk mmc1_cmd mmc1_dat[3:0] sdr1041 sdr1042l sdr1042h sdr1045 sdr1046 sdr1045 sdr1046 sprs906_timing_mmc1_12 mmc _clk 1 mmc _cmd 1 mmc _dat[3:0] 1 ddr500 ddr501 ddr502 ddr505 ddr506 ddr508 ddr507 ddr507 ddr508 sprs906_timing_mmc1_13 286 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-91. sdmmc - high speed sd - ddr - data/command transmit note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . virtual io timings modes must be used to guaranteed some io timings for mmc1. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-134 virtual functions mapping for mmc1 for a definition of the virtual modes. table 5-134 presents the values for delaymode bitfield. table 5-134. virtual functions mapping for mmc1 ball ball name delay mode value muxmode mmc1_ virtual1 mmc1_ virtual4 mmc1_ virtual5 mmc1_ virtual6 0 u3 mmc1_clk 15 12 11 10 mmc1_clk v4 mmc1_cmd 15 12 11 10 mmc1_cmd v3 mmc1_dat0 15 12 11 10 mmc1_dat0 v2 mmc1_dat1 15 12 11 10 mmc1_dat1 w1 mmc1_dat2 15 12 11 10 mmc1_dat2 v1 mmc1_dat3 15 12 11 10 mmc1_dat3 note to configure the desired manual io timing mode the user must follow the steps described in section manual io timing modes of the device trm. the associated registers to configure are listed in the cfg register column. for more information see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for mmc1. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-135 manual functions mapping for mmc1 for a definition of the manual modes. table 5-135 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. mmc _clk 1 mmc _cmd 1 mmc _dat[3:0] 1 ddr500 ddr501 ddr502 ddr503(max) ddr503(min) ddr504(max) ddr504(min) ddr504(min) ddr504(max) mmc1_14 copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 287 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 table 5-135. manual functions mapping for mmc1 ball ball name mmc1_manual1 mmc1_manual2 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 0 u3 mmc1_clk 588 0 - - cfg_mmc1_clk_in mmc1_clk v4 mmc1_cmd 1000 0 - - cfg_mmc1_cmd_in mmc1_cmd v3 mmc1_dat0 1375 0 - - cfg_mmc1_dat0_in mmc1_dat0 v2 mmc1_dat1 1000 0 - - cfg_mmc1_dat1_in mmc1_dat1 w1 mmc1_dat2 1000 0 - - cfg_mmc1_dat2_in mmc1_dat2 v1 mmc1_dat3 1000 0 - - cfg_mmc1_dat3_in mmc1_dat3 u3 mmc1_clk 1230 0 520 320 cfg_mmc1_clk_out mmc1_clk v4 mmc1_cmd 0 0 0 0 cfg_mmc1_cmd_out mmc1_cmd v3 mmc1_dat0 56 0 40 0 cfg_mmc1_dat0_out mmc1_dat0 v2 mmc1_dat1 76 0 83 0 cfg_mmc1_dat1_out mmc1_dat1 w1 mmc1_dat2 91 0 98 0 cfg_mmc1_dat2_out mmc1_dat2 v1 mmc1_dat3 99 0 106 0 cfg_mmc1_dat3_out mmc1_dat3 v4 mmc1_cmd 0 0 51 0 cfg_mmc1_cmd_oen mmc1_cmd v3 mmc1_dat0 0 0 0 0 cfg_mmc1_dat0_oen mmc1_dat0 v2 mmc1_dat1 0 0 363 0 cfg_mmc1_dat1_oen mmc1_dat1 w1 mmc1_dat2 0 0 199 0 cfg_mmc1_dat2_oen mmc1_dat2 v1 mmc1_dat3 0 0 273 0 cfg_mmc1_dat3_oen mmc1_dat3 5.10.6.21.2 mmc2 ? emmc mmc2 interface is compliant with the jc64 emmc standard v4.5 and it supports the following emmc applications: ? standard jc64 sdr, 8-bit data, half cycle ? high-speed jc64 sdr, 8-bit data, half cycle ? high-speed hs200 jeds84, 8-bit data, half cycle ? high-speed jc64 ddr, 8-bit data note for more information, see the emmc/sd/sdio chapter of the device trm. copyright ? 2016 ? 2018, texas instruments incorporated specifications submit documentation feedback product folder links: dra71 288 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com 5.10.6.21.2.1 standard jc64 sdr, 8-bit data, half cycle table 5-136 and table 5-137 present timing requirements and switching characteristics for mmc2 - standart sdr in receiver and transmitter mode (see figure 5-92 and figure 5-93 ). table 5-136. timing requirements for mmc2 - jc64 standard sdr mode no. parameter description min max unit ssdr5 t su(cmdv-clkh) setup time, mmc2_cmd valid before mmc2_clk rising clock edge 13.19 ns ssdr6 t h(clkh-cmdv) hold time, mmc2_cmd valid after mmc2_clk rising clock edge 8.4 ns ssdr7 t su(dv-clkh) setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 13.19 ns ssdr8 t h(clkh-dv) hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 8.4 ns 289 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-137. switching characteristics for mmc2 - jc64 standard sdr mode no. parameter description min max unit ssdr1 fop(clk) operating frequency, mmc2_clk 24 mhz ssdr2h t w(clkh) pulse duration, mmc2_clk high 0.5 p- 0.172 (1) ns ssdr2l t w(clkl) pulse duration, mmc2_clk low 0.5 p- 0.172 (1) ns ssdr3 t d(clkl-cmdv) delay time, mmc2_clk falling clock edge to mmc2_cmd transition -16.96 16.96 ns ssdr4 t d(clkl-dv) delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -16.96 16.96 ns (1) p = output mmc2_clk period in ns figure 5-92. mmc/sd/sdio in - standard jc64 - receiver mode figure 5-93. mmc/sd/sdio in - standard jc64 - transmitter mode 5.10.6.21.2.2 high-speed jc64 sdr, 8-bit data, half cycle table 5-138 and table 5-139 present timing requirements and switching characteristics for mmc2 - high speed sdr in receiver and transmitter mode (see figure 5-94 and figure 5-95 ). table 5-138. timing requirements for mmc2 - jc64 high speed sdr mode no. parameter description min max unit jc643 t su(cmdv-clkh) setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 ns jc644 t h(clkh-cmdv) hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.6 ns jc647 t su(dv-clkh) setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 5.6 ns jc648 t h(clkh-dv) hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 2.6 ns ssdr2 mmc2_clk mmc2_cmd mmc2_dat[7:0] ssdr1 ssdr2 ssdr3 ssdr4 sprs906_timing_mmc2_02 mmc2_clk mmc2_cmd mmc2_dat[7:0] ssdr2 ssdr2 ssdr1 ssdr6 ssdr5 ssdr8 ssdr7 sprs906_timing_mmc2_01 290 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-139. switching characteristics for mmc2 - jc64 high speed sdr mode no. parameter description min max unit jc641 fop(clk) operating frequency, mmc2_clk 48 mhz jc642h t w(clkh) pulse duration, mmc2_clk high 0.5 p- 0.172 (1) ns jc642l t w(clkl) pulse duration, mmc2_clk low 0.5 p- 0.172 (1) ns jc645 t d(clkl-cmdv) delay time, mmc2_clk falling clock edge to mmc2_cmd transition -6.64 6.64 ns jc646 t d(clkl-dv) delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -6.64 6.64 ns (1) p = output mmc2_clk period in ns figure 5-94. mmc/sd/sdio in - high speed jc64 - receiver mode figure 5-95. mmc/sd/sdio in - high speed jc64 - transmitter mode 5.10.6.21.2.3 high-speed hs200 jeds84 sdr, 8-bit data, half cycle table 5-140 presents switching characteristics for mmc2 - hs200 in transmitter mode (see figure 5-96 ). mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] jc645 jc645 jc646 jc646 jc641 jc642h jc642l mmc2_04 mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] jc644 jc648 jc643 jc647 jc641 jc642h jc642l sprs906_timing_mmc2_03 291 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-140. switching characteristics for mmc2 - jeds84 hs200 mode no. parameter description min max unit hs2001 fop(clk) operating frequency, mmc2_clk 192 mhz hs2002h t w(clkh) pulse duration, mmc2_clk high 0.5 p- 0.172 (1) ns hs2002l t w(clkl) pulse duration, mmc2_clk low 0.5 p- 0.172 (1) ns hs2005 t d(clkl-cmdv) delay time, mmc2_clk falling clock edge to mmc2_cmd transition -1.136 0.536 ns hs2006 t d(clkl-dv) delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -1.136 0.536 ns (1) p = output mmc2_clk period in ns figure 5-96. emmc in - hs200 sdr - transmitter mode 5.10.6.21.2.4 high-speed jc64 ddr, 8-bit data table 5-141 and table 5-142 present timing requirements and switching characteristics for mmc2 - high speed ddr in receiver and transmitter mode (see figure 5-97 and figure 5-98 ). table 5-141. timing requirements for mmc2 - jc64 high speed ddr mode no. parameter description mode min max unit ddr3 t su(cmdv-clk) setup time, mmc2_cmd valid before mmc2_clk transition 1.8 ns ddr4 t h(clk-cmdv) hold time, mmc2_cmd valid after mmc2_clk transition 1.6 ns ddr7 t su(dv-clk) setup time, mmc2_dat[7:0] valid before mmc2_clk transition 1.8 ns ddr8 t h(clk-dv) hold time, mmc2_dat[7:0] valid after mmc2_clk transition pad loopback (1.8v and 3.3v), boot 1.6 ns internal loopback (1.8v with mmc2_virtual2) 1.86 ns internal loopback (3.3v with mmc2_virtual2) 1.95 ns internal loopback (1.8v with mmc2_manual2) ns internal loopback (3.3v with mmc2_manual2) 1.6 ns table 5-142. switching characteristics for mmc2 - jc64 high speed ddr mode no. parameter description min max unit ddr1 fop(clk) operating frequency, mmc2_clk 48 mhz ddr2h t w(clkh) pulse duration, mmc2_clk high 0.5 p- 0.172 (1) ns ddr2l t w(clkl) pulse duration, mmc2_clk low 0.5 p- 0.172 (1) ns mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] hs2005 hs2005 hs2006 hs2006 hs2001 hs2002l hs2002h mmc2_05 292 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-142. switching characteristics for mmc2 - jc64 high speed ddr mode (continued) no. parameter description min max unit ddr5 t d(clk-cmdv) delay time, mmc2_clk transition to mmc2_cmd transition 2.9 7.14 ns ddr6 t d(clk-dv) delay time, mmc2_clk transition to mmc2_dat[7:0] transition 2.9 7.14 ns (1) p = output mmc2_clk period in ns figure 5-97. mmc/sd/sdio in - high speed ddr jc64 - receiver mode figure 5-98. mmc/sd/sdio in - high speed ddr jc64 - transmitter mode note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . virtual io timings modes must be used to guaranteed some io timings for mmc2. see table 5-29 modes summary for a list of io timings requiring the use of virtual io timings modes. see table 5-143 virtual functions mapping for mmc2 for a definition of the virtual modes. table 5-143 presents the values for delaymode bitfield. table 5-143. virtual functions mapping for mmc2 ball ball name delay mode value muxmode mmc2_virtual2 1 a6 gpmc_cs1 13 mmc2_cmd a4 gpmc_a19 13 mmc2_dat4 mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] ddr1 ddr2h ddr2l ddr3 ddr4 ddr7 ddr8 ddr7 ddr8 ddr7 ddr8 ddr7 sprs906_timing_mmc2_07 mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] ddr1 ddr2 ddr2 ddr5 ddr5 ddr6 ddr6 ddremmc6 ddremmc6 ddr5 ddr5 ddr6 ddr6 sprs906_timing_mmc2_08 293 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-143. virtual functions mapping for mmc2 (continued) ball ball name delay mode value muxmode mmc2_virtual2 1 e7 gpmc_a20 13 mmc2_dat5 d6 gpmc_a21 13 mmc2_dat6 c5 gpmc_a22 13 mmc2_dat7 b5 gpmc_a23 13 mmc2_clk d7 gpmc_a24 13 mmc2_dat0 c6 gpmc_a25 13 mmc2_dat1 a5 gpmc_a26 13 mmc2_dat2 b6 gpmc_a27 13 mmc2_dat3 note to configure the desired manual io timing mode the user must follow the steps described in section manual io timing modes of the device trm. the associated registers to configure are listed in the cfg register column. for more information see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for mmc2. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-144 manual functions mapping for mmc2 for a definition of the manual modes. table 5-144 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-144. manual functions mapping for mmc2 bal l ball name mmc2_manual1 mmc2_manual2 mmc2_manual3 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 1 a4 gpmc_a19 0 0 0 14 - - cfg_gpmc_a19_in mmc2_dat4 e7 gpmc_a20 119 0 127 0 - - cfg_gpmc_a20_in mmc2_dat5 d6 gpmc_a21 0 0 22 0 - - cfg_gpmc_a21_in mmc2_dat6 c5 gpmc_a22 18 0 72 0 - - cfg_gpmc_a22_in mmc2_dat7 b5 gpmc_a23 894 0 410 4000 - - cfg_gpmc_a23_in mmc2_clk d7 gpmc_a24 30 0 82 0 - - cfg_gpmc_a24_in mmc2_dat0 c6 gpmc_a25 0 0 0 0 - - cfg_gpmc_a25_in mmc2_dat1 a5 gpmc_a26 23 0 77 0 - - cfg_gpmc_a26_in mmc2_dat2 b6 gpmc_a27 0 0 0 0 - - cfg_gpmc_a27_in mmc2_dat3 a6 gpmc_cs1 0 0 0 0 - - cfg_gpmc_cs1_in mmc2_cmd a4 gpmc_a19 152 0 152 0 285 0 cfg_gpmc_a19_out mmc2_dat4 e7 gpmc_a20 206 0 206 0 189 0 cfg_gpmc_a20_out mmc2_dat5 d6 gpmc_a21 78 0 78 0 0 120 cfg_gpmc_a21_out mmc2_dat6 c5 gpmc_a22 2 0 2 0 0 70 cfg_gpmc_a22_out mmc2_dat7 b5 gpmc_a23 266 0 266 0 730 360 cfg_gpmc_a23_out mmc2_clk d7 gpmc_a24 0 0 0 0 0 0 cfg_gpmc_a24_out mmc2_dat0 c6 gpmc_a25 0 0 0 0 0 0 cfg_gpmc_a25_out mmc2_dat1 a5 gpmc_a26 43 0 43 0 70 0 cfg_gpmc_a26_out mmc2_dat2 b6 gpmc_a27 0 0 0 0 0 0 cfg_gpmc_a27_out mmc2_dat3 a6 gpmc_cs1 0 0 0 0 0 120 cfg_gpmc_cs1_out mmc2_cmd a4 gpmc_a19 0 0 0 0 0 0 cfg_gpmc_a19_oen mmc2_dat4 294 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-144. manual functions mapping for mmc2 (continued) bal l ball name mmc2_manual1 mmc2_manual2 mmc2_manual3 cfg register muxmode a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) a_delay (ps) g_delay (ps) 1 e7 gpmc_a20 0 0 0 0 231 0 cfg_gpmc_a20_oen mmc2_dat5 d6 gpmc_a21 0 0 0 0 39 0 cfg_gpmc_a21_oen mmc2_dat6 c5 gpmc_a22 0 0 0 0 91 0 cfg_gpmc_a22_oen mmc2_dat7 d7 gpmc_a24 0 0 0 0 176 0 cfg_gpmc_a24_oen mmc2_dat0 c6 gpmc_a25 0 0 0 0 0 0 cfg_gpmc_a25_oen mmc2_dat1 a5 gpmc_a26 0 0 0 0 101 0 cfg_gpmc_a26_oen mmc2_dat2 b6 gpmc_a27 0 0 0 0 0 0 cfg_gpmc_a27_oen mmc2_dat3 a6 gpmc_cs1 0 0 0 0 360 0 cfg_gpmc_cs1_oe n mmc2_cmd 5.10.6.21.3 mmc3 and mmc4 ? sdio/sd mmc3 and mmc4 interfaces are compliant with the sdio3.0 standard v1.0, sd part e1 and for generic sdio devices, it supports the following applications: ? mmc3 8-bit data and mmc4 4-bit data, sd default speed, sdr ? mmc3 8-bit data and mmc4 4-bit data, sd high speed, sdr ? mmc3 8-bit data and mmc4 4-bit data, uhs-1 sdr12 (sd standard v3.01), 4-bit data, sdr, half cycle ? mmc3 8-bit data and mmc4 4-bit data, uhs-i sdr25 (sd standard v3.01), 4-bit data, sdr, half cycle ? mmc3 8-bit data, uhs-i sdr50 note the emmc/sd/sdioj (j = 3 to 4) controller is also referred to as mmcj. note for more information, see the mmc/sdio chapter of the device trm. 5.10.6.21.3.1 mmc3 and mmc4, sd default speed figure 5-99 , figure 5-100 , and table 5-145 through table 5-148 present timing requirements and switching characteristics for mmc3 and mmc4 - sd default speed in receiver and transmitter mode. table 5-145. timing requirements for mmc3 - default speed mode (1) no. parameter description min max unit ds5 t su(cmdv-clkh) setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.11 ns ds6 t h(clkh-cmdv) hold time, mmc3_cmd valid after mmc3_clk rising clock edge 20.46 ns ds7 t su(dv-clkh) setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.11 ns ds8 t h(clkh-dv) hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 20.46 ns (1) i in [i:0] = 7 table 5-146. switching characteristics for mmc3 - sd/sdio default speed mode (2) no. parameter description min max unit ds0 fop(clk) operating frequency, mmc3_clk 24 mhz ds1 t w(clkh) pulse duration, mmc3_clk high 0.5 p- 0.270 (1) ns 295 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-146. switching characteristics for mmc3 - sd/sdio default speed mode (2) (continued) no. parameter description min max unit ds2 t w(clkl) pulse duration, mmc3_clk low 0.5 p- 0.270 (1) ns ds3 t d(clkl-cmdv) delay time, mmc3_clk falling clock edge to mmc3_cmd transition -14.93 14.93 ns ds4 t d(clkl-dv) delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -14.93 14.93 ns (1) p = output mmc3_clk period in ns (2) i in [i:0] = 7 table 5-147. timing requirements for mmc4 - default speed mode (1) no. parameter description min max unit ds5 t su(cmdv-clkh) setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.11 ns ds6 t h(clkh-cmdv) hold time, mmc4_cmd valid after mmc4_clk rising clock edge 20.46 ns ds7 t su(dv-clkh) setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.11 ns ds8 t h(clkh-dv) hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 20.46 ns (1) i in [i:0] = 3 table 5-148. switching characteristics for mmc4 - default speed mode (2) no. parameter description min max unit ds0 fop(clk) operating frequency, mmc4_clk 24 mhz ds1 t w(clkh) pulse duration, mmc4_clk high 0.5 p- 0.270 (1) ns ds2 t w(clkl) pulse duration, mmc4_clk low 0.5 p- 0.270 (1) ns ds3 t d(clkl-cmdv) delay time, mmc4_clk falling clock edge to mmc4_cmd transition -14.93 14.93 ns ds4 t d(clkl-dv) delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -14.93 14.93 ns (1) p = output mmc4_clk period in ns (2) i in [i:0] = 3 figure 5-99. mmc/sd/sdioj in - default speed - receiver mode ds2 ds1 ds0 ds6 ds5 ds8 ds7 mmcj_clk mmcj_cmd mmcj_dat[i:0] sprs906_timing_mmc3_07 296 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-100. mmc/sd/sdioj in - default speed - transmitter mode 5.10.6.21.3.2 mmc3 and mmc4, sd high speed figure 5-101 , figure 5-102 , and table 5-149 through table 5-152 present timing requirements and switching characteristics for mmc3 and mmc4 - sd and sdio high speed in receiver and transmitter mode. table 5-149. timing requirements for mmc3 - sd/sdio high speed mode (1) no. parameter description min max unit hs3 t su(cmdv-clkh) setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.3 ns hs4 t h(clkh-cmdv) hold time, mmc3_cmd valid after mmc3_clk rising clock edge 2.6 ns hs7 t su(dv-clkh) setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.3 ns hs8 t h(clkh-dv) hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 2.6 ns (1) i in [i:0] = 7 table 5-150. switching characteristics for mmc3 - sd/sdio high speed mode (2) no. parameter description min max unit hs1 fop(clk) operating frequency, mmc3_clk 48 mhz hs2h t w(clkh) pulse duration, mmc3_clk high 0.5 p- 0.270 (1) ns hs2l t w(clkl) pulse duration, mmc3_clk low 0.5 p- 0.270 (1) ns hs5 t d(clkl-cmdv) delay time, mmc3_clk falling clock edge to mmc3_cmd transition -7.6 3.6 ns hs6 t d(clkl-dv) delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -7.6 3.6 ns (1) p = output mmc3_clk period in ns (2) i in [i:0] = 7 table 5-151. timing requirements for mmc4 - high speed mode (1) no. parameter description min max unit hs3 t su(cmdv-clkh) setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns hs4 t h(clkh-cmdv) hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns hs7 t su(dv-clkh) setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns hs8 t h(clkh-dv) hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) i in [i:0] = 3 table 5-152. switching characteristics for mmc4 - high speed mode (2) no. parameter description min max unit hs1 fop(clk) operating frequency, mmc4_clk 48 mhz hs2h t w(clkh) pulse duration, mmc4_clk high 0.5 p- 0.270 (1) ns ds2 ds1 ds0 ds3 ds4 mmcj_clk mmcj_cmd mmcj_dat[i:0] sprs906_timing_mmc3_08 297 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-152. switching characteristics for mmc4 - high speed mode (2) (continued) no. parameter description min max unit hs2l t w(clkl) pulse duration, mmc4_clk low 0.5 p- 0.270 (1) ns hs5 t d(clkl-cmdv) delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns hs6 t d(clkl-dv) delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns (1) p = output mmc4_clk period in ns (2) i in [i:0] = 3 figure 5-101. mmc/sd/sdioj in - high speed 3.3v signaling - receiver mode figure 5-102. mmc/sd/sdioj in - high speed 3.3v signaling - transmitter mode 5.10.6.21.3.3 mmc3 and mmc4, sd and sdio sdr12 mode figure 5-103 , figure 5-104 , and table 5-153 , through table 5-156 present timing requirements and switching characteristics for mmc3 and mmc4 - sd and sdio sdr12 in receiver and transmitter mode. table 5-153. timing requirements for mmc3 - sdr12 mode (1) no. parameter description min max unit sdr125 t su(cmdv-clkh) setup time, mmc3_cmd valid before mmc3_clk rising clock edge 25.99 ns sdr126 t h(clkh-cmdv) hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns sdr127 t su(dv-clkh) setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 25.99 ns sdr128 t h(clkh-dv) hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 table 5-154. switching characteristics for mmc3 - sdr12 mode (2) no. parameter description min max unit sdr120 fop(clk) operating frequency, mmc3_clk 24 mhz sdr121 t w(clkh) pulse duration, mmc3_clk high 0.5 p- 0.270 (1) ns mmcj_clk mmcj_cmd mmcj_dat[i:0] hs1 hs2l hs2h hs5 hs6 hs5 hs6 sprs906_timing_mmc3_10 mmcj_clk mmcj_cmd mmcj_dat[i:0] hs1 hs2l hs2h hs3 hs4 hs7 hs8 sprs906_timing_mmc3_09 298 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-154. switching characteristics for mmc3 - sdr12 mode (2) (continued) no. parameter description min max unit sdr122 t w(clkl) pulse duration, mmc3_clk low 0.5 p- 0.270 (1) ns sdr123 t d(clkl-cmdv) delay time, mmc3_clk falling clock edge to mmc3_cmd transition -19.13 16.93 ns sdr124 t d(clkl-dv) delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -19.13 16.93 ns (1) p = output mmc3_clk period in ns (2) i in [i:0] = 7 table 5-155. timing requirements for mmc4 - sdr12 mode (1) no. parameter description min max unit sdr125 t su(cmdv-clkh) setup time, mmc4_cmd valid before mmc4_clk rising clock edge 25.99 ns sdr126 t h(clkh-cmdv) hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns sdr127 t su(dv-clkh) setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 25.99 ns sdr128 t h(clkh-dv) hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) j in [i:0] = 3 table 5-156. switching characteristics for mmc4 - sdr12 mode (2) no. parameter description min max unit sdr120 fop(clk) operating frequency, mmc4_clk 24 mhz sdr121 t w(clkh) pulse duration, mmc4_clk high 0.5 p- 0.270 (1) ns sdr122 t w(clkl) pulse duration, mmc4_clk low 0.5 p- 0.270 (1) ns sdr125 t d(clkl-cmdv) delay time, mmc4_clk falling clock edge to mmc4_cmd transition -19.13 16.93 ns sdr126 t d(clkl-dv) delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -19.13 16.93 ns (1) p = output mmc4_clk period in ns (2) j in [i:0] = 3 figure 5-103. mmc/sd/sdioj in - sdr12 - receiver mode sdr122 sdr121 sdr120 sdr126 sdr125 sdr128 sdr127 mmcj_clk mmcj_cmd mmcj_dat[i:0] sprs906_timing_mmc3_11 299 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-104. mmc/sd/sdioj in - sdr12 - transmitter mode 5.10.6.21.3.4 mmc3 and mmc4, sd sdr25 mode figure 5-105 , figure 5-106 , and table 5-157 , through table 5-160 present timing requirements and switching characteristics for mmc3 and mmc4 - sd and sdio sdr25 in receiver and transmitter mode. table 5-157. timing requirements for mmc3 - sdr25 mode (1) no. parameter description min max unit sdr253 t su(cmdv-clkh) setup time, mmc3_cmd valid before mmc3_clk rising clock edge 5.3 ns sdr254 t h(clkh-cmdv) hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns sdr257 t su(dv-clkh) setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 5.3 ns sdr258 t h(clkh-dv) hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 table 5-158. switching characteristics for mmc3 - sdr25 mode (2) no. parameter description min max unit sdr251 fop(clk) operating frequency, mmc3_clk 48 mhz sdr252 h t w(clkh) pulse duration, mmc3_clk high 0.5 p- 0.270 (1) ns sdr252l t w(clkl) pulse duration, mmc3_clk low 0.5 p- 0.270 (1) ns sdr255 t d(clkl-cmdv) delay time, mmc3_clk falling clock edge to mmc3_cmd transition -8.8 6.6 ns sdr256 t d(clkl-dv) delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -8.8 6.6 ns (1) p = output mmc3_clk period in ns (2) i in [i:0] = 7 table 5-159. timing requirements for mmc4 - sdr25 mode (1) no. parameter description min max unit sdr255 t su(cmdv-clkh) setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.3 ns sdr256 t h(clkh-cmdv) hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns sdr257 t su(dv-clkh) setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.3 ns sdr258 t h(clkh-dv) hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns (1) i in [i:0] = 3 table 5-160. switching characteristics for mmc4 - sdr25 mode (2) no. parameter description min max unit sdr251 fop(clk) operating frequency, mmc4_clk 48 mhz sdr252 h t w(clkh) pulse duration, mmc4_clk high 0.5 p- 0.270 (1) ns sdr122 sdr121 sdr120 sdr123 sdr124 mmcj_clk mmcj_cmd mmcj_dat[i:0] sprs906_timing_mmc3_12 300 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-160. switching characteristics for mmc4 - sdr25 mode (2) (continued) no. parameter description min max unit sdr252l t w(clkl) pulse duration, mmc4_clk low 0.5 p- 0.270 (1) ns sdr255 t d(clkl-cmdv) delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns sdr256 t d(clkl-dv) delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns (1) p = output mmc4_clk period in ns (2) i in [i:0] = 3 figure 5-105. mmc/sd/sdioj in - sdr25 - receiver mode figure 5-106. mmc/sd/sdioj in - sdr25 - transmitter mode 5.10.6.21.3.5 mmc3 sdio high-speed uhs-i sdr50 mode, half cycle figure 5-107 , figure 5-108 , table 5-161 , and table 5-162 present timing requirements and switching characteristics for mmc3 - sdio high speed sdr50 in receiver and transmitter mode. table 5-161. timing requirements for mmc3 - sdr50 mode (1) no. parameter description min max unit sdr503 t su(cmdv-clkh) setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1.48 ns sdr504 t h(clkh-cmdv) hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns sdr507 t su(dv-clkh) setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 1.48 ns sdr508 t h(clkh-dv) hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 table 5-162. switching characteristics for mmc3 - sdr50 mode (2) no. parameter description min max unit sdr501 fop(clk) operating frequency, mmc3_clk 64 mhz sdr502 h t w(clkh) pulse duration, mmc3_clk high 0.5 p- 0.270 (1) ns sdr502l t w(clkl) pulse duration, mmc3_clk low 0.5 p- 0.270 (1) ns mmcj_clk mmcj_cmd mmcj_dat[i:0] sdr251 sdr252l sdr252h sdr255 sdr256 sdr255 sdr256 sprs906_timing_mmc3_14 mmcj_clk mmcj_cmd mmcj_dat[i:0] sdr254 sdr258 sdr253 sdr257 sdr251 sdr252h sdr252l sprs906_timing_mmc3_13 301 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-162. switching characteristics for mmc3 - sdr50 mode (2) (continued) no. parameter description min max unit sdr505 t d(clkl-cmdv) delay time, mmc3_clk falling clock edge to mmc3_cmd transition -3.66 1.46 ns sdr506 t d(clkl-dv) delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -3.66 1.46 ns (1) p = output mmc3_clk period in ns (2) i in [i:0] = 7 figure 5-107. mmc/sd/sdioj in - high speed sdr50 - receiver mode figure 5-108. mmc/sd/sdioj in - high speed sdr50 - transmitter mode note to configure the desired manual io timing mode the user must follow the steps described in section manual io timing modes of the device trm. the associated registers to configure are listed in the cfg register column. for more information see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for mmc3. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-163 manual functions mapping for mmc3 for a definition of the manual modes. table 5-163 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-163. manual functions mapping for mmc3 ball ball name mmc3_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 0 y2 mmc3_clk 1085 21 cfg_mmc3_clk_in mmc3_clk y2 mmc3_clk 1269 0 cfg_mmc3_clk_out mmc3_clk y1 mmc3_cmd 0 0 cfg_mmc3_cmd_in mmc3_cmd y1 mmc3_cmd 128 0 cfg_mmc3_cmd_oen mmc3_cmd y1 mmc3_cmd 98 0 cfg_mmc3_cmd_out mmc3_cmd y4 mmc3_dat0 0 0 cfg_mmc3_dat0_in mmc3_dat0 mmcj_clk mmcj_cmd mmcj_dat[7:0] sdr504 sdr508 sdr503 sdr507 sdr501 sdr502h sdr502l sprs906_timing_mmc3_05 mmcj_clk mmcj_cmd mmcj_dat[7:0] sdr501 sdr502l sdr502h sdr505 sdr506 sdr505 sdr506 sprs906_timing_mmc3_06 302 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-163. manual functions mapping for mmc3 (continued) ball ball name mmc3_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 0 y4 mmc3_dat0 362 0 cfg_mmc3_dat0_oen mmc3_dat0 y4 mmc3_dat0 0 0 cfg_mmc3_dat0_out mmc3_dat0 aa2 mmc3_dat1 7 0 cfg_mmc3_dat1_in mmc3_dat1 aa2 mmc3_dat1 333 0 cfg_mmc3_dat1_oen mmc3_dat1 aa2 mmc3_dat1 0 0 cfg_mmc3_dat1_out mmc3_dat1 aa3 mmc3_dat2 0 0 cfg_mmc3_dat2_in mmc3_dat2 aa3 mmc3_dat2 402 0 cfg_mmc3_dat2_oen mmc3_dat2 aa3 mmc3_dat2 0 0 cfg_mmc3_dat2_out mmc3_dat2 w2 mmc3_dat3 203 0 cfg_mmc3_dat3_in mmc3_dat3 w2 mmc3_dat3 549 0 cfg_mmc3_dat3_oen mmc3_dat3 w2 mmc3_dat3 1 0 cfg_mmc3_dat3_out mmc3_dat3 y3 mmc3_dat4 121 0 cfg_mmc3_dat4_in mmc3_dat4 y3 mmc3_dat4 440 0 cfg_mmc3_dat4_oen mmc3_dat4 y3 mmc3_dat4 206 0 cfg_mmc3_dat4_out mmc3_dat4 aa1 mmc3_dat5 336 0 cfg_mmc3_dat5_in mmc3_dat5 aa1 mmc3_dat5 283 0 cfg_mmc3_dat5_oen mmc3_dat5 aa1 mmc3_dat5 174 0 cfg_mmc3_dat5_out mmc3_dat5 aa4 mmc3_dat6 320 0 cfg_mmc3_dat6_in mmc3_dat6 aa4 mmc3_dat6 443 0 cfg_mmc3_dat6_oen mmc3_dat6 aa4 mmc3_dat6 0 0 cfg_mmc3_dat6_out mmc3_dat6 ab1 mmc3_dat7 2 0 cfg_mmc3_dat7_in mmc3_dat7 ab1 mmc3_dat7 344 0 cfg_mmc3_dat7_oen mmc3_dat7 ab1 mmc3_dat7 0 0 cfg_mmc3_dat7_out mmc3_dat7 5.10.6.22 gpio the general-purpose interface combines eight general-purpose input/output (gpio) banks. each gpio module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 186 pins. these pins can be configured for the following applications: ? data input (capture)/output (drive) ? keyboard interface with a debounce cell ? interrupt generation in active mode upon the detection of external events. detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations ? wake-up request generation in idle mode upon the detection of external events note for more information, see the general-purpose interface chapter of the device trm. note the general-purpose input/output i (i = 1 to 8) bank is also referred to as gpioi. 303 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.23 pru-icss the device programmable real-time unit subsystem and industrial communication subsystem (pru- icss) consists of dual 32-bit load / store risc cpu cores - programmable real-time units (pru0 and pru1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller (pru-icss_intc). the programmable nature of the prus, along with their access to pins, events and all soc resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on-chip (soc). the each pru-icss includes the following main features: ? 21x enhanced gpis (egpis) and 21x enhanced gpos (egpos) with asynchronous capture and serial support per each pru cpu core ? one ethernet mii_rt module (pru-icss_mii_rt) with two mii ports and configurable connections to prus ? 1 mdio port (pru-icss_mii_mdio) ? one industrial ethernet peripheral (iep) to manage/generate industrial ethernet functions ? 1 x 16550-compatible uart with a dedicated 192 mhz clock to support 12mbps profibus ? 1 industrial ethernet timer with 7/9 capture and 8 compare events ? 1 enhanced capture module (ecap) ? 1 interrupt controller (pru-icss_intc) ? a flexible power management support ? integrated switched central resource with programmable priority ? parity control supported by all memories caution the i/o timings provided in this section are valid only if signals within a single ioset are used. the iosets are defined in the table 5-186 and table 5-187 . note for more information about pru-icss subsystems interfaces, please see the device trm. note to configure the desired virtual mode the user must set modeselect bit and delaymode bitfield for each corresponding pad control register. the pad control registers are presented in table 4-32 and described in device trm, control module chapter . 5.10.6.23.1 programmable real-time unit (pru-icss pru) 5.10.6.23.1.1 pru-icss pru direct input/output mode electrical data and timing table 5-164. pru-icss pru timing requirements - direct input mode no. parameter description min max unit 1 t w(gpi) pulse width, gpi 2 p (1) ns 2 t sk(gpi) skew between gpi[20:0] signals 4.5 ns 304 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) icss_clk clock period figure 5-109. pru-icss pru direct input timing (1) m in gpi[m:0] = 20 table 5-165. pru-icss pru switching requirements ? direct output mode no. parameter description min max unit 1 t w(gpo) pulse width, gpo 2 p (1) ns 2 t sk(gpo) skew between gpo[20:0] signals 4.5 ns (1) icss_clk clock period figure 5-110. pru-icss pru direct output timing (1) n in gpo[n:0] = 20 5.10.6.23.1.2 pru-icss pru parallel capture mode electrical data and timing table 5-166. pru-icss pru timing requirements - parallel capture mode no. parameter description min max unit 1 t w(clockin) cyle time, clockin 20 ns 2 t w(clockin_l) pulse duration, clockin low 9 11 ns 3 t w(clockin_h) pulse duration, clockin high 9 11 ns 4 t su(datain-clockin) setup time, datain valid before clockin 4.5 ns 5 t h(clockin-datain) hold time, datain valid after clockin 0 ns figure 5-111. pru-icss pru parallel capture timing - rising edge mode clockin datain 1 3 2 4 5 sprs91x_timing_pru_03 gpi[m:0] 2 1 sprs91x_timing_pru_01 gpo[n:0] 2 1 sprs91x_timing_pru_02 305 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-112. pru-icss pru parallel capture timing - falling edge mode 5.10.6.23.1.3 pru-icss pru shift mode electrical data and timing table 5-167. pru-icss pru timing requirements ? shift in mode no. parameter description min max unit 1 t c(datain) cycle time, datain 10.00 ns 2 t w(datain) pulse width, datain 0.45 p (1) ns (1) p = 10.00ns figure 5-113. pru-icss pru shift in timing table 5-168. pru-icss pru switching requirements - shift out mode no. parameter description min max unit 1 t c(clockout) cycle time, clockout 10.00 ns 2 t w(clockout) pulse width, clockout 0.45 p (1) ns 3 t d(clockout-dataout) delay time, clockout to dataout valid -3.00 3.60 ns (1) p = 10.00ns figure 5-114. pru-icss pru shift out timing datain 1 2 sprs91x_timing_pru_05 clockin datain 1 2 3 4 5 sprs91x_timing_pru_04 clockout dataout 1 2 3 sprs91x_timing_pru_06 306 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.23.1.4 pru-icss pru sigma delta and endat modes table 5-169. pru-icss pru timing requirements - sigma delta mode no. parameter description min max unit 1 tw(sdx_clk) pulse width, sdx_clk 20 ns 2 tsu(sdx_d-sdx_clk) setup time, sdx_d valid before sdx_clk active edge 10 ns 3 th(sdx_clk-sdx_d) hold time, sdx_d valid before sdx_clk active edge 5 ns figure 5-115. pru-icss pru sd_clk falling active edge figure 5-116. pru-icss pru sd_clk rising active edge table 5-170. pru-icss pru timing requirements - endat mode no. parameter description min max unit 1 tw(endatx_in) pulse width, endatx_in 40 ns table 5-171. pru-icss pru switching requirements - endat mode no. parameter description min max unit 2 tw(endatx_clk) pulse width, endatx_clk 20 ns 3 td(endatx_out- endatx_clk) delay time, endatx_clk fall to endatx_out -10 10 ns 4 td(endatx_out_en- endatx_clk) delay time, endatx_clk fall to endatx_out_en -10 10 ns sdx_clk sdx_d 1 2 3 sprs91x_timing_pru_08 sdx_clk sdx_d 1 2 3 sprs91x_timing_pru_07 307 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-117. pru-icss pru endat timing 5.10.6.23.2 pru-icss ethercat (pru-icss ecat) 5.10.6.23.2.1 pru-icss ecat electrical data and timing table 5-172. pru-icss ecat timing requirements ? input validated with latch_in no. parameter description min max unit 1 t w(edio_latch_in) pulse width, edio_latch_in 100.00 ns 2 t su(edio_data_in- edio_latch_in) setup time, edio_data_in valid before edio_latch_in active edge 20.00 ns 3 t h(edio_latch_in- edio_data_in) hold time, edio_data_in valid after edio_latch_in active edge 20.00 ns figure 5-118. pru-icss ecat input validated with latch_in timing edio_latch_in 3 1 2 edio_data_in[7:0] sprs91x_timing_pru_ecat_01 endatx_in endatx_clk 2 1 4 endatx_out endatx_out_en sprs91x_timing_pru_09 3 308 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-173. pru-icss ecat timing requirements ? input validated with syncx no. parameter description min max unit 1 t w(edc_syncx_out) pulse width, edc_syncx_out 100.00 ns 2 t su(edio_data_in- edc_syncx_out) setup time, edio_data_in valid before edc_syncx_out active edge 20.00 ns 3 t h(edc_syncx_out- edio_data_in) hold time, edio_data_in valid after edc_syncx_out active edge 20.00 ns figure 5-119. pru-icss ecat input validated with syncx timing table 5-174. pru-icss ecat timing requirements ? input validated with start of frame (sof) no. parameter description min max unit 1 t w(edio_sof) pulse duration, edio_sof 4 p (1) 5 p (1) ns 2 t su(edio_data_in- edio_sof) setup time, edio_data_in valid before edio_sof active edge 20.00 ns 3 t h(edio_sof- edio_data_in) hold time, edio_data_in valid after edio_sof active edge 20.00 ns (1) icss_iep_clk clock period figure 5-120. pru-icss ecat input validated with sof table 5-175. pru-icss ecat timing requirements - latchx_in no. parameter description min max unit 1 t w(edc_latchx_in) pulse duration, edc_latchx_in 3 p (1) ns edio_sof 3 1 2 edio_data_in[7:0] sprs91x_timing_pru_ecat_03 edc_syncx_out 3 1 2 edio_data_in[7:0] sprs91x_timing_pru_ecat_02 309 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated (1) icss_iep_clk clock period figure 5-121. pru-icss ecat latchx_in timing table 5-176. pru-icss ecat switching requirements - digital ios no. parameter description min max unit 1 t w(edio_outvalid) pulse duration, edio_outvalid 14 p (1) 32 p (1) ns 2 t d(edio_outvalid- edio_data_out) delay time, edio_outvalid to edio_data_out 0.00 18 p (1) ns 1 t sk(edio_data_out) edio_data_out skew 8 ns (1) icss_iep_clk clock period 5.10.6.23.3 pru-icss mii_rt and switch 5.10.6.23.3.1 pru-icss mdio electrical data and timing table 5-177. pru-icss mdio timing requirements ? mdio_data no. parameter description min max unit 1 t su(mdio-mdc) setup time, mdio valid before mdc high 90 ns 2 t h(mdio-mdc) hold time, mdio valid from mdc high 0 ns figure 5-122. pru-icss mdio_data timing - input mode table 5-178. pru-icss mdio switching characteristics - mdio_clk no. parameter description min max unit 1 t c(mdc) cycle time, mdc 400 ns 2 t w(mdch) pulse duration, mdc high 160 ns 3 t w(mdcl) pulse duration, mdc low 160 ns 4 t t(mdc) transition time, mdc 5 ns edc_latchx_in 1 sprs91x_timing_pru_ecat_04 mdio_clk (output) 1 2 mdio_data (input) sprs91x_timing_pru_mii_rt_01 310 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-123. pru-icss mdio_clk timing table 5-179. pru-icss mdio switching characteristics ? mdio_data no. parameter description min max unit 1 t d(mdc-mdio) delay time, mdc high to mdio valid 0 390 ns figure 5-124. pru-icss mdio_data timing ? output mode 5.10.6.23.3.2 pru-icss mii_rt electrical data and timing note in order to guarantee the mii_rt io timing values published in the device data manual, the icss_clk clock must be configured for 200mhz (default value) and the tx_clk_delay bitfield in the pruss_mii_rt_txcfg0/1 register must be set to 6h (non-default value). table 5-180. pru-icss mii_rt timing requirements ? mii[x]_rxclk no. parameter description speed min max unit 1 t c(rx_clk) cycle time, rx_clk 10 mbps 399.96 400.04 ns 100 mbps 39.996 40.004 ns 2 t w(rx_clkh) pulse duration, rx_clk high 10 mbps 140 260 ns 100 mbps 14 26 ns 3 t w(rx_clkl) pulse duration, rx_clk low 10 mbps 140 260 ns 100 mbps 14 26 ns figure 5-125. pru-icss mii[x]_rxclk timing 1 mdio_clk (output) mdio_data (output) sprs91x_timing_pru_mii_rt_03 mdio_clk 2 3 1 4 4 sprs91x_timing_pru_mii_rt_02 mii_rxclk 2 3 1 4 4 sprs91x_timing_pru_mii_rt_04 311 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-181. pru-icss mii_rt timing requirements - mii[x]_txclk no. parameter description speed min max unit 1 t c(tx_clk) cycle time, tx_clk 10 mbps 399.96 400.04 ns 100 mbps 39.996 40.004 ns 2 t w(tx_clkh) pulse duration, tx_clk high 10 mbps 140 260 ns 100 mbps 14 26 ns 3 t w(tx_clkl) pulse duration, tx_clk low 10 mbps 140 260 ns 100 mbps 14 26 ns 4 t t(tx_clk) transition time, tx_clk 10 mbps 3 ns 100 mbps 3 ns figure 5-126. pru-icss mii[x]_txclk timing table 5-182. pru-icss mii_rt timing requirements - mii_rxd[3:0], mii_rxdv, and mii_rxer no. parameter description speed min max unit 1 t su(rxd-rx_clk) setup time, rxd[3:0] valid before rx_clk 10 mbps 8 ns t su(rx_dv-rx_clk) setup time, rx_dv valid before rx_clk t su(rx_er-rx_clk) setup time, rx_er valid before rx_clk t su(rxd-rx_clk) setup time, rxd[3:0] valid before rx_clk 100 mbps 8 ns t su(rx_dv-rx_clk) setup time, rx_dv valid before rx_clk t su(rx_er-rx_clk) setup time, rx_er valid before rx_clk 2 t h(rx_clk-rxd) hold time rxd[3:0] valid after rx_clk 10 mbps 8 ns t h(rx_clk-rx_dv) hold time rx_dv valid after rx_clk t h(rx_clk-rx_er) hold time rx_er valid after rx_clk t h(rx_clk-rxd) hold time rxd[3:0] valid after rx_clk 100 mbps 8 ns t h(rx_clk-rx_dv) hold time rx_dv valid after rx_clk t h(rx_clk-rx_er) hold time rx_er valid after rx_clk figure 5-127. pru-icss mii_rxd[3:0], mii_rxdv, and mii_rxer timing mii_mrclk (input) 1 2 mii_rxd[3:0], mii_rxdv, mii_rxer (inputs) sprs91x_timing_pru_mii_rt_06 mii_txclk 2 3 1 4 4 sprs91x_timing_pru_mii_rt_05 312 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-183. pru-icss mii_rt switching characteristics - mii_txd[3:0] and mii_txen no. parameter description speed min max unit 1 t d(tx_clk-txd) delay time, tx_clk high to txd[3:0] valid 10 mbps 5 25 ns t d(tx_clk-tx_en) delay time, tx_clk to tx_en valid t d(tx_clk-txd) delay time, tx_clk high to txd[3:0] valid 100 mbps 5 25 ns t d(tx_clk-tx_en) delay time, tx_clk to tx_en valid figure 5-128. pru-icss mii_txd[3:0], mii_txen timing 5.10.6.23.4 pru-icss universal asynchronous receiver transmitter (pru-icss uart) table 5-184. timing requirements for pru-icss uart receive no. parameter description min max unit 3 t w(rx) pulse duration, receive start, stop, data bit 0.96u (1) 1.05u (1) ns (1) u = uart baud time = 1/programmed baud rate. table 5-185. switching characteristics over recommended operating conditions for pru-icss uart transmit no. parameter description min max unit 1 ? baud(baud) maximum programmable baud rate 0 12 mhz 2 t w(tx) pulse duration, transmit start, stop, data bit u - 2 (1) u + 2 (1) ns (1) u = uart baud time = 1/programmed baud rate. figure 5-129. pru-icss uart timing 5.10.6.23.5 pru-icss iosets in table 5-186 are presented the specific groupings of signals (ioset) for use with pru-icss1. 2 1 start bit data bits uart_txd 3 data bits bit start 4 uart_rxd sprs960_timing_pru_uart_01 1 mii_txclk (input) mii_txd[3:0], mii_txen (outputs) sprs91x_timing_pru_mii_rt_07 313 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-186. pru-icss1 iosets signals ioset1 ioset2 ball mux ball mux pru-icss 1 pr1_pru1_gpi20 d13 12 pr1_pru1_gpi19 c13 12 pr1_pru1_gpi18 e13 12 pr1_pru1_gpi17 b13 12 pr1_pru1_gpi16 f11 12 pr1_pru1_gpi15 e11 12 pr1_pru1_gpi14 a13 12 pr1_pru1_gpi13 a12 12 pr1_pru1_gpi12 b12 12 pr1_pru1_gpi11 c11 12 pr1_pru1_gpi10 d11 12 pr1_pru1_gpo20 d13 13 pr1_pru1_gpo19 c13 13 pr1_pru1_gpo18 e13 13 pr1_pru1_gpo17 b13 13 pr1_pru1_gpo16 f11 13 pr1_pru1_gpo15 e11 13 pr1_pru1_gpo14 a13 13 pr1_pru1_gpo13 a12 13 pr1_pru1_gpo12 b12 13 pr1_pru1_gpo11 c11 13 pr1_pru1_gpo10 d11 13 pr1_pru1_gpi9 b11 12 pr1_pru1_gpi8 c10 12 pr1_pru1_gpi7 d10 12 pr1_pru1_gpi6 e10 12 pr1_pru1_gpi5 b10 12 pr1_pru1_gpi4 a10 12 pr1_pru1_gpi3 f10 12 pr1_pru1_gpi2 a11 12 pr1_pru1_gpi1 a8 12 pr1_pru1_gpi0 a9 12 pr1_pru1_gpo9 b11 13 pr1_pru1_gpo8 c10 13 pr1_pru1_gpo7 d10 13 pr1_pru1_gpo6 e10 13 pr1_pru1_gpo5 b10 13 pr1_pru1_gpo4 a10 13 pr1_pru1_gpo3 f10 13 pr1_pru1_gpo2 a11 13 pr1_pru1_gpo1 a8 13 pr1_pru1_gpo0 a9 13 pr1_mii1_crs d13 11 pr1_mii1_rxlink e13 11 pr1_mii1_col c13 11 314 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-186. pru-icss1 iosets (continued) signals ioset1 ioset2 ball mux ball mux pr1_mii0_col l5 11 pr1_mii0_rxlink l6 11 pr1_mii0_crs p4 11 pr1_edio_data_out7 a7 13 pr1_edio_data_out6 b9 13 pr1_edio_data_out5 c8 13 pr1_edio_data_out4 b8 13 pr1_edio_data_out3 e8 13 pr1_edio_data_out2 c7 13 pr1_edio_data_out1 b7 13 pr1_edio_data_out0 d8 13 pr1_edio_data_in7 a7 12 pr1_edio_data_in6 b9 12 pr1_edio_data_in5 c8 12 pr1_edio_data_in4 b8 12 pr1_edio_data_in3 e8 12 pr1_edio_data_in2 c7 12 pr1_edio_data_in1 b7 12 pr1_edio_data_in0 d8 12 pr1_edio_sof a11 11 pr1_edc_latch0_in a9 11 pr1_edc_sync0_out a8 11 pr1_uart0_cts_n e8 11 pr1_uart0_rts_n b8 11 pr1_uart0_txd b9 11 pr1_uart0_rxd c8 11 pr1_ecap0_ecap_capin_apwm _o a7 11 pru-icss 1 mii pr1_mii1_txd3 b10 11 pr1_mii1_txd2 e10 11 pr1_mii1_txd1 b11 11 pr1_mii1_txd0 d11 11 pr1_mii1_rxd3 a12 11 pr1_mii1_rxd2 a13 11 pr1_mii1_rxd1 e11 11 pr1_mii1_rxd0 f11 11 pr1_mii1_rxdv b12 11 pr1_mii1_txen a10 11 pr1_mii1_rxer b13 11 pr1_mii_mr1_clk c11 11 pr1_mii_mt1_clk f10 11 pr1_mii0_txd3 p2 11 pr1_mii0_txd2 n1 11 pr1_mii0_txd1 n3 11 pr1_mii0_txd0 n4 11 pr1_mii0_rxd3 t4 11 315 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-186. pru-icss1 iosets (continued) signals ioset1 ioset2 ball mux ball mux pr1_mii0_rxd2 t5 11 pr1_mii0_rxd1 r2 11 pr1_mii0_rxd0 r1 11 pr1_mii0_rxdv n5 11 pr1_mii0_txen p1 11 pr1_mii0_rxer p3 11 pr1_mii_mt0_clk n2 11 pr1_mii_mr0_clk n6 11 pr1_mdio_mdclk d10 11 pr1_mdio_data c10 11 in table 5-187 , table 5-188 and table 5-189 are presented the specific groupings of signals (ioset) for use with pru-icss2. table 5-187. pru-icss2 iosets signals ioset1 ioset2 ball mux ball mux pru-icss 2 pr2_pru1_gpi16 n4 12 e16 12 pr2_pru1_gpi15 n3 12 e17 12 pr2_pru1_gpi14 p1 12 a19 12 pr2_pru1_gpi13 n1 12 b18 12 pr2_pru1_gpi12 p2 12 b16 12 pr2_pru1_gpi11 n2 12 b17 12 pr2_pru1_gpi10 r1 12 a18 12 pr2_pru1_gpi9 r2 12 b14 12 pr2_pru1_gpi8 p3 12 d14 12 pr2_pru1_gpi7 p4 12 c16 12 pr2_pru1_gpi6 t5 12 j24 12 pr2_pru1_gpi5 t4 12 j25 12 pr2_pru1_gpi4 n6 12 ac4 12 pr2_pru1_gpi3 n5 12 aa5 12 pr2_pru1_gpi2 p5 12 u6 12 pr2_pru1_gpi1 l6 12 ac3 12 pr2_pru1_gpi0 l5 12 d23 12 pr2_pru1_gpo16 n4 13 e16 13 pr2_pru1_gpo15 n3 13 e17 13 pr2_pru1_gpo14 p1 13 a19 13 pr2_pru1_gpo13 n1 13 b18 13 pr2_pru1_gpo12 p2 13 b16 13 pr2_pru1_gpo11 n2 13 b17 13 pr2_pru1_gpo10 r1 13 a18 13 pr2_pru1_gpo9 r2 13 b14 13 pr2_pru1_gpo8 p3 13 d14 13 pr2_pru1_gpo7 p4 13 c16 13 pr2_pru1_gpo6 t5 13 j24 13 316 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-187. pru-icss2 iosets (continued) signals ioset1 ioset2 ball mux ball mux pr2_pru1_gpo5 t4 13 j25 13 pr2_pru1_gpo4 n6 13 ac4 13 pr2_pru1_gpo3 n5 13 aa5 13 pr2_pru1_gpo2 p5 13 u6 13 pr2_pru1_gpo1 l6 13 ac3 13 pr2_pru1_gpo0 l5 13 d23 13 pr2_pru0_gpi20 f16 12 pr2_pru0_gpi19 d19 12 pr2_pru0_gpi18 e19 12 pr2_pru0_gpi17 b21 12 pr2_pru0_gpi16 a21 12 pr2_pru0_gpi15 b23 12 pr2_pru0_gpi14 b22 12 pr2_pru0_gpi13 a23 12 pr2_pru0_gpi12 a22 12 pr2_pru0_gpi11 ab1 12 pr2_pru0_gpi10 aa4 12 pr2_pru0_gpi9 aa1 12 pr2_pru0_gpi8 y3 12 pr2_pru0_gpi7 w2 12 pr2_pru0_gpi6 aa3 12 pr2_pru0_gpi5 aa2 12 pr2_pru0_gpi4 y4 12 pr2_pru0_gpi3 y1 12 pr2_pru0_gpi2 y2 12 pr2_pru0_gpi1 y6 12 pr2_pru0_gpi0 y5 12 pr2_pru0_gpo20 f16 13 pr2_pru0_gpo19 d19 13 pr2_pru0_gpo18 e19 13 pr2_pru0_gpo17 b21 13 pr2_pru0_gpo16 a21 13 pr2_pru0_gpo15 b23 13 pr2_pru0_gpo14 b22 13 pr2_pru0_gpo13 a23 13 pr2_pru0_gpo12 a22 13 pr2_pru0_gpo11 ab1 13 pr2_pru0_gpo10 aa4 13 pr2_pru0_gpo9 aa1 13 pr2_pru0_gpo8 y3 13 pr2_pru0_gpo7 w2 13 pr2_pru0_gpo6 aa3 13 pr2_pru0_gpo5 aa2 13 pr2_pru0_gpo4 y4 13 pr2_pru0_gpo3 y1 13 pr2_pru0_gpo2 y2 13 317 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-187. pru-icss2 iosets (continued) signals ioset1 ioset2 ball mux ball mux pr2_pru0_gpo1 y6 13 pr2_pru0_gpo0 y5 13 pr2_mii1_crs j24 11 pr2_mii1_rxlink b23 11 pr2_mii0_crs a22 11 pr2_mii0_rxlink b21 11 pr2_mii0_col a23 11 pr2_mii1_col j25 11 pru-icss 2 mii pr2_mii1_txd3 y2 11 pr2_mii1_txd2 y1 11 pr2_mii1_txd1 y4 11 pr2_mii1_txd0 aa2 11 pr2_mii1_rxd3 y3 11 pr2_mii1_rxd2 aa1 11 pr2_mii1_rxd1 aa4 11 pr2_mii1_rxd0 ab1 11 pr2_mii_mr1_clk aa3 11 pr2_mii1_rxer b22 11 pr2_mii_mt1_clk y5 11 pr2_mii1_rxdv w2 11 pr2_mii1_txen y6 11 pr2_mii0_txd3 b17 11 pr2_mii0_txd2 b16 11 pr2_mii0_txd1 b18 11 pr2_mii0_txd0 a19 11 pr2_mii0_rxd3 f16 11 pr2_mii0_rxd2 e19 11 pr2_mii0_rxd1 d19 11 pr2_mii0_rxd0 a21 11 pr2_mii_mr0_clk e17 11 pr2_mii0_rxer d14 11 pr2_mii_mt0_clk b14 11 pr2_mii0_rxdv e16 11 pr2_mii0_txen a18 11 pr2_mdio_mdclk c16 11 aa5 11 pr2_mdio_data c17 11 ac4 11 table 5-188. pru-icss2 iosets (endat) (1) signals ioset3 ioset4 ball mux ball mux pru-icss 2 endat pr2_pru1_endat0_clk l5 13 d23 13 pr2_pru1_endat0_out l6 13 ac3 13 pr2_pru1_endat0_out_en p5 13 u6 13 pr2_pru1_endat1_clk n5 13 aa5 13 318 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-188. pru-icss2 iosets (endat) (1) (continued) signals ioset3 ioset4 ball mux ball mux pr2_pru1_endat1_out n6 13 ac4 13 pr2_pru1_endat1_out_en t4 13 j25 13 pr2_pru1_endat2_clk t5 13 j24 13 pr2_pru1_endat2_out p4 13 c16 13 pr2_pru1_endat2_out_en p3 13 d14 13 pr2_pru1_endat0_in r2 12 b14 12 pr2_pru1_endat1_in r1 12 a18 12 pr2_pru1_endat2_in n2 12 b17 12 (1) these signals are internally muxed with the pru gpi/gpo signals. refer to the pru chapter in the trm for more details about the pru-icss internal wrapper multiplexing. table 5-189. pru-icss2 iosets (sigma delta) (1) signals ioset4 ball mux pru-icss 2 sd pr2_pru0_sd0_clk y5 12 pr2_pru0_sd0_d y6 12 pr2_pru0_sd1_clk y2 12 pr2_pru0_sd1_d y1 12 pr2_pru0_sd2_clk y4 12 pr2_pru0_sd2_d aa2 12 pr2_pru0_sd3_clk aa3 12 pr2_pru0_sd3_d w2 12 pr2_pru0_sd4_clk y3 12 pr2_pru0_sd4_d aa1 12 pr2_pru0_sd5_clk aa4 12 pr2_pru0_sd5_d ab1 12 pr2_pru0_sd6_clk a22 12 pr2_pru0_sd6_d a23 12 pr2_pru0_sd7_clk b22 12 pr2_pru0_sd7_d b23 12 pr2_pru0_sd8_clk a21 12 pr2_pru0_sd8_d b21 12 (1) these signals are internally muxed with the pru gpi/gpo signals. refer to the pru chapter in the trm for more details about the pru-icss internal wrapper multiplexing. 5.10.6.23.6 pru-icss manual functional mapping note to configure the desired manual io timing mode the user must follow the steps described in section " manual io timing modes " of the device trm. the associated registers to configure are listed in the cfg register column. for more information see the control module chapter in the device trm. manual io timings modes must be used to guaranteed some io timings for pru-icss1 pru1 direct input mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-190 manual functions mapping for pru-icss1 pru1 direct input mode for a definition of the manual modes. 319 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-190 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-190. manual functions mapping for pru-icss1 pru1 direct input mode ball ball name pr1_pru1_dir_in_manual cfg register muxmode a_delay (ps) g_delay (ps) 12 d10 vin2a_d10 0 800 cfg_vin2a_d10_in pr1_pru1_gpi7 c10 vin2a_d11 0 0 cfg_vin2a_d11_in pr1_pru1_gpi8 b11 vin2a_d12 0 200 cfg_vin2a_d12_in pr1_pru1_gpi9 d11 vin2a_d13 0 0 cfg_vin2a_d13_in pr1_pru1_gpi10 c11 vin2a_d14 0 0 cfg_vin2a_d14_in pr1_pru1_gpi11 b12 vin2a_d15 0 400 cfg_vin2a_d15_in pr1_pru1_gpi12 a12 vin2a_d16 0 300 cfg_vin2a_d16_in pr1_pru1_gpi13 a13 vin2a_d17 0 400 cfg_vin2a_d17_in pr1_pru1_gpi14 e11 vin2a_d18 0 900 cfg_vin2a_d18_in pr1_pru1_gpi15 f11 vin2a_d19 0 1500 cfg_vin2a_d19_in pr1_pru1_gpi16 b13 vin2a_d20 0 100 cfg_vin2a_d20_in pr1_pru1_gpi17 e13 vin2a_d21 0 500 cfg_vin2a_d21_in pr1_pru1_gpi18 c13 vin2a_d22 0 500 cfg_vin2a_d22_in pr1_pru1_gpi19 d13 vin2a_d23 0 600 cfg_vin2a_d23_in pr1_pru1_gpi20 a9 vin2a_d3 0 900 cfg_vin2a_d3_in pr1_pru1_gpi0 a8 vin2a_d4 0 100 cfg_vin2a_d4_in pr1_pru1_gpi1 a11 vin2a_d5 0 600 cfg_vin2a_d5_in pr1_pru1_gpi2 f10 vin2a_d6 0 200 cfg_vin2a_d6_in pr1_pru1_gpi3 a10 vin2a_d7 0 400 cfg_vin2a_d7_in pr1_pru1_gpi4 b10 vin2a_d8 0 500 cfg_vin2a_d8_in pr1_pru1_gpi5 e10 vin2a_d9 0 600 cfg_vin2a_d9_in pr1_pru1_gpi6 manual io timings modes must be used to guaranteed some io timings for pru-icss1 pru1 direct output mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-191 manual functions mapping for pru-icss1 pru1 direct output mode for a definition of the manual modes. table 5-191 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-191. manual functions mapping for pru-icss1 pru1 direct output mode ball ball name pr1_pru1_dir_out_manual cfg register muxmode a_delay (ps) g_delay (ps) 13 d10 vin2a_d10 0 1000 cfg_vin2a_d10_out pr1_pru1_gpo7 c10 vin2a_d11 0 1300 cfg_vin2a_d11_out pr1_pru1_gpo8 b11 vin2a_d12 0 2300 cfg_vin2a_d12_out pr1_pru1_gpo9 d11 vin2a_d13 0 2200 cfg_vin2a_d13_out pr1_pru1_gpo10 c11 vin2a_d14 0 1800 cfg_vin2a_d14_out pr1_pru1_gpo11 b12 vin2a_d15 0 1800 cfg_vin2a_d15_out pr1_pru1_gpo12 a12 vin2a_d16 0 1600 cfg_vin2a_d16_out pr1_pru1_gpo13 a13 vin2a_d17 0 2000 cfg_vin2a_d17_out pr1_pru1_gpo14 e11 vin2a_d18 0 700 cfg_vin2a_d18_out pr1_pru1_gpo15 f11 vin2a_d19 0 700 cfg_vin2a_d19_out pr1_pru1_gpo16 b13 vin2a_d20 0 500 cfg_vin2a_d20_out pr1_pru1_gpo17 e13 vin2a_d21 0 400 cfg_vin2a_d21_out pr1_pru1_gpo18 320 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-191. manual functions mapping for pru-icss1 pru1 direct output mode (continued) ball ball name pr1_pru1_dir_out_manual cfg register muxmode a_delay (ps) g_delay (ps) 13 c13 vin2a_d22 0 0 cfg_vin2a_d22_out pr1_pru1_gpo19 d13 vin2a_d23 0 400 cfg_vin2a_d23_out pr1_pru1_gpo20 a9 vin2a_d3 0 2200 cfg_vin2a_d3_out pr1_pru1_gpo0 a8 vin2a_d4 540 2800 cfg_vin2a_d4_out pr1_pru1_gpo1 a11 vin2a_d5 0 400 cfg_vin2a_d5_out pr1_pru1_gpo2 f10 vin2a_d6 0 1500 cfg_vin2a_d6_out pr1_pru1_gpo3 a10 vin2a_d7 0 2200 cfg_vin2a_d7_out pr1_pru1_gpo4 b10 vin2a_d8 0 2600 cfg_vin2a_d8_out pr1_pru1_gpo5 e10 vin2a_d9 0 2300 cfg_vin2a_d9_out pr1_pru1_gpo6 manual io timings modes must be used to guaranteed some io timings for pru-icss1 pru1 parallel capture mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-192 manual functions mapping for pru-icss1 pru1 parallel capture mode for a definition of the manual modes. table 5-192 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-192. manual functions mapping for pru-icss1 pru1 parallel capture mode ball ball name pr1_pru1_par_cap_manual cfg register muxmode a_delay (ps) g_delay (ps) 12 d10 vin2a_d10 1535 0 cfg_vin2a_d10_in pr1_pru1_gpi7 c10 vin2a_d11 1151 0 cfg_vin2a_d11_in pr1_pru1_gpi8 b11 vin2a_d12 1173 0 cfg_vin2a_d12_in pr1_pru1_gpi9 d11 vin2a_d13 970 0 cfg_vin2a_d13_in pr1_pru1_gpi10 c11 vin2a_d14 1196 0 cfg_vin2a_d14_in pr1_pru1_gpi11 b12 vin2a_d15 1286 0 cfg_vin2a_d15_in pr1_pru1_gpi12 a12 vin2a_d16 1354 0 cfg_vin2a_d16_in pr1_pru1_gpi13 a13 vin2a_d17 1331 0 cfg_vin2a_d17_in pr1_pru1_gpi14 e11 vin2a_d18 2097 0 cfg_vin2a_d18_in pr1_pru1_gpi15 f11 vin2a_d19 0 453 cfg_vin2a_d19_in pr1_pru1_gpi16 a9 vin2a_d3 1566 0 cfg_vin2a_d3_in pr1_pru1_gpi0 a8 vin2a_d4 1012 0 cfg_vin2a_d4_in pr1_pru1_gpi1 a11 vin2a_d5 1337 0 cfg_vin2a_d5_in pr1_pru1_gpi2 f10 vin2a_d6 1130 0 cfg_vin2a_d6_in pr1_pru1_gpi3 a10 vin2a_d7 1202 0 cfg_vin2a_d7_in pr1_pru1_gpi4 b10 vin2a_d8 1395 0 cfg_vin2a_d8_in pr1_pru1_gpi5 e10 vin2a_d9 1338 0 cfg_vin2a_d9_in pr1_pru1_gpi6 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru0 ioset2 direct input mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-193 manual functions mapping for pru-icss2 pru0 ioset2 direct input mode for a definition of the manual modes. table 5-193 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. 321 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-193. manual functions mapping for pru-icss2 pru0 ioset2 direct input mode ball ball name pr2_pru0_dir_in_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 12 y5 gpio6_10 1000 3300 cfg_gpio6_10_in pr2_pru0_gpi0 y6 gpio6_11 1000 3400 cfg_gpio6_11_in pr2_pru0_gpi1 f16 mcasp1_axr15 0 1300 cfg_mcasp1_axr15_in pr2_pru0_gpi20 e19 mcasp2_aclkx 0 800 cfg_mcasp2_aclkx_in pr2_pru0_gpi18 a21 mcasp2_axr2 0 1900 cfg_mcasp2_axr2_in pr2_pru0_gpi16 b21 mcasp2_axr3 0 1400 cfg_mcasp2_axr3_in pr2_pru0_gpi17 d19 mcasp2_fsx 0 1400 cfg_mcasp2_fsx_in pr2_pru0_gpi19 b22 mcasp3_axr0 0 1400 cfg_mcasp3_axr0_in pr2_pru0_gpi14 b23 mcasp3_axr1 0 1000 cfg_mcasp3_axr1_in pr2_pru0_gpi15 a23 mcasp3_fsx 0 1300 cfg_mcasp3_fsx_in pr2_pru0_gpi13 y2 mmc3_clk 1000 3700 cfg_mmc3_clk_in pr2_pru0_gpi2 y1 mmc3_cmd 1000 3500 cfg_mmc3_cmd_in pr2_pru0_gpi3 y4 mmc3_dat0 1000 3500 cfg_mmc3_dat0_in pr2_pru0_gpi4 aa2 mmc3_dat1 1000 4000 cfg_mmc3_dat1_in pr2_pru0_gpi5 aa3 mmc3_dat2 1000 3300 cfg_mmc3_dat2_in pr2_pru0_gpi6 w2 mmc3_dat3 1000 3900 cfg_mmc3_dat3_in pr2_pru0_gpi7 y3 mmc3_dat4 1000 3500 cfg_mmc3_dat4_in pr2_pru0_gpi8 aa1 mmc3_dat5 1000 3600 cfg_mmc3_dat5_in pr2_pru0_gpi9 aa4 mmc3_dat6 1000 3500 cfg_mmc3_dat6_in pr2_pru0_gpi10 ab1 mmc3_dat7 1000 3100 cfg_mmc3_dat7_in pr2_pru0_gpi11 a22 mcasp3_aclkx 0 0 cfg_mcasp3_aclkx_in pr2_pru0_gpi12 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru0 ioset2 direct output mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-194 manual functions mapping for pru-icss2 pru0 ioset2 direct output mode for a definition of the manual modes. table 5-194 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-194. manual functions mapping for pru-icss2 pru0 ioset2 direct output mode ball ball name pr2_pru0_dir_out_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 13 y5 gpio6_10 1800 1900 cfg_gpio6_10_out pr2_pru0_gpo0 y6 gpio6_11 2500 2100 cfg_gpio6_11_out pr2_pru0_gpo1 f16 mcasp1_axr15 0 400 cfg_mcasp1_axr15_out pr2_pru0_gpo20 e19 mcasp2_aclkx 0 400 cfg_mcasp2_aclkx_out pr2_pru0_gpo18 a21 mcasp2_axr2 0 500 cfg_mcasp2_axr2_out pr2_pru0_gpo16 b21 mcasp2_axr3 0 500 cfg_mcasp2_axr3_out pr2_pru0_gpo17 d19 mcasp2_fsx 0 0 cfg_mcasp2_fsx_out pr2_pru0_gpo19 a22 mcasp3_aclkx 0 500 cfg_mcasp3_aclkx_out pr2_pru0_gpo12 b22 mcasp3_axr0 0 0 cfg_mcasp3_axr0_out pr2_pru0_gpo14 b23 mcasp3_axr1 0 200 cfg_mcasp3_axr1_out pr2_pru0_gpo15 a23 mcasp3_fsx 0 300 cfg_mcasp3_fsx_out pr2_pru0_gpo13 y2 mmc3_clk 2100 2200 cfg_mmc3_clk_out pr2_pru0_gpo2 y1 mmc3_cmd 2300 2300 cfg_mmc3_cmd_out pr2_pru0_gpo3 y4 mmc3_dat0 2000 1600 cfg_mmc3_dat0_out pr2_pru0_gpo4 322 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-194. manual functions mapping for pru-icss2 pru0 ioset2 direct output mode (continued) ball ball name pr2_pru0_dir_out_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 13 aa2 mmc3_dat1 2000 1700 cfg_mmc3_dat1_out pr2_pru0_gpo5 aa3 mmc3_dat2 2050 2200 cfg_mmc3_dat2_out pr2_pru0_gpo6 w2 mmc3_dat3 2000 2000 cfg_mmc3_dat3_out pr2_pru0_gpo7 y3 mmc3_dat4 2150 2600 cfg_mmc3_dat4_out pr2_pru0_gpo8 aa1 mmc3_dat5 2400 2600 cfg_mmc3_dat5_out pr2_pru0_gpo9 aa4 mmc3_dat6 2200 2300 cfg_mmc3_dat6_out pr2_pru0_gpo10 ab1 mmc3_dat7 1800 2400 cfg_mmc3_dat7_out pr2_pru0_gpo11 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset1 direct input mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-195 manual functions mapping for pru-icss2 pru1 ioset1 direct input mode for a definition of the manual modes. table 5-195 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-195. manual functions mapping for pru-icss2 pru1 ioset1 direct input mode ball ball name pr2_pru1_dir_in_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 12 p5 rmii_mhz_50_cl k 1400 1200 cfg_rmii_mhz_50_clk_in pr2_pru1_gpi2 l6 mdio_d 1300 1600 cfg_mdio_d_in pr2_pru1_gpi1 l5 mdio_mclk 1400 800 cfg_mdio_mclk_in pr2_pru1_gpi0 n2 rgmii0_rxc 1400 500 cfg_rgmii0_rxc_in pr2_pru1_gpi11 p2 rgmii0_rxctl 1400 1800 cfg_rgmii0_rxctl_in pr2_pru1_gpi12 n4 rgmii0_rxd0 1400 1300 cfg_rgmii0_rxd0_in pr2_pru1_gpi16 n3 rgmii0_rxd1 1400 1650 cfg_rgmii0_rxd1_in pr2_pru1_gpi15 p1 rgmii0_rxd2 1400 1400 cfg_rgmii0_rxd2_in pr2_pru1_gpi14 n1 rgmii0_rxd3 1400 1650 cfg_rgmii0_rxd3_in pr2_pru1_gpi13 t4 rgmii0_txc 1400 900 cfg_rgmii0_txc_in pr2_pru1_gpi5 t5 rgmii0_txctl 1400 1300 cfg_rgmii0_txctl_in pr2_pru1_gpi6 r1 rgmii0_txd0 1400 900 cfg_rgmii0_txd0_in pr2_pru1_gpi10 r2 rgmii0_txd1 1300 1400 cfg_rgmii0_txd1_in pr2_pru1_gpi9 p3 rgmii0_txd2 1300 1100 cfg_rgmii0_txd2_in pr2_pru1_gpi8 p4 rgmii0_txd3 1300 1300 cfg_rgmii0_txd3_in pr2_pru1_gpi7 n5 uart3_rxd 1300 1000 cfg_uart3_rxd_in pr2_pru1_gpi3 n6 uart3_txd 1300 800 cfg_uart3_txd_in pr2_pru1_gpi4 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset2 direct input mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-196 manual functions mapping for pru-icss2 pru1 ioset2 direct input mode for a definition of the manual modes. table 5-196 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. 323 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-196. manual functions mapping for pru-icss2 pru1 ioset2 direct input mode ball ball name pr2_pru1_dir_in_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 12 c16 mcasp1_aclkx 400 0 cfg_mcasp1_aclkx_in pr2_pru1_gpi7 d14 mcasp1_axr0 700 200 cfg_mcasp1_axr0_in pr2_pru1_gpi8 b14 mcasp1_axr1 600 300 cfg_mcasp1_axr1_in pr2_pru1_gpi9 b16 mcasp1_axr10 600 500 cfg_mcasp1_axr10_in pr2_pru1_gpi12 b18 mcasp1_axr11 700 500 cfg_mcasp1_axr11_in pr2_pru1_gpi13 a19 mcasp1_axr12 500 0 cfg_mcasp1_axr12_in pr2_pru1_gpi14 e17 mcasp1_axr13 600 200 cfg_mcasp1_axr13_in pr2_pru1_gpi15 e16 mcasp1_axr14 600 0 cfg_mcasp1_axr14_in pr2_pru1_gpi16 a18 mcasp1_axr8 800 0 cfg_mcasp1_axr8_in pr2_pru1_gpi10 b17 mcasp1_axr9 600 300 cfg_mcasp1_axr9_in pr2_pru1_gpi11 d23 mcasp4_axr1 500 0 cfg_mcasp4_axr1_in pr2_pru1_gpi0 ac3 mcasp5_aclkx 2100 1959 cfg_mcasp5_aclkx_in pr2_pru1_gpi1 aa5 mcasp5_axr0 2300 2000 cfg_mcasp5_axr0_in pr2_pru1_gpi3 ac4 mcasp5_axr1 2300 1800 cfg_mcasp5_axr1_in pr2_pru1_gpi4 u6 mcasp5_fsx 2100 1780 cfg_mcasp5_fsx_in pr2_pru1_gpi2 j25 xref_clk0 0 0 cfg_xref_clk0_in pr2_pru1_gpi5 j24 xref_clk1 0 0 cfg_xref_clk1_in pr2_pru1_gpi6 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset1 direct output mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-197 manual functions mapping for pru-icss2 pru1 ioset1 direct output mode for a definition of the manual modes. table 5-197 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-197. manual functions mapping for pru-icss2 pru1 ioset1 direct output mode ball ball name pr2_pru1_dir_out_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 13 p5 rmii_mhz_50_clk 2306 100 cfg_rmii_mhz_50_clk_out pr2_pru1_gpo2 l6 mdio_d 1900 2000 cfg_mdio_d_out pr2_pru1_gpo1 l5 mdio_mclk 2000 1100 cfg_mdio_mclk_out pr2_pru1_gpo0 n2 rgmii0_rxc 2000 1200 cfg_rgmii0_rxc_out pr2_pru1_gpo11 p2 rgmii0_rxctl 2000 1700 cfg_rgmii0_rxctl_out pr2_pru1_gpo12 n4 rgmii0_rxd0 2000 1000 cfg_rgmii0_rxd0_out pr2_pru1_gpo16 n3 rgmii0_rxd1 2200 1000 cfg_rgmii0_rxd1_out pr2_pru1_gpo15 p1 rgmii0_rxd2 2200 1300 cfg_rgmii0_rxd2_out pr2_pru1_gpo14 n1 rgmii0_rxd3 2250 1100 cfg_rgmii0_rxd3_out pr2_pru1_gpo13 t4 rgmii0_txc 2350 1000 cfg_rgmii0_txc_out pr2_pru1_gpo5 t5 rgmii0_txctl 2000 1200 cfg_rgmii0_txctl_out pr2_pru1_gpo6 r1 rgmii0_txd0 2000 1500 cfg_rgmii0_txd0_out pr2_pru1_gpo10 r2 rgmii0_txd1 1850 1000 cfg_rgmii0_txd1_out pr2_pru1_gpo9 p3 rgmii0_txd2 2100 1100 cfg_rgmii0_txd2_out pr2_pru1_gpo8 p4 rgmii0_txd3 2200 1000 cfg_rgmii0_txd3_out pr2_pru1_gpo7 n5 uart3_rxd 2000 1600 cfg_uart3_rxd_out pr2_pru1_gpo3 n6 uart3_txd 2000 1000 cfg_uart3_txd_out pr2_pru1_gpo4 324 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset2 direct output mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-198 manual functions mapping for pru-icss2 pru1 ioset2 direct output mode for a definition of the manual modes. table 5-198 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-198. manual functions mapping for pru-icss2 pru1 ioset2 direct output mode ball ball name pr2_pru1_dir_out_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 13 c16 mcasp1_aclkx 200 800 cfg_mcasp1_aclkx_out pr2_pru1_gpo7 d14 mcasp1_axr0 200 1000 cfg_mcasp1_axr0_out pr2_pru1_gpo8 b14 mcasp1_axr1 0 1110 cfg_mcasp1_axr1_out pr2_pru1_gpo9 b16 mcasp1_axr10 0 2500 cfg_mcasp1_axr10_out pr2_pru1_gpo12 b18 mcasp1_axr11 0 1900 cfg_mcasp1_axr11_out pr2_pru1_gpo13 a19 mcasp1_axr12 0 2300 cfg_mcasp1_axr12_out pr2_pru1_gpo14 e17 mcasp1_axr13 200 1200 cfg_mcasp1_axr13_out pr2_pru1_gpo15 e16 mcasp1_axr14 200 1100 cfg_mcasp1_axr14_out pr2_pru1_gpo16 a18 mcasp1_axr8 200 1600 cfg_mcasp1_axr8_out pr2_pru1_gpo10 b17 mcasp1_axr9 0 1900 cfg_mcasp1_axr9_out pr2_pru1_gpo11 d23 mcasp4_axr1 0 700 cfg_mcasp4_axr1_out pr2_pru1_gpo0 ac3 mcasp5_aclkx 1400 4000 cfg_mcasp5_aclkx_out pr2_pru1_gpo1 aa5 mcasp5_axr0 1500 3000 cfg_mcasp5_axr0_out pr2_pru1_gpo3 ac4 mcasp5_axr1 1500 1900 cfg_mcasp5_axr1_out pr2_pru1_gpo4 u6 mcasp5_fsx 1300 2700 cfg_mcasp5_fsx_out pr2_pru1_gpo2 j25 xref_clk0 0 160 cfg_xref_clk0_out pr2_pru1_gpo5 j24 xref_clk1 0 0 cfg_xref_clk1_out pr2_pru1_gpo6 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru0 ioset2 parallel capture mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-199 manual functions mapping for pru-icss2 pru0 ioset2 parallel capture mode for a definition of the manual modes. table 5-199 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-199. manual functions mapping for pru-icss2 pru0 ioset2 parallel capture mode ball ball name pr2_pru0_par_cap_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 12 y5 gpio6_10 4125 481 cfg_gpio6_10_in pr2_pru0_gpi0 y6 gpio6_11 3935 997 cfg_gpio6_11_in pr2_pru0_gpi1 a21 mcasp2_axr2 0 0 cfg_mcasp2_axr2_in pr2_pru0_gpi16 a22 mcasp3_aclkx 571 0 cfg_mcasp3_aclkx_in pr2_pru0_gpi12 b22 mcasp3_axr0 1570 0 cfg_mcasp3_axr0_in pr2_pru0_gpi14 b23 mcasp3_axr1 1405 0 cfg_mcasp3_axr1_in pr2_pru0_gpi15 a23 mcasp3_fsx 1946 0 cfg_mcasp3_fsx_in pr2_pru0_gpi13 y2 mmc3_clk 4093 1066 cfg_mmc3_clk_in pr2_pru0_gpi2 y1 mmc3_cmd 4043 921 cfg_mmc3_cmd_in pr2_pru0_gpi3 y4 mmc3_dat0 4010 864 cfg_mmc3_dat0_in pr2_pru0_gpi4 aa2 mmc3_dat1 3817 1643 cfg_mmc3_dat1_in pr2_pru0_gpi5 325 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-199. manual functions mapping for pru-icss2 pru0 ioset2 parallel capture mode (continued) ball ball name pr2_pru0_par_cap_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 12 aa3 mmc3_dat2 4040 673 cfg_mmc3_dat2_in pr2_pru0_gpi6 w2 mmc3_dat3 3923 1478 cfg_mmc3_dat3_in pr2_pru0_gpi7 y3 mmc3_dat4 4096 729 cfg_mmc3_dat4_in pr2_pru0_gpi8 aa1 mmc3_dat5 3926 1271 cfg_mmc3_dat5_in pr2_pru0_gpi9 aa4 mmc3_dat6 4004 929 cfg_mmc3_dat6_in pr2_pru0_gpi10 ab1 mmc3_dat7 3963 666 cfg_mmc3_dat7_in pr2_pru0_gpi11 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset1 parallel capture mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-200 manual functions mapping for pru-icss2 pru1 ioset1 parallel capture mode for a definition of the manual modes. table 5-200 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. table 5-200. manual functions mapping for pru-icss2 pru1 ioset1 parallel capture mode ball ball name pr2_pru1_par_cap_manual1 cfg register muxmode a_delay (ps) g_delay (ps) 12 p5 rmii_mhz_5 0_clk 1717 0 cfg_rmii_mhz_50_clk_in pr2_pru1_gpi2 l5 mdio_d 2088 0 cfg_mdio_d_in pr2_pru1_gpi1 l6 mdio_mclk 1321 0 cfg_mdio_mclk_in pr2_pru1_gpi0 n2 rgmii0_rxc 1287 0 cfg_rgmii0_rxc_in pr2_pru1_gpi11 p2 rgmii0_rxctl 2456 0 cfg_rgmii0_rxctl_in pr2_pru1_gpi12 n4 rgmii0_rxd0 0 0 cfg_rgmii0_rxd0_in pr2_pru1_gpi16 n3 rgmii0_rxd1 2157 0 cfg_rgmii0_rxd1_in pr2_pru1_gpi15 p1 rgmii0_rxd2 2008 0 cfg_rgmii0_rxd2_in pr2_pru1_gpi14 n1 rgmii0_rxd3 2271 0 cfg_rgmii0_rxd3_in pr2_pru1_gpi13 t4 rgmii0_txc 1851 0 cfg_rgmii0_txc_in pr2_pru1_gpi5 t5 rgmii0_txctl 1875 0 cfg_rgmii0_txctl_in pr2_pru1_gpi6 r1 rgmii0_txd0 1685 0 cfg_rgmii0_txd0_in pr2_pru1_gpi10 r2 rgmii0_txd1 2131 0 cfg_rgmii0_txd1_in pr2_pru1_gpi9 p3 rgmii0_txd2 1734 0 cfg_rgmii0_txd2_in pr2_pru1_gpi8 p4 rgmii0_txd3 1764 0 cfg_rgmii0_txd3_in pr2_pru1_gpi7 n5 uart3_rxd 1654 0 cfg_uart3_rxd_in pr2_pru1_gpi3 n6 uart3_txd 1242 0 cfg_uart3_txd_in pr2_pru1_gpi4 manual io timings modes must be used to guaranteed some io timings for pru-icss2 pru1 ioset2 parallel capture mode. see table 5-29 modes summary for a list of io timings requiring the use of manual io timings modes. see table 5-201 manual functions mapping for pru-icss2 pru1 ioset2 parallel capture mode for a definition of the manual modes. table 5-201 lists the a_delay and g_delay values needed to calculate the correct values to be set in the cfg_x registers. 326 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-201. manual functions mapping for pru-icss2 pru1 ioset2 parallel capture mode ball ball name pr2_pru1_par_cap_manual2 cfg register muxmode a_delay (ps) g_delay (ps) 12 c16 mcasp1_aclkx 1928 0 cfg_mcasp1_aclkx_in pr2_pru1_gpi7 d14 mcasp1_axr0 2413 0 cfg_mcasp1_axr0_in pr2_pru1_gpi8 b14 mcasp1_axr1 2523 25 cfg_mcasp1_axr1_in pr2_pru1_gpi9 b16 mcasp1_axr10 2607 0 cfg_mcasp1_axr10_in pr2_pru1_gpi12 b18 mcasp1_axr11 2669 92 cfg_mcasp1_axr11_in pr2_pru1_gpi13 a19 mcasp1_axr12 2225 0 cfg_mcasp1_axr12_in pr2_pru1_gpi14 e17 mcasp1_axr13 2315 0 cfg_mcasp1_axr13_in pr2_pru1_gpi15 e16 mcasp1_axr14 0 0 cfg_mcasp1_axr14_in pr2_pru1_gpi16 a18 mcasp1_axr8 2201 0 cfg_mcasp1_axr8_in pr2_pru1_gpi10 b17 mcasp1_axr9 2293 278 cfg_mcasp1_axr9_in pr2_pru1_gpi11 d23 mcasp4_axr1 1759 0 cfg_mcasp4_axr1_in pr2_pru1_gpi0 ac3 mcasp5_aclkx 3732 1810 cfg_mcasp5_aclkx_in pr2_pru1_gpi1 aa5 mcasp5_axr0 3776 2255 cfg_mcasp5_axr0_in pr2_pru1_gpi3 ac4 mcasp5_axr1 3886 1923 cfg_mcasp5_axr1_in pr2_pru1_gpi4 u6 mcasp5_fsx 3800 1449 cfg_mcasp5_fsx_in pr2_pru1_gpi2 j25 xref_clk0 1375 21 cfg_xref_clk0_in pr2_pru1_gpi5 j24 xref_clk1 1320 0 cfg_xref_clk1_in pr2_pru1_gpi6 327 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.6.24 system and miscellaneous interfaces the device includes the following system and miscellaneous interfaces: ? sysboot interface ? system dma interface ? interrupt controllers (intc) interface 5.10.7 emulation and debug subsystem the device includes the following test interfaces: ? ieee 1149.1 standard-test-access port (jtag) ? trace port interface unit (tpiu) 5.10.7.1 ieee 1149.1 standard-test-access port (jtag) the jtag (ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture) interface is used for bsdl testing and emulation of the device. the trstn pin only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. for maximum reliability, the device includes an internal pulldown (ipd) on the trstn pin to ensure that trstn is always asserted upon power up and the device's internal emulation logic is always properly initialized. jtag controllers from texas instruments actively drive trstn high. however, some third-party jtag controllers may not drive trstn high but expect the use of a pullup resistor on trstn. when using this type of jtag controller, assert trstn to initialize the device after powerup and externally drive trstn high before attempting any emulation or boundary-scan operations. the main jtag features include: ? 32kb embedded trace buffer (etb) ? 5-pin system trace interface for debug ? supports advanced event triggering (aet) ? all processors can be emulated via jtag ports ? all functions on emu pins of the device: ? emu[1:0] - cross-triggering, boot mode (wir), stm trace ? emu[4:2] - stm trace only (single direction) 5.10.7.1.1 jtag electrical data/timing table 5-202 , table 5-203 and figure 5-130 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-202. timing requirements for ieee 1149.1 jtag no. parameter description min max unit 1 t c(tck) cycle time, tck 62.29 ns 1a t w(tckh) pulse duration, tck high (40% of t c ) 24.92 ns 1b t w(tckl) pulse duration, tck low (40% of t c ) 24.92 ns 3 t su(tdi-tck) input setup time, tdi valid to tck high 6.23 ns t su(tms-tck) input setup time, tms valid to tck high 6.23 ns 4 t h(tck-tdi) input hold time, tdi valid from tck high 31.15 ns t h(tck-tms) input hold time, tms valid from tck high 31.15 ns table 5-203. switching characteristics over recommended operating conditions for ieee 1149.1 jtag no. parameter description min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid 0 30.5 ns 328 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated figure 5-130. jtag timing table 5-204 , table 5-205 and figure 5-131 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-204. timing requirements for ieee 1149.1 jtag with rtck no. parameter description min max unit 1 t c(tck) cycle time, tck 62.29 ns 1a t w(tckh) pulse duration, tck high (40% of t c ) 24.92 ns 1b t w(tckl) pulse duration, tck low (40% of t c ) 24.92 ns 3 t su(tdi-tck) input setup time, tdi valid to tck high 6.23 ns t su(tms-tck) input setup time, tms valid to tck high 6.23 ns 4 t h(tck-tdi) input hold time, tdi valid from tck high 31.15 ns t h(tck-tms) input hold time, tms valid from tck high 31.15 ns table 5-205. switching characteristics over recommended operating conditions for ieee 1149.1 jtag with rtck no. parameter description min max unit 5 t d(tck-rtck) delay time, tck to rtck with no selected subpaths (i.e. icepick is the only tap selected - when the arm is in the scan chain, the delay time is a function of the arm functional clock). 0 27 ns 6 t c(rtck) cycle time, rtck 62.29 ns 7 t w(rtckh) pulse duration, rtck high (40% of t c ) 24.92 ns 8 t w(rtckl) pulse duration, rtck low (40% of t c ) 24.92 ns figure 5-131. jtag with rtck timing 5 6 8 7 tck rtck sprs906_timing_jtag_02 3 tck tdo tdi/tms 2 4 1 1a 1b sprs906_timing_jtag_01 329 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated 5.10.7.2 trace port interface unit (tpiu) caution the i/o timings provided in this section are valid only if signals within a single ioset are used. the iosets are defined in table 5-207 . 5.10.7.2.1 tpiu pll ddr mode table 5-206 and figure 5-132 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 5-206. switching characteristics for tpiu no. parameter description min max unit tpiu1 t c(clk) cycle time, traceclk period 5.56 ns tpiu4 t d(clk-ctlv) skew time, traceclk transition to tracectl transition -1.61 1.98 ns tpiu5 t d(clk-datav) skew time, traceclk transition to tracedata[17:0] -1.61 1.98 ns figure 5-132. tpiu ? pll ddr transmit mode (1) (1) in d[x:0], x is equal to 15 or 17. in table 5-207 are presented the specific groupings of signals (ioset) for use with tpiu signals. table 5-207. tpiu iosets signals ioset1 ioset2 ball mux ball mux emu19 e10 5 emu18 b10 5 emu17 a10 5 emu16 f10 5 emu15 a11 5 emu14 a8 5 emu13 a9 5 emu12 a7 5 emu11 b9 5 emu10 c8 5 emu9 b8 5 emu8 e8 5 emu7 c7 5 emu6 b7 5 traceclk tracectl tracedata[x:0] tpiu4 tpiu4 tpiu2 tpiu1 tpiu3 tpiu5 tpiu5 sprs906_timing_timer_01 330 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 specifications copyright ? 2016 ? 2018, texas instruments incorporated table 5-207. tpiu iosets (continued) signals ioset1 ioset2 ball mux ball mux emu5 d8 5 emu1 c22 0 c22 0 emu0 c21 0 c21 0 331 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6 detailed description 6.1 description the dra71x processor is offered in a 538-ball, 17 17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with via channel ? array (vca) technology, ball grid array (bga) package. the architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the dra75x ("jacinto 6 ep" and "jacinto 6 ex"), dra74x "jacinto 6" and dra72x "jacinto 6 eco" family of infotainment processors , including graphics, voice, hmi, multimedia and smartphone projection mode capabilities. programmability is provided by a single-core arm cortex-a15 risc cpu with neon ? extensions and a ti c66x vliw floating-point dsp core. the arm processor lets developers keep control functions separate from other algorithms programmed on the dsp and coprocessors, thus reducing the complexity of the system software. additionally, ti provides a complete set of development tools for the arm, and dsp, including c compilers and a debugging interface for visibility into source code execution. cryptographic acceleration is available in all devices. all other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on high-security (hs) devices. for more information about hs devices, contact your ti representative. the dra71x jacinto 6 entry processor family is qualified according to the aec-q100 standard. the device features are simplified power supply rail mapping which enables lower cost pmic solutions. 6.2 functional block diagram figure 6-1 is functional block diagram for the device. 332 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated figure 6-1. dra71x block diagram (1x c66x co-processor) mailbox x13 edma high-speed interconnect program/data storage connectivity system (1x arm cortexCa15) iva hd 1080p video co-processor dsp pcie ss x2 medialb (nand/nor/ async) (1x sgx544 3d) vip x1 (dual cortexCm4) intro-001 gpmc / elm 256-kb rom ocmc dra71x gpu mpu ipu1 serial interfaces i2c x6 uart x10 mcspi x4 dcan x2 spinlock gpio x8 timers x16 wdt qspi emif x1 1x 32-bit ddr3/ddr3l sdma vpe mcasp x8 mmu x2 cal csi2 x1 bb2d (gc320 2d) (dual cortexCm4) ipu2 pwm ss x3 hdq kbd gmac avb most150 1x usb 3.0 dual mode fs/hs/ss w/ phy 2x usb 2.0 dual mode fs/hs 1x phy, 1x ulpi radio accelerators vcp x2 hd atl 512-kb ram with ecc dmm mmc / sd x4 pru-icss x2 copyright ? 2016, texas instruments incorporated display subsystem 1xgfx / 3xvid blend / scale hdmi 1.4a lcd3 secure boot debug security tee (hs devices) lcd2 333 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.3 mpu the cortex ? -a15 microprocessor unit (mpu) subsystem serves the applications processing role by running the high-level operating system (hlos) and application code. the mpu subsystem incorporates one cortex-a15 mpu core (mpu_c0), individual level 1 (l1) caches, level 2 (l2) cache (mpu_l2cache) shared between them, and various other shared peripherals. to aid software development, the processor core can be kept cache-coherent with the l2 cache. the mpu subsystem provides a high-performance computing platform with high peak-computing performance and low memory latency. the arm subsystem supports the following key features: 334 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? arm ? cortex-a15 mp core ? (mpu_cluster) ? one cortex-a15 mpu core (revision r2p2) which has the following features: ? superscalar, dynamic multi-issue technology ? out-of-order (ooo) instruction dispatch and completion ? dynamic branch prediction with branch target buffer (btb), global history buffer (ghb), and 48-entry return stack ? continuous fetch and decoding of three instructions per clock cycle ? dispatch of up to four instructions and completion of eight instructions per clock cycle ? provides optimal performance from binaries compiled for previous arm processors ? five execution units handle simple instructions, branch instructions, neon ? and floating point instructions, multiply instructions, and load and store instructions. ? simple instructions take two cycles from dispatch, while complex instructions take up to 11 cycles. ? can issue two simple instructions in a cycle ? can issue a load and a store instruction in the same cycle ? integrated neon processing engine to include the arm neon advanced simd (single instruction, multiple data) support for accelerated media and signal processing computation ? includes vfpv4-compatible hardware to support single- and double-precision add, subtract, divide, multiply and accumulate, and square root operations ? extensive support to accelerate virtualization using a hypervisor ? 32-kib l1 instruction (l1i) and 32-kib l1 data (l1d) cache: ? 64-byte line size ? 2-way set associative ? memory management unit (mmu): ? two-level translation lookaside buffer (tlb) organization ? first level is an 32-entry, fully associative micro-tlb implemented for each of instruction fetch, load, and store. ? second level is a unified, 4-way associative, 512-entry main tlb ? supports hardware tlb table-walk for backward-compatible and new 64-bit entry page table formats ? new page table format can produce 40-bit physical addresses ? two-stage translation where first stage is hlos-controlled and the second level may be controlled by a hypervisor. second stage always uses the new page table format ? integrated l2 cache (mpu_l2cache) and snoop control unit (scu): ? 1-mib of unified (instructions and data) cache organized as 16 ways of 1024 sets of 64-byte lines ? redundant l1 data (cache) tags to perform snoop filtering (l1 instruction cache tags are not duplicated) ? operates at cortex-a15 mpu core clock rate ? integrated l2 cache controller (mpu_l2cache_ctrl): ? sixteen 64-byte line buffers that handle evictions, line fills and snoop transfers ? one 128-bit amba4 coherent bus (axi4-ace) port ? auto-prefetch buffer for up to 16 streams and detecting forward and backward strides ? generalized interrupt controller (gic, also referred to as mpu_intc): an interrupt controller supplied by arm. the single gic in the mpu_cluster routes interrupts to the mpu core. the gic supports: ? number of shared peripheral interrupts (spi): 160 ? number of software generated interrupts (sgi): 16 ? number of cpu interfaces: 1 335 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? virtual cpu interface for virtualization support. this allows the majority of guest operating system (os) interactions with the gic to be handled in hardware, but with physical interrupts still requiring hypervisor intervention to assign them to the appropriate virtual machine. ? integrated timer counter and one timer block ? arm coresight ? debug and trace modules. for more information, see chapter on-chip debug support of the device trm.. ? mpu_axi2ocp bridge (local interconnect): ? connected to memory adapter (mpu_ma), which routes the non-emif address space transactions to mpu_axi2ocp ? single request multiple data (srmd) protocol on l3_main port ? multiple targets: ? 64-bit port to the l3_main interconnect. interface frequency is 1/4 or 1/8 of core frequency ? mpu_rom ? internal mpu subsystem peripheral targets, including memory adapter lisa section manager (ma_lsm), wake-up generator (mpu_wugen), watchdog timer (mpu_wd_timer), and local prcm module (mpu_prcm) configuration ? internal axi target, coresight system trace module (cs_stm) ? memory adapter (mpu_ma): helps decrease the latency of accesses between the mpu_l2cache and the external memory interface (emif1) by providing a direct path between the mpu subsystem and emif1: ? connected to 128-bit amba4 interface of mpu_cluster ? direct 128-bit interface to emif1 ? interface speed between mpu_cluster and mpu_ma is at half-speed of the mpu core frequency ? quarter-speed interface to emif ? uses firewall logic to check access rights of incoming addresses ? local prcm (mpu_prcm): ? handles mpu_c0 power domain ? supports sr3-apg (smartreflex3 automatic power gating) power management technology inside the mpu_cluster ? mpu subsystem has five power domains ? wake-up generator (mpu_wugen) ? responsible for waking up the mpu core ? standby controller: handles the power transitions inside the mpu subsystem ? realtime (master) counter (counter_realtime): produces the count used by the private timer peripheral in the mpu_cluster ? watchdog timer (mpu_wd_timer): used to generate a chip-level watchdog reset request to global prcm ? on-chip boot rom (mpu_rom): the mpu_rom size is 48-kib, and the address range is from 0x4003 8000 to 0x4004 3fff. for more information about booting from this memory, see chapter initialization of the device trm.. 336 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? interfaces: ? 128-bit interface to emif1 ? 64-bit master port to the l3_main interconnect ? 32-bit slave port from the l4_cfg_emu interconnect (debug subsystem) for configuration of the mpu subsystem debug modules ? 32-bit slave port from the l4_cfg interconnect for memory adapter firewall (mpu_ma_nttp_fw) configuration ? 32-bit atb output for transmitting debug and trace data ? 160 peripheral interrupt inputs for more information, see section arm cortex-a15 subsystem in chapter processors and accelerators of the device trm. 6.4 dsp subsystem the device includes a single instance (dsp1) of a digital signal processor (dsp) subsystem, based on the ti's standard tms320c66x ? dsp corepac core. the tms320c66x dsp core enhances the tms320c674x ? core, which merges the c674x ? floating point and the c64x+ ? fixed-point instruction set architectures. the c66x dsp is object-code compatible with the c64x+/c674x dsps. for more information on the tms320c66x core cpu, see the tms320c66x dsp cpu and instruction set reference guide , ( sprugh7 ). the dsp subsystem integrated in the device includes the following components: ? a tms320c66x ? corepac dsp core that encompasses: ? l1 program-dedicated (l1p) cacheable memory ? l1 data-dedicated (l1d) cacheable memory ? l2 (program and data) cacheable memory ? extended memory controller (xmc) ? external memory controller (emc) ? dsp corepac located interrupt controller (intc) ? dsp corepac located power-down controller (pdc) ? dedicated enhanced data memory access engine - edma, to transfer data from/to memories and peripherals external to the dsp subsystem and to local dsp memory (most commonly l2 sram). the external dma requests are passed through dsp system level (sys) wakeup logic, and collected from the dsp1 dedicated outputs of the device dma events crossbar for the subsystem. ? a level 2 (l2) interconnect network (dsp noc) to allow connectivity between different modules of the subsystem or the remainder of the device via the device l3_main interconnect. ? two memory management units (on edma l2 interconnect and dsp mdma paths) for accessing the device l3_main interconnect address space ? dedicated system control logic (dsp_system) responsible for power management, clock generation, and connection to the device power, reset, and clock management (prcm) module the tms320c66x instruction set architecture ( isa ? ) is the latest for the c6000 family. as with its predecessors (c64x, c64x+ and c674x), the c66x is an advanced vliw architecture with 8 functional units (two multiplier units and six arithmetic logic units) that operate in parallel. the c66x cpu has a total of 64 general-purpose 32-bit registers. some features of the dsp c6000 family devices are: ? advanced vliw cpu with eight functional units (two multipliers and six alus) which: ? executes up to eight instructions per cycle for up to ten times the performance of typical dsps ? allows designers to develop highly effective risc-like code for fast development time 337 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? instruction packing ? gives code size equivalence for eight instructions executed serially or in parallel ? reduces code size, program fetches, and power consumption ? conditional execution of most instructions ? reduces costly branching ? increases parallelism for higher sustained performance ? efficient code execution on independent functional units ? industry's most efficient c compiler on dsp benchmark suite ? industry's first assembly optimizer for fast development and improved parallelization ? 8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications ? 40-bit arithmetic options which add extra precision for vocoders and other computationally intensive applications ? saturation and normalization to provide support for key arithmetic operations ? field manipulation and instruction extract, set, clear, and bit counting support common operation found in control and data manipulation applications. the c66x cpu has the following additional features: ? each multiplier can perform two 16 16-bit or four 8 8 bit multiplies every clock cycle. ? quad 8-bit and dual 16-bit instruction set extensions with data flow support ? support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses ? special communication-specific instructions have been added to address common operations in error- correcting codes. ? bit count and rotate hardware extends support for bit-level algorithms. ? compact instructions: common instructions (and, add, ld, mpy) have 16-bit versions to reduce code size. ? protected mode operation: a two-level system of privileged program execution to support higher- capability operating systems and system features such as memory protection. ? exceptions support for error detection and program redirection to provide robust code execution ? hardware support for modulo loop operation to reduce code size and allow interrupts during fully- pipelined code ? each multiplier can perform 32 32 bit multiplies ? additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts per clock cycle the tms320c66x has the following key improvements to the isa: ? 4x multiply accumulate improvement for both fixed and floating point ? improvement of the floating point arithmetic ? enhancement of the vector processing capability for fixed and floating point ? addition of domain-specific instructions for complex arithmetic and matrix operations on the c66x isa, the vector processing capability is improved by extending the width of the simd instructions. the c674x dsp supports 2-way simd operations for 16-bit data and 4-way simd operations for 8-bit data. c66x enhances this capabilities with the addition of simd instructions for 32-bit data allowing operation on 128-bit vectors. for example the qmpy32 instruction is able to perform the element to element multiplication between two vectors of four 32-bit data each. c66x isa includes a set of specific instructions to handle complex arithmetic and matrix operations. 338 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? tms320c66x dsp corepac memory components: ? a 32-kib l1 program memory (l1p) configurable as cache and/or sram: ? when configured as a cache, the l1p is a 1-way set-associative cache with a 32-byte cache line ? the dsp corepac l1p memory controller provides bandwidth management, memory protection, and power-down functions ? the l1p is capable of cache block and global coherence operations ? the l1p controller has an error detection (ed) mechanism, including necessary sram ? the l1p memory can be fully configured as a cache or sram ? page size for l1p memory is 2kb ? a 32-kib l1 data memory (l1d) configurable as cache and / or sram: ? when configured as a cache, the l1d is a 2-way set-associative cache with a 64-byte cache line ? the dsp corepac l1d memory controller provides bandwidth management, memory protection, and power-down functions ? the l1d memory can be fully configured as a cache or sram ? no support for error correction or detection ? page size for l1d memory is 2kb ? a 288-kib (program and data) l2 memory, only part of which is cacheable: ? when configured as a cache, the l2 memory is a 4-way set associative cache with a 128-byte cache line ? only 256 kib of l2 memory can be configured as cache or sram ? 32 kib of the l2 memory is always mapped as sram ? the l2 memory controller has an error correction code (ecc) and ed mechanism, including necessary sram ? the l2 memory controller supports hardware prefetching and also provides bandwidth management, memory protection, and power-down functions. ? page size for l2 memory is 16kb ? the external memory controller (emc) is a bridge from the c66x corepac to the rest of the dsp subsystem and device. it has : ? a 32-bit configuration port (cfg) providing access to local subsystem resources (like dsp_edma, dsp_system, and so forth) or to l3_main resources accessible via the cfg address range. ? a 128-bit slave-dma port (sdma) which provides accesses of system masters outside the dsp subsystem to resources inside the dsp subsystem or c66x dsp corepac memories, i.e. when the dsp subsystem is the slave in a transaction. ? the extended memory controller (xmc) processes requests from the l2 cache controller (which are a result of cpu instruction fetches, load/store commands, cache operations) to device resources via the c66x dsp corepac 128-bit master dma (mdma) port: ? memory protection for addresses outside c66x dsp corepac generated over device l3_main on the mdma port ? prefetch, multi-in-flight requests ? a dsp local interrupt controller (intc) in the dsp c66x corepac, interfaces the system events to the dsp c66x core cpu interrupt and exceptions inputs. the dsp subsystem c66x corepac interrupt controller supports up to 128 system events of which 64 interrupts are external to dsp subsystem, collected from the dsp1 dedicated outputs of the device interrupt crossbar. 339 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? local enhanced direct memory access (edma) controller features: ? channel controller (cc) : 64-channel, 128 param, 2 queues ? 2 x third-party transfer controllers (tptc0 and tptc1): ? each tc has a 128-bit read port and a 128-bit write port ? 2kib fifos on each tptc ? 1-dimensional/2-dimensional (1d/2d) addressing ? chaining capability ? dsp subsystem integrated mmus : ? two mmus are integrated: ? the mmu0 is located between dsp mdma master port and the device l3_main interconnect and can be optionally bypassed ? the mmu1 is located between the edma master port and the device l3_main interconnect ? a dsp local power-down controller (pdc) is responsible to power-down various parts of the dsp c66x corepac, or the entire dsp c66x corepac. ? the dsp subsystem system control logic provides: ? slave idle and master standby protocols with device prcm for powerdown ? ocp disconnect handshake for init and target busses ? asynchronous reset ? power-down modes: ? "clockstop" mode featuring wake-up on interrupt event. the dma event wake-up is managed in software. ? the device dsp subsystem is supplied by a prcm dpll, but dsp1 has integrated its own pll module outside the c66x corepac for clock gating and division. ? the device dsp subsystem has following port instances to connect to remaining part of the device. see also : ? a 128-bit initiator (dsp mdma master) port for mdma/cache requests ? a 128-bit initiator (dsp edma master) port for edma requests ? a 32-bit initiator (dsp cfg master) port for configuration requests ? a 128-bit target (dsp slave) port for requests to dsp memories and various peripherals ? c66x dsp subsystem (dspss) safety aspects : ? above mentioned memory ecc/ed mechanisms ? mmus enable mapping of only the necessary application space to the processor ? memory protection units internal to the dspss (in l1p, l1d and l2 memory controllers) and external to dspss (firewalls) to help define legal accesses and raise exceptions on illegal accesses ? exceptions: memory errors, various dsp errors, mmu errors and some system errors are detected and cause exceptions. the exceptions could be handled by the dsp or by a designated safety processor at the chip level. note that it may not be possible for the safety processor to completely handle some exceptions unsupported features on the c66x dsp core for the device are: ? the extended memory controller mpax (memory protection and address extension) 36-bit addressing is not supported known dsp subsystem powermode restrictions for the device are: ? "full logic / ram retention" mode featuring wake-up on both interrupt or dma event (logic in ? always on ? domain). only off mode is supported by dsp subsystem, requiring full boot. 340 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated fore more information about: ? c66x debug/trace support, see chapter on-chip debug of the device trm. 6.5 iva the iva supports resolutions up to 1080 p/i with full performance of 60 fps (or 120 fields), achievable for encode or decode only (not for simultaneous encode and decode). the iva subsystem is composed of: ? a primary sequencer, including its memories and an imaging controller: icont1 ? a video direct memory access (vdma) processor, which can be used as a secondary sequencer: icont2 ? a vdma engine: dma_iva ? an entropy codec: ecd3 ? a motion compensation engine: mc3 ? a transform and quantization calculation engine: calc3 ? a loop filter acceleration engine: ilf3 ? a motion estimation acceleration engine: ime3 ? an intraprediction estimation engine: ipe3 ? shared level 2 (l2) interface and memory ? local interconnect (l4_iva) ? a message interface for communication between syncboxes ? mailbox ? a debug module for trace event and software instrumentation: smset note the iva allows execution of compliant codecs through the software development kit (sdk). refer to the sdk documentation for details. for more information, see chapter iva subsystem of the device trm. 6.6 ipu the device instantiates two dual cortex ? -m4 image processor unit (ipu) subsystems : ? ipu1 subsystem is available for general purpose usage ? ipu2 subsystem is dedicated to iva support and is not available for other processing note the two ipu subsystems are identical from functional point of view. thus, a unified name ipux shall be used throughout the chapter for simplification. each ipu subsystem contains two arm ? cortex-m4 processors (ipux_c0 and ipux_c1) that share a common level 1 (l1) cache (called unicache [ipux_unicache]). the two cortex-m4 cores are completely homogeneous to one another. any task possible using one cortex-m4 core is also possible using the other cortex-m4 core. it is software responsibility to distribute the various tasks between each cortex-m4 core for optimal performance. the integrated interrupt handling of the ipux subsystem allows it to function as an efficient control unit. each ipu subsystem integrates the following: 341 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? two arm cortex-m4 microprocessors (ipux_c0 and ipux_c1): ? armv7-m and thumb ? -2 instruction set architecture (isa) ? armv6 simd and digital signal processor (dsp) extensions ? single-cycle mac ? integrated nested vector interrupt controller (nvic) (also called ipux_cx_intc, where x = 0, 1) ? integrated bus matrix ? registers: ? thirteen general-purpose 32-bit registers ? link register (lr) ? program counter (pc) ? program status register, xpsr ? two banked sp registers ? integrated power management ? extensive debug capabilities ? unicache interface: ? instruction and data interface ? supports paralleled accesses ? level 2 (l2) master interface (mif) splitter for access to memory or configuration port ? configuration port: used for unicache maintenance and unicache memory management unit (ipux_unicache_mmu) configuration ? unicache: ? 32 kib divided into 16 banks ? 4-way ? cache configuration lock/freeze/preload ? internal mmu: ? 16-entry region-based address translation ? read/write control and access type control ? execute never (xn) mmu protection policy ? little-endian format ? subsystem counter timer module (ipux_unicache_sctm, or just sctm) ? on-chip rom (ipux_rom) and banked ram (ipux_ram) memory ? emulation/debug: emulation feature embedded in cortex-m4 ? l2 mmu (ipux_mmu): 32 entries with table walking logic ? wake-up generator (ipux_wugen): generates wake-up request from external interrupts ? power management: ? local power-management control: configurable through the ipux_wugen registers. ? three sleep modes supported, controlled by the local power-management module. ? ipux is clock-gated in all sleep modes. ? ipux_cx_intc interrupt interface stays awake. for more information, see chapter dual cortex-m4 ipu subsystem of the device trm. 6.7 gpu the 3d graphics processing unit (gpu) accelerates 2-dimensional (2d) and 3-dimensional (3d) graphics and compute applications. it is based on the powervr ? sgx544-mp subsystem from imagination technologies. 342 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated sgx is a new generation of programmable powervr graphics and video processing subsystems. the powervr sgx is a scalable architecture which efficiently processes a number of differing multimedia data types concurrently: ? pixel data ? vertex data ? general purpose processing ? api support for industry standards: ? opengl ? - es 1.1 and 2.0 ? opencl ? -ep 1.1 ? direct3d ? feature level 9.3 ? single-core gpu architecture: ? 1 sgx544 core ? system level cache of 64 kib ? tile-based deferred rendering architecture: ? reduces external bandwidth to sdram ? universal scalable shader engine (usse ? ): ? multithreaded engine incorporating vertex and pixel shader functionality ? automatic load balancing of vertex and pixel processing tasks ? present and texture load accelerator (ptla): ? enables to move, rotate, twiddle, and scale texture surfaces ? supports rgb, argb, yuv4:2:2, and yuv4:2:0 surface formats ? supports bilinear upscale ? supports source color key ? fully virtualized memory addressing for operating system (os) in a unified memory architecture: ? memory management unit (mmu) ? up to 4-gib virtual address space the 3d-gpu subsystem generates a single (aggregate) interrupt connected to the device interrupt crossbar. this allows for this interrupt to be programmatically mapped to multiple device host interrupt controllers. ? texture support: ? cube map ? projected textures ? non-square textures ? texture formats: ? rgba 8888, 565, 1555, and 1565 ? monochromatic 8, 16, 16f, 32f, and 32int ? dual channel, 8:8, 16:16, and 16f:16f ? compressed textures: ? pvrtc-i 2 bpp ? pvrtc-i 4 bpp ? pvrtc-ii 2 bpp ? pvrtc-ii 4 bpp ? etc1 ? dxt 1-5 and bc 4-5 ? programmable support for yuv formats: ? programmable matrix in hardware, coefficients on 12 bits ? yuv4:2:2, yuv4:2:0, two planes (nv12 or nv21); yuv4:2:0, three planes 343 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? resolution support: ? frame buffer maximum = 4096 4096 ? texture maximum size = 4096 4096 ? texture filtering: ? bilinear, trilinear ? independent minimum and mag control ? anti-aliasing: ? 4 multisampling ? programmable sample positions for more information, see chapter 3d graphics accelerator of the device trm. 6.8 bb2d the 2d graphics accelerator subsystem accelerates 2d graphics applications. the 2d graphics accelerator subsystem is based on the gc320 2d gpu core from vivante corporation. the hardware acceleration is brought to numerous 2d applications, including on-screen display and touch screen user interfaces, graphical user interfaces (guis) and menu displays, flash animation, and gaming. ? api support: ? openwf ? , directfb ? gdi/directdraw ? ? flash ? bb2d architecture: ? bitblt and stretchblt ? directfb hardware acceleration ? rop2, rop3, rop4 full alpha blending and transparency ? clipping rectangle support ? alpha blending includes java ? 2 porter-duff compositing rules ? 90-, 180-, 270-degree rotation on every primitive ? yuv-to-rgb color space conversion ? programmable display format conversion with 14 source and 7 destination formats ? high-quality 9-tap, 32-phase filter for image and video scaling at 1080p ? monochrome expansion for text rendering ? 32 k 32 k coordinate system ? hardware acceleration for directfb : ? high-speed video scaler ? rop2/3/4 ? rectangle filling and drawing ? line drawing ? simple blitting ? stretch blitting ? blending with alpha channel (per-pixel alpha) ? blending with alpha factor (alpha modulation) ? nine source and destination blending functions ? porter-duff rules support ? premultiplied alpha support ? colorized blitting (color modulation) ? source color keying ? destination color keying 344 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated the device bb2d generates a single (aggregate) interrupt request connected to the device interrupt crossbar. this allows for this interrupt to be programmatically mapped to multiple device host interrupt controllers. for more information, see chapter 2d graphics accelerator of the device trm. 6.9 pru-icss the device programmable real-time unit and industrial communication subsystem (pru-icss) consists of dual 32-bit load / store risc cpu cores - programmable real-time units (pru0 and pru1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller (pru-icss_intc). the programmable nature of the prus, along with their access to pins, events and all soc resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on- chip (soc). the each pru-icss includes the following main features: ? 21x enhanced gpis (egpis) and 21x enhanced gpos (egpos) with asynchronous capture and serial support per each pru cpu core ? one ethernet mii_rt module (pru-icss_mii_rt) with two mii ports and configurable connections to prus ? 1 mdio port (pru-icss_mii_mdio) ? one industrial ethernet peripheral (iep) to manage/generate industrial ethernet functions ? 1 x 16550-compatible uart with a dedicated 192 mhz clock to support 12mbps profibus ? 1 industrial ethernet timer with 7/9 capture and 8 compare events ? 1 enhanced capture module (ecap) ? 1 interrupt controller (pru-icss_intc) ? a flexible power management support ? integrated switched central resource with programmable priority ? parity control supported by all memories for more information, see chapter programmable real-time unit subsystem and industrial communication subsystem (pru-icss) of the device trm. 345 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.10 memory subsystem 6.10.1 emif the emif module provides connectivity between ddr memory types and manages data bus read/write accesses between external memory and device subsystems which have master access to the l3_main interconnect and dma capability. the emif module has the following capabilities: ? supports jedec standard-compliant ddr3/ddr3l-sdram memory types ? 2-gib sdram address range over one chip-select. this range is configurable through the dynamic memory manager (dmm) module ? supports sdram devices with one, two, four or eight internal banks ? supports sdram devices with single or dual die packages ? data bus widths: ? 128-bit l3_main (system) interconnect data bus width ? 128-bit port for direct connection with mpu subsystem ? 32-bit sdram data bus width ? 16-bit sdram data bus width used in narrow mode ? supported cas latencies: ? ddr3: 5, 6, 7, 8, 9, 10 and 11 ? supports 256-, 512-, 1024-, and 2048-word page sizes ? supported burst length: 8 ? supports sequential burst type ? sdram auto initialization from reset or configuration change ? supports self refresh and power-down modes for low power ? partial array self-refresh mode for low power. ? output impedance (zq) calibration for ddr3 ? supports on-die termination (odt) ddr3 ? supports prioritized refresh ? programmable sdram refresh rate and backlog counter ? programmable sdram timing parameters ? write and read leveling/calibration and data eye training for ddr3. the emif module does not support: ? burst chop for ddr3 ? interleave burst type ? auto precharge because of better bank interleaving performance ? dll disabling from emif side ? sdram devices with more than one die, or topologies which require more than one chip select on a single emif channel for more information, see section ddr external memory interface (emif) in chapter memory subsystem of the device trm. 6.10.2 gpmc the general purpose memory controller (gpmc) is an external memory controller of the device. its data access engine provides a flexible programming model for communication with all standard memories. the gpmc supports the following various access types: ? asynchronous read/write access 346 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? asynchronous read page access (4, 8, and 16 word16) ? synchronous read/write access ? synchronous read/write burst access without wrap capability (4, 8 and 16 word16) ? synchronous read/write burst access with wrap capability (4, 8 and 16 word16) ? address-data-multiplexed (ad) access ? address-address-data (aad) multiplexed access ? little- and big-endian access the gpmc can communicate with a wide range of external devices: ? external asynchronous or synchronous 8-bit wide memory or device (non burst device) ? external asynchronous or synchronous 16-bit wide memory or device ? external 16-bit non-multiplexed nor flash device ? external 16-bit address and data multiplexed nor flash device ? external 8-bit and 16-bit nand flash device ? external 16-bit pseudo-sram (psram) device the main features of the gpmc are: ? 8- or 16-bit-wide data path to external memory device ? supports up to eight cs regions of programmable size and programmable base addresses in a total address space of 1 gib ? supports transactions controlled by a firewall ? on-the-fly error code detection using the bose-chaudhuri-hocquenghem (bch) (t = 4, 8, or 16) or hamming code to improve the reliability of nand with a minimum effect on software (nand flash with 512-byte page size or greater) ? fully pipelined operation for optimal memory bandwidth use ? the clock to the external memory is provided from gpmc functional clock divided by 1, 2, 3, or 4 ? supports programmable autoclock gating when no access is detected ? independent and programmable control signal timing parameters for setup and hold time on a per-chip basis. parameters are set according to the memory device timing parameters, with a timing granularity of one gpmc functional clock cycle. ? flexible internal access time control (wait state) and flexible handshake mode using external wait pin monitoring ? support bus keeping ? support bus turnaround ? prefetch and write posting engine associated with to achieve full performance from the nand device with minimum effect on nor/sram concurrent access for more information, see section general-purpose memory controller (gpmc) in chapter memory subsystem of the device trm. 6.10.3 elm in the case of nand modules with no internal correction capability, sometimes referred to as bare nand, the correction process can be delegated to the error location module (elm) used in conjunction with the gpmc. the elm supports the following features: ? 4, 8, and 16 bits per 512-byte block error location based on bch algorithm ? eight simultaneous processing contexts ? page-based and continuous modes 347 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? interrupt generation when error location process completes: ? when the full page has been processed in page mode ? for each syndrome polynomial (checksum-like information) in continuous mode for more information, see section error location module (elm) in chapter memory subsystem of the device trm. 6.10.4 ocmc there is one on-chip memory controller (ocmc) in the device. the ocm controller supports the following features: ? l3_main data interface: ? used for maximum throughput performance ? 128-bit data bus width ? burst supported ? l4 interface (ocmc_ram only): ? used for access to configuration registers ? 32-bit data bus width ? only single accesses supported ? the l4 associated ocmc clock is two times lower than the l3 associated ocmc clock ? error correction and detection: ? single error correction and dual error detection ? 9-bit hamming error correction code (ecc) calculated on 128-bit data word which is concatenated with memory address bits ? hamming distance of 4 ? enable/disable mode control through a dedicated register ? single bit error correction on a read transaction ? exclusion of repeated addresses from correctable error address trace history ? ecc valid for all write transactions to an enabled region ? sub-128-bit writes supported via read modify write ? ecc error status reporting: ? trace history buffer (fifo) with depth of 4 for corrected error address ? trace history buffer with depth of 4 for non correctable error address and also including double error detection ? interrupt generation for correctable and uncorrectable detected errors ? ecc diagnostics configuration: ? counters for single error correction (sec), double error detection (ded) and address error events (aee) ? programmable threshold registers for exeptions associated with sec, ded and aee counters ? register control for enabling and disabling of diagnostics ? configuration registers and ecc status accessible through l4 interconnect ? circular buffer for sliced based vip frame transfers: ? up to 12 programmable circular buffers mapped with unique virtual frame addresses ? on the fly (with no additional latency) address translation from virtual to ocmc circular buffer memory space ? virtual frame size up to 8 mib and circular buffer size up to 1 mib ? error handling and reporting of illegal cbuf addressing ? underflow and overflow status reporting and error handling ? last access read/write address history 348 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? two interrupt outputs configured independently to service either ecc or cbuf interrupt events the ocm controller does not have a memory protection logic and does not support endianism conversion. for more information, see section on-chip memory (ocm) in chapter memory subsystem of the device trm. 6.11 interprocessor communication 6.11.1 mailbox communication between the on-chip processors of the device uses a queued mailbox-interrupt mechanism. the queued mailbox-interrupt mechanism allows the software to establish a communication channel between two processors through a set of registers and associated interrupt signals by sending and receiving messages (mailboxes). the device implements the following mailbox types: ? system mailbox: ? number of instances: 13 ? used for communication between: mpu, dsp1, ipu1, and ipu2 subsystems ? reference name: mailbox(1..13) ? iva mailbox: ? number of instances: 1 ? used for communication between: iva local user (icont1, or icont2) and three external users (selected among mpu, dsp1, ipu1, and ipu2 subsystems) ? reference name: iva_mbox each mailbox module supports the following features: ? parameters configurable at design time ? number of users ? number of mailbox message queues ? number of messages (fifo depth) for each message queue ? 32-bit message width ? message reception and queue-not-full notification using interrupts ? support of 16-/32-bit addressing scheme ? power management support for more information, see chapter mailbox of the device trm. 6.11.2 spinlock the spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device: ? cortex ? -a15 microprocessor unit (mpu) subsystem ? digital signal processor (dsp) subsystem ? dsp1 ? dual cortex-m4 image processing unit (ipu) subsystems ? ipu1 and ipu2 the spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need of a readmodify- write bus transfer that the programmable cores are not capable of. for more information, see chapter spinlock module of the device trm. 6.12 interrupt controller 349 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated the device has a large number of interrupts to service the needs of its many peripherals and subsystems. the mpu, dsp, and ipu (x2) subsystems are capable of servicing these interrupts via their integrated interrupt controllers. in addition, each processor's interrupt controller is preceded by an interrupt controller crossbar (irq_crossbar) that provides flexibility in mapping the device interrupts to processor interrupt inputs. for more information about irq crossbar, see chapter control module of the device trm. cortex ? -a15 mpu subsystem interrupt controller (mpu_intc) the mpu_intc module (also called generalized interrupt controller [gic]) is a single functional unit that is integrated in the arm ? cortex-a15 multiprocessor core (mpcore) alongside cortex-a15 processor. it provides: ? 160 hardware interrupt inputs ? generation of interrupts by software ? prioritization of interrupts ? masking of any interrupts ? distribution of the interrupts to the target cortex-a15 processor(s) ? tracking the status of interrupts the cortex-a15 processor supports three main groups of interrupt sources, with each interrupt source having a unique id: ? software generated interrupts (sgis): sgis are generated by writing to the cortex-a15 software generated interrupt register (gicd_sgir). a maximum of 16 sgis (id0 ? id15) can be generated for the cpu interface. an sgi has edge-triggered properties. the software triggering of the interrupt is equivalent to the edge transition of the interrupt signal on a peripheral input. ? private peripheral interrupts (ppis): a ppi is an interrupt generated by a peripheral that is specific to the processor. although interrupts id16 ? id31 are dedicated to ppis in general, only seven ppis are actually used for the cpu interface (id25 ? id31). interrupts id16 ? id24 are reserved (not used). ? shared peripheral interrupts (spis): spis are triggered by events generated on associated interrupt input lines. in this device, the gic is configured to support 160 spis corresponding to its external irqs[159:0] signals. for detailed information about this module and description of sgis and ppis, see the arm cortex-a15 mpcore technical reference manual (available at infocenter.arm.com/help/index.jsp ). c66x dsp subsystem interrupt controller (dsp1_intc) the dsp1 subsystem integrates an interrupt controller - dsp1_intc, which interfaces the system events to the c66x core interrupt and exceptions inputs. it combines up to 128 interrupts into 12 prioritized interrupts presented to the c66x cpu. for detailed information about this module, see chapter dsp subsystem of the device trm. dual cortex-m4 ipu subsystem interrupt controller (ipux_cx_intc, where x = 1, 2) there are two image processing unit (ipu) subsystems in the device - ipu1, and ipu2. each ipu subsystem integrates two arm cortex-m4 cores. a nested vectored interrupt controller (nvic) is integrated within each cortex-m4. the interrupt mapping is the same (per ipu) for the two cores to facilitate parallel processing. the nvic supports: ? 64 external interrupts (in addition to 16 cortex-m4 internal interrupts), which are dynamically prioritized with 16 levels of priority defined for each core ? low-latency exception and interrupt handling ? prioritization and handling of exceptions ? control of the local power management ? debug accesses to the processor core 350 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated for detailed information about this module, refer to arm cortex-m4 technical reference manual (available at infocenter.arm.com/help/index.jsp ). 6.13 edma the primary purpose of the enhanced direct memory access (edma) controller is to service user- programmed data transfers between two memory-mapped slave endpoints on the device. typical usage of the edma controller includes: ? servicing software-driven paging transfers (for example, data movement between external memory [such as sdram] and internal memory [such as dsp l2 sram]) ? servicing event-driven peripherals, such as a serial port ? performing sorting or sub-frame extraction of various data structures ? offloading data transfers from the main device cpus, such as the c66x dsp corepac or the arm corepac the edma controller consists of two major principle blocks: ? edma channel controller ? edma transfer controller(s) the edma channel controller (edmacc) serves as the user interface for the edma controller. the edmacc includes parameter ram (param), channel control registers, and interrupt control registers. the edmacc serves to prioritize incoming software requests or events from peripherals and submits transfer requests (tr) to the edma transfer controller. the edma transfer controller (edmatc) is responsible for data movement. the transfer request packets (trp) submitted by the edmacc contain the transfer context, based on which the transfer controller issues read/write commands to the source and destination addresses programmed for a given transfer. there are two edma controllers present on this device: ? edma_0, integrating: ? 1 channel controller, referenced as: edmacc_0 ? 2 transfer controllers, referenced as: edmacc_0_tc_0 (or edmatc_0) and edmacc_0_tc_1 (or edmatc_1) ? edma_1, integrating: ? 1 channel controller, referenced as: edmacc_1 ? 2 transfer controllers, referenced as: edmacc_1_tc_0 (or edmatc_2) and edmacc_1_tc_1 (or edmatc_3) the two edma channel controllers (edmacc_0 and edmacc_1) are functionally identical. for simplification, the unified name edmacc shall be regularly used throughout this chapter when referring to edma channel controllers functionality and features. the four edma transfer controllers (edmacc_0_tc_0, edmacc_0_tc_1, edmacc_1_tc_0 and edmacc_1_tc_1) are functionally identical. for simplification, the unified name edmatc shall be regularly used throughout this chapter when referring to edma transfer controllers functionality and features. each edmacc has the following features: ? fully orthogonal transfer description ? 3 transfer dimensions: ? array (multiple bytes) ? frame (multiple arrays) ? block (multiple frames) ? single event can trigger transfer of array, frame, or entire block ? independent indexes on source and destination 351 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? flexible transfer definition ? increment or constant addressing modes ? linking mechanism allows automatic param set update ? chaining allows multiple transfers to execute with one event ? 64 dma channels ? channels triggered by either: ? event synchronization ? manual synchronization (cpu write to event set register) ? chain synchronization (completion of one transfer triggers another transfer) ? support for programmable dma channel to param mapping ? 8 quick dma (qdma) channels ? qdma channels are triggered automatically upon writing to param set entry ? support for programmable qdma channel to param mapping ? 512 param sets ? each param set can be used for a dma channel, qdma channel, or link set ? 2 transfer controllers/event queues ? 16 event entries per event queue ? interrupt generation based on: ? transfer completion ? error conditions ? debug visibility ? queue water marking/threshold ? error and status recording to facilitate debug ? memory protection support ? proxied memory protection for tr submission ? active memory protection for accesses to param and registers each edmatc has the following features: ? supports 2-dimensional (2d) transfers with independent indexes on source and destination (edmacc manages the 3rd dimension) ? up to 4 in-flight transfer requests (tr) ? programmable priority levels ? support for increment or constant addressing mode transfers ? interrupt and error support ? supports only little-endian operation in this device ? memory mapped register (mmr) bit fields are fixed position in 32-bit mmr for more information chapter edma controller of the device trm. 6.14 peripherals 6.14.1 vip the vip module provides video capture functions for the device. vip incorporates a multi-channel raw video parser, various video processing blocks, and a flexible video port direct memory access (vpdma) engine to store incoming video in various formats. the device uses a single instantiation of the vip module giving the ability of capturing up to two video streams. a vip module includes the following main features: 352 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? two independently configurable external video input capture slices (slice 0 and slice 1) each of which has two video input ports, port a and port b, where port a can be configured as a 24/16/8-bit port, and port b is a fixed 8-bit port. ? each video port a can be operated as a port with clock independent input channels (with interleaved or separated y/c data input). embedded sync and external sync modes are supported for all input configurations. ? support for a single external asynchronous pixel clock, up to 165mhz per port. ? pixel clock input domain port a supports up to one 24-bit input data bus, including bt.1120 style embedded sync for 16-bit and 24-bit data. ? embedded sync data interface mode supports single or multiplexed sources ? discrete sync data interface mode supports only single source input ? 24-bit data input plus discrete syncs can be configured to include: ? 8-bit yuv422 (y and u/v time interleaved) ? 16-bit yuv422 (cby and cry time interleaved) ? 24-bit yuv444 ? 16-bit rgb565 ? 24-bit rgb888 ? 12/16-bit raw capture ? 24-bit raw capture ? discrete sync modes include: ? vsync + hsync (fid determined by fid signal pin or hsync/vsync skew) ? vsync + actvid + fid ? vblank + actvid (actvid toggles in vblank) + fid ? vblank + actvid (no actvid toggles in vblank) + fid ? multichannel parser (embedded syncs only) ? embedded syncs only ? pixel (2x or 4x) or line multiplexed modes supported ? performs demultiplexing and basic error checking ? supports maximum of 9 channels in line mux (8 normal + 1 split line) ? ancillary data capture support ? for 16-bit or 24-bit input, ancillary data may be extracted from any single channel ? for 8-bit time interleaved input, ancillary data can be chosen from the luma channel, the chroma channel, or both channels ? horizontal blanking interval data capture only supported when using discrete syncs (vsync + hsync or vsync + hblank) ? ancillary data extraction supported on multichannel capture as well as single source streams 353 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? format conversion and scaling ? programmable color space conversion ? yuv422 to yuv444 conversion ? yuv444 to yuv422 conversion ? yuv422 to yuv420 conversion ? yuv444 source: yuv444 to yuv444, yuv444 to rgb888, yuv444 to yuv422, yuv444 to yuv420 ? rgb888 source: rgb888 to rgb888, rgb888 to yuv444, rgb888 to yuv422, rgb888 to yuv420 ? yuv422 source: yuv422 to yuv422, yuv422 to yuv420, yuv422 to yuv444, yuv422 to rgb888 ? supports raw to raw (no processing) ? scaling and format conversions do not work for multiplexed input ? supports up to 2047 pixels wide input - when scaling is engaged ? supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without scaling ? supports up to 4095 pixels wide input - without scaling and chroma up/down sampling ? the maximum supported input resolution is further limited by: ? pixel clock and feature-dependent constraints ? for rgb24-bit format (raw data), the maximum frame width is limited to 2730 pixels for more information, see chapter video input port of the device trm 6.14.2 dss display port interfaces (dpi) is available in dss named dpi video output (vout). vout interface consists of: ? 24-bit data bus (data[23:0]) ? horizontal synchronization signal (hsync) ? vertical synchronization signal (vsync) ? data enable (de) ? field id (fid) ? pixel clock (clk) for more information, see section display subsystem (dss) of the device trm. 6.14.3 timers the device includes several types of timers used by the system software, including 16 general-purpose (gp) timers, one watchdog timer, and a 32-khz synchronized timer (counter_32k). 6.14.3.1 general-purpose timers the device has 16 gp timers: timer1 through timer16. ? timer1(1ms tick): has its event capture pin tied to 32khz clock and can be used to gauge the system clock input and detects its frequency among 19.2, 20, or 27 mhz. it includes a specific functions to generate accurate tick interrupts to the operating system and it belongs to the pd_wkupaon domain ? timer2 and timer10: (1ms tick timers): they include a specific functions to generate accurate tick interrupts to the operating system, timer2 and timer10 belong to the pd_l4per domain ? timer3/4/9/11/13/14/15/16: they belongs to the pd_l4per domain ? timer12 belongs to the pd_wkupaon power domain ? timer5 trough timer8: belong to the pd_ipu module 354 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated each timer (except timer12) can be clocked from the system clock (19.2, 20, or 27 mhz) or the 32-khz clock. the selection of clock source is made at the power, reset, and clock management (prcm) module level. timer12 can be clocked only from the internal oscillator (on-die oscillator) the following are the main features of the gp timer controllers: ? level 4 (l4) slave interface support: ? 32-bit data bus width ? 32-/16-bit access supported ? 8-bit access not supported ? 10-bit address bus width ? burst mode not supported ? write nonposted transaction mode supported ? interrupts generated on overflow, compare, and capture ? free-running 32-bit upward counter ? compare and capture modes ? autoreload mode ? start/stop mode ? programmable divider clock source (2 n , where n = [0:8]) ? dedicated input trigger for capture mode and dedicated output trigger/pwm signal ? dedicated gp output signal for using the timeri_gpo_cfg signal ? on-the-fly read/write register (while counting) ? 1-ms tick with 32.768-hz functional clock generated (only timer1, timer2, and timer10) for more information, see section timers of the device trm. 6.14.3.2 32-khz synchronized timer (counter_32k) the 32-khz synchronized timer (counter_32k) is a 32-bit counter clocked by the falling edge of the 32- khz system clock. the main features of the 32-khz synchronized timer controller are: ? l4 slave interface (ocp) support: ? 32-bit data bus width ? 32-/16-bit access supported ? 8-bit access not supported ? 16-bit address bus width ? burst mode not supported ? write nonposted transaction mode not supported ? only read operations are supported on the module registers; no write operation is supported (no error/no action on write). ? free-running 32-bit upward counter ? start and keep counting after power-on reset ? automatic roll over to 0; highest value reached: 0xffff ffff ? on-the-fly read (while counting) for more information, see section timers of the device trm. 6.14.3.3 watchdog timer the device includes one instance of the 32-bit watchdog timer: wd_timer2. 355 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated the watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt to the device system modules following an overflow condition. the wd_timer2 timer serves resets to the prcm module (its interrupt outputs are unused). wd_timer2 is located in the pd_wkupaon power domain, and can run when the device is in lowest power state (all power domains are off except always-on (aon) and wkup). the watchdog timer can be accessed, loaded, and cleared by registers through the l4_wkup interface. the watchdog timer has the 32-khz clock for its timer clock input. wd_timer2 directly generates a warm reset condition on overflow. wd_timer2 connects to a single target agent port on the l4_wkup interconnect. the main features of the watchdog timer controllers are: ? l4 slave interface support: ? 32-bit data bus width ? 32-/16-bit access supported ? 8-bit access not supported ? 11-bit address bus width ? burst mode not supported ? write nonposted mode supported ? free-running 32-bit upward counter ? programmable divider clock source (2 n where n = [0:7]) ? on-the-fly read/write register (while counting) ? subset programming model of the gp timer ? the watchdog timer is reset either on power on or after a warm reset before it starts counting. ? reset or interrupt actions when a timer overflow condition occurs ? the watchdog timer generates a reset or an interrupt in its hardware integration. for more information, see section timers of the device trm. 6.14.4 i2c the device contains five multimaster high-speed (hs) inter-integrated circuit (i 2 c) controllers (i2c i modules, where i = 1, 2 ,3, 4, 5, 6) each of which provides an interface between a local host (lh), such as a digital signal processor (dsp), and any i 2 c-bus-compatible device that connects through the i 2 c serial bus. external components attached to the i 2 c bus can serially transmit and receive up to 8 bits of data to and from the lh device through the 2-wire i 2 c interface. each multimaster hs i 2 c controller can be configured to act like a slave or master i 2 c-compatible device. i 2 c1 and i 2 c2 controllers have dedicated i 2 c compliant open drain buffers, and support fast mode (up to 400kbps). i 2 c3, i 2 c4, i 2 c5 and i 2 c6 controllers are multiplexed with standard lvcmos io and connected to emulate open drain. i 2 c emulation is achieved by configuring the lvcmos buffers to output hi-z instead of driving high when transmitting logic 1. these controllers support hs mode (up to 3.4mbps). for more information, see section multimaster high-speed i2c controller (i2c) in chapter serial communication interfaces of the device trm. 6.14.5 uart the uart is a simple l4 slave peripheral that utilizes the dma_system or edma for data transfer or irq polling via cpu. there are 10 uart modules in the device. only one uart supports irda features. each uart can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices. 356 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.14.5.1 uart features the uarti (where i = 1 to 10) include the following features: ? 16c750 compatibility ? 64-byte fifo buffer for receiver and 64-byte fifo for transmitter ? programmable interrupt trigger levels for fifos ? baud generation based on programmable divisors n (where n = 1 ? 16,384) operating from a fixed functional clock of 48 mhz or 192 mhz oversampling is programmed by software as 16 or 13. thus, the baud rate computation is one of two options: ? baud rate = (functional clock / 16) / n ? baud rate = (functional clock / 13) / n ? this software programming mode enables higher baud rates with the same error amount without changing the clock source ? break character detection and generation ? configurable data format: ? data bit: 5, 6, 7, or 8 bits ? parity bit: even, odd, none ? stop-bit: 1, 1.5, 2 bit(s) ? flow control: hardware (rts/cts) or software (xon/xoff) ? the 48 mhz functional clock option allows baud rates up to 3.6mbps ? the 192 mhz functional clock option allows baud rates up to 12mbps ? uart1 module has extended modem control signals (dcd, ri, dtr, dsr) ? uart3 supports irda 6.14.5.2 irda features uart3 supports the following irda key features: ? support of irda 1.4 slow infrared (sir), medium infrared (mir), and fast infrared (fir) communications: ? frame formatting: addition of variable beginning-of-frame (xbof) characters and end-of-frame (eof) characters ? uplink/downlink cyclic redundancy check (crc) generation/detection ? asynchronous transparency (automatic insertion of break character) ? eight-entry status fifo (with selectable trigger levels) to monitor frame length and frame errors ? framing error, crc error, illegal symbol (fir), and abort pattern (sir, mir) detection 6.14.5.3 cir features the cir mode uses a variable pulse-width modulation (pwm) technique (based on multiples of a programmable t period) to encompass the various formats of infrared encoding for remote-control applications. the cir logic transmits data packets based on a user-definable frame structure and packet content. the cir (uart3 only) includes the following features to provide cir support for remote-control applications: ? transmit mode only (receive mode is not supported) ? free data format (supports any remote-control private standards) ? selectable bit rate ? configurable carrier frequency ? 1/2, 5/12, 1/3, or 1/4 carrier duty cycle 357 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated for more information, see section universal asynchronous receiver/transmitter (uart) in chapter serial communication interfaces of the device trm. 6.14.6 mcspi the mcspi is a master/slave synchronous serial bus. there are four separate mcspi modules (mcspi1, mcspi2, mcspi3, and mcspi4) in the device. all these four modules support up to four external devices (four chip selects) and are able to work as both master and slave. the mcspi modules include the following main features: ? serial clock with programmable frequency, polarity, and phase for each channel ? wide selection of mcspi word lengths, ranging from 4 to 32 bits ? up to four master channels, or single channel in slave mode ? master multichannel mode: ? full duplex/half duplex ? transmit-only/receive-only/transmit-and-receive modes ? flexible input/output (i/o) port controls per channel ? programmable clock granularity ? mcspi configuration per channel. this means, clock definition, polarity enabling and word width ? single interrupt line for multiple interrupt source events ? power management through wake-up capabilities ? enable the addition of a programmable start-bit for mcspi transfer per channel (start-bit mode) ? supports start-bit write command ? supports start-bit pause and break sequence ? programmable timing control between chip select and external clock generation ? built-in fifo available for a single channel for more information, see section serial peripheral interface (mcspi) in chapter serial communication interfaces of the device trm. 358 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.14.7 qspi the quad serial peripheral interface (qspi ? ) module is a kind of spi module that allows single, dual, or quad read access to external spi devices. this module has a memory mapped register interface, which provides a direct interface for accessing data from external spi devices and thus simplifying software requirements. the qspi works as a master only. the qspi supports the following features: ? general spi features: ? programmable clock divider ? six pin interface ? programmable length (from 1 to 128 bits) of the words transferred ? programmable number (from 1 to 4096) of the words transferred ? 4 external chip-select signals ? support for 3-, 4-, or 6-pin spi interface ? optional interrupt generation on word or frame (number of words) completion ? programmable delay between chip select activation and output data from 0 to 3 qspi clock cycles ? programmable signal polarities ? programmable active clock edge ? software-controllable interface allowing for any type of spi transfer ? control through l3_main configuration port ? serial flash interface (sfi) features: ? serial flash read/write interface ? additional registers for defining read and write commands to the external serial flash device ? 1 to 4 address bytes ? fast read support, where fast read requires dummy bytes after address bytes; 0 to 3 dummy bytes can be configured. ? dual read support ? quad read support ? little-endian support only ? linear increment addressing mode only the qspi supports only dual and quad reads. dual or quad writes are not supported. in addition, there is no "pass through" mode supported where the data present on the qspi input is sent to its output. for more information, see section quad serial peripheral interface (qspi) in chapter serial communication interfaces of the device trm. 6.14.8 mcasp the mcasp functions as a general-purpose audio serial port optimized to the requirements of various audio applications. the mcasp module can operate in both transmit and receive modes. the mcasp is useful for time-division multiplexed (tdm) stream, inter-ic sound (i2s) protocols reception and transmission as well as for an intercomponent digital audio interface transmission (dit). the mcasp has the flexibility to gluelessly connect to a sony/philips digital interface (s/pdif) transmit physical layer component. although intercomponent digital audio interface reception (dir) mode (i.e. s/pdif stream receiving) is not natively supported by the mcasp module, a specific tdm mode implementation for the mcasp receivers allows an easy connection to external dir components (for example, s/pdif to i2s format converters). the device have integrated 8 mcasp modules (mcasp1-mcasp8) with: ? mcasp1 and mcasp2 supporting 16 channels with independent tx/rx clock/sync domain ? mcasp3 through mcasp7 modules supporting 4 channels with independent tx/rx clock/sync domain 359 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? mcasp8 module supporting 2 channels with independent tx/rx clock/sync domain for more information, see section multichannel audio serial port (mcasp) in chapter serial communication interfaces of the device trm. 6.14.9 usb superspeed usb drd subsystem has three instances in the device providing the following functions: ? usb1: superspeed (ss) usb 3.0 dual-role-device (drd) subsystem with integrated ss (usb3.0) phy and hs/fs (usb2.0) phy ? usb2: high-speed (hs) usb 2.0 dual-role-device (drd) subsystem with integrated hs/fs phy ? usb3: hs usb 2.0 dual-role-device (drd) subsystem with ulpi (sdr) interface to external hs/fs phys superspeed usb drd subsystem has the following features: ? dual-role-device (drd) capability: ? supports usb peripheral (or device) mode at speeds ss (5gbps)(usb1 only), hs (480 mbps), and fs (12 mbps) ? supports usb host mode at speeds ss (5gbps)(usb1 only), hs (480 mbps), fs (12 mbps), and ls (1.5 mbps) ? usb static peripheral operation ? usb static host operation ? flexible stream allocation ? stream priority ? external buffer control ? each instance contains single xhci controller with the following features: ? internal dma controller ? descriptor caching and data prefetching ? interrupt moderation and blocking ? power management usb3.0 states for u0, u1, u2, and u3 ? dynamic fifo memory allocation for all endpoints ? supports all modes of transfers (control, bulk, interrupt, and isochronous) ? supports high bandwidth iso mode ? connects to an external charge pump for vbus 5 v generation ? usb-hs phy (usb2phy1 and usb2phy2 for usb1 and usb2, respectively): contain the usb functions, drivers, receivers, and pads for correct d+/d ? signalling ? usb3phy. the usb3phy is embedded in the usb1 subsystem and contains: ? usb3rx_phy deserializer to receive data at superspeed mode ? usb3tx_phy serializer to transmit data at superspeed mode ? power sequencer that contains a power control state machine, generating the sequences to power up/down the usb3rx_phy/usb3tx_phy ? dedicated dpll (dpll_usb_otg_ss) for more information, see section superspeed usb drd (usb) in chapter serial communication interfaces of the device trm. 360 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.14.10 pcie the peripheral component interconnect express (pcie) module is a multi-lane i/o interconnect that provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 gbps per lane, per direction, for serial links on backplanes and printed wiring boards. it is a 3-rd generation i/o interconnect technology succeeding pci and isa bus that is designed to be used as a general-purpose serial i/o interconnect. it is also used as a bridge to other interconnects like usb2/3.0, gbe mac, and so forth. the pci express standard predecessor - pci, is a parallel bus architecture that is increasingly difficult to scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. the pcie architecture was developed to help minimize i/o bus bottlenecks within systems and to provide the necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. it is designed to replace the pci-based shared, parallel bus signaling technology that is approaching its practical performance limits while simplifying the interface design. the device instantiates two pcie subsystems (pcie_ss1 and pcie_ss2). the pcie controller is capable to operate either in root complex (rc) or in end point (ep) pcie mode. the device pcie_ss1 controller supports up to two 16-bit data lanes on its pipe port. the device pcie_ss2 controller supports only one 16-bit data lane on its pipe port. when the pcie_ss1 controller pipe port is configured to operate in a single-lane mode, it operates on a single pair of pcie phy serializer and deserializer - pcie1_phy_tx/pcie1_phy_rx. when pcie_ss1 pipe is configured to operate in dual-lane mode, it operates on two pairs of pcie phy serializer and deserializer - pcie1_phy_tx/pcie1_phy_rx and pcie2_phy_tx/pcie2_phy_rx, respectively. the single-lane pcie_ss2 controller pipe port (if enabled) can operate only on the pcie2_phy_tx/pcie2_phy_rx pair. hereby, if pcie_ss2 controller is used, the pcie_ss1 can operate only in a single-lane mode on the pcie1_phy_tx/pcie1_phy_rx. in addition, pcie phy subsystem encompasses a pcie pcs (physical coding sublayer), a pcie power management logic, apll, a dpll reference clock generator and an apll clock low-jitter buffer. ? the pcie controller implements the transport and link layers of the pcie interface protocol. ? pcie pcs (a physical coding sublayer component) converts a 8-bit portion of parallel data over a pcie lane to a 10-bit parallel data to adapt the process of serialization and deserialization in the tx/rx phys to various requirements. at the same time it transforms the transmission rate to maintain the pcie gen2 bandwidth (5 gbps) on both sides (pcie controller and phy). ? a multiplexer logic which adds flexibility to connect a pcie controller hardware mapped pcs logic output to a single (for the single-lane pcie_ss2 controller) or to a couple (for the 2-lane pcie_ss1 controller) of phy ports at a time ? physical layer (phy) serializer/deserializer components with associated power control logic, building the so called pma (physical media attachment) part of the pcie_phy transceiver, as follows: ? pcie physical port 0 associated serializer (tx) - pcie1_phy_tx and deserializer (rx) - pcie1_phy_rx ? pcie physical port 1 associated serializer (tx) - pcie2_phy_tx and deserializer (rx) - pcie2_phy_rx ? dpll_pcie_ref is a dpll clock source, controlled from the device prcm, that provides a 100-mhz clock to the pcie phy serializer/deserializer components reference clock inputs. ? both the pcie_ss1 and pcie_ss2 share the same apll (apllpcie) which by default multiplies the dpll_pcie_ref (typically 100 mhz or 20 mhz) clock to 2.5 ghz. ? the apllpcie low-jitter buffer (acspcie) and additional logic takes care to provide the pcie apll reference input clock. pcie module supports the following features: ? pci local bus specification revision 3.0 ? pci express base 3.0 specification, revision 1.0. 361 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated at system level the device supports pci express interface in the following configurations: ? each pcie subsystem controller has support for pcie gen2 mode (5.0 gbps per lane) and gen1 mode (2.5 gbps per lane). ? one pcie (pcie_ss1) operates as gen2 2-lanes supporting in either root-complex (rc) or end-point ep. ? two pcie (pcie_ss1 and pcie_ss2) operates gen2 1-lane supporting either rc or ep with the possibility of one operating in gen1 and one in gen2. ? pcie_ss1 can be configured to operate in either 2-lane (dual lane) or 1-lane (single lane) mode, as follows: ? single lane - lane 0 mapped to the pcie port 0 of the device ? flexible dual lane configuration - lanes 0 and 1 can be swapped on the two pcie ports ? pcie_ss2 can only operate in 1-lane mode, as follows: ? single lane - lane 0 mapped to the device pcie port 1 when pcie_ss1 is configured to operate in dual-lane mode, pcie_ss2 is in-operable as both pcie1_phy_rx/tx and pcie2_phy_rx/tx are assigned to pcie_ss1, and thereby not available to pcie_ss2. the main features of a device pcie controller are: ? 16-bit operation at 250 mhz on pipe interface (per 16-bit lane) ? one master port on the l3_main supporting 32-bit address and 64-bit data bus. ? pcie_ss1 master port dedicated mmu (device mmu2) on l3_main path, to which pcie traffic can be optionally mapped. ? one slave port on the l3_main supporting 29-bit address and 64-bit data bus. ? maximum outbound payload size of 64 bytes (the l3 interconnect pcie1/2 target ports split bursts of size > 64 bytes to the into multiple 64 byte bursts) ? maximum inbound payload size of 256 bytes (internally converted to 128 byte - bursts) ? no remote read request size limit: implicit support for 4 kib-size and greater ? support of ep legacy mode ? support of inbound i/o accesses in ep legacy mode ? pipe interface features fixed-width (16-bit data per lane) and dynamic frequency to switch between pcie gen1 and gen2. ? ultra-low transmit and receive latency ? automatic lane reversal as specified in the pci express base 3.0 specification, revision 1.0 (transmit and receive) ? polarity inversion on receive ? single virtual channel (vc0) and single traffic class (tc0) ? single function in end point mode ? automatic credit management ? ecrc generation and checking ? all pci device power management d-states with the exception of d3 cold /l2 state ? pci express active state power management (aspm) state l0s and l1 (with exceptions) ? pci express link power management states except for l2 state ? pci express advanced error reporting (aer) ? pci express messages for both transmit and receive ? filtering for posted, non-posted, and completion traffic ? configurable bar filtering, i/o filtering, configuration filtering and completion lookup/timeout ? access to configuration space registers and external application memory mapped registers through ecam mechanism. 362 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? legacy pci interrupts reception (rc) and generation (ep) ? 2 x hardware interrupts per pcie_ss1and pcie_ss2 controller mapped via the device interrupt crossbar (irq_crossbar) to multiple device host (mpu, dsp, and so forth) interrupt controllers in the device ? msis generation and reception ? pcie_phy loopback in rc mode for more information, see section pcie controller in chapter serial communication interfaces of the device trm. 6.14.11 dcan the controller area network (can) is a serial communications protocol which efficiently supports distributed real-time applications. can has high immunity to electrical interference and the ability to self- diagnose and repair data errors. in a can network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. the device provides two dcan interfaces for supporting distributed realtime control with a high level of security. the dcan interfaces implement the following features: ? supports can protocol version 2.0 part a, b ? bit rates up to 1 mbit/s ? 64 message objects ? individual identifier mask for each message object ? programmable fifo mode for message objects ? programmable loop-back modes for self-test operation ? suspend mode for debug support ? software module reset ? automatic bus on after bus-off state by a programmable 32-bit timer ? direct access to message ram during test mode ? can rx/tx pins are configurable as general-purpose io pins ? two interrupt lines (plus additional parity-error interrupts line) ? ram initialization ? dma support for more information, see section dcan in chapter serial communication interfaces of the device trm. 6.14.12 gmac_sw the three-port gigabit ethernet switch subsystem (gmac_sw) provides ethernet packet communication and can be configured as an ethernet switch. it provides the gigabit media independent interface (g/mii) in mii mode, reduced gigabit media independent interface (rgmii), reduced media independent interface (rmii), and the management data input output (mdio) for physical layer device (phy) management. the gmac_sw subsystem provides the following features: ? two ethernet ports (port 1 and port 2) with selectable rgmii, rmii, and g/mii (in mii mode only) interfaces plus internal communications port programming interface (cppi 3.1) on port 0 ? synchronous 10/100/1000 mbit operation ? wire rate switching (802.1d) ? non-blocking switch fabric ? flexible logical fifo-based packet buffer structure ? four priority level quality of service (qos) support (802.1p) ? cppi 3.1 compliant dma controllers ? support for audio/video bridging (p802.1qav/d6.0) 363 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? support for ieee 1588 clock synchronization (2008 annex d and annex f) ? timing fifo and time stamping logic embedded in the subsystem ? device level ring (dlr) support ? energy efficient ethernet (eee) support (802.3az) ? flow control support (802.3x) ? address lookup engine (ale) ? 1024 total address entries plus vlans ? wire rate lookup ? host controlled time-based aging ? multiple spanning tree support (spanning tree per vlan) ? l2 address lock and l2 filtering support ? mac authentication (802.1x) ? receive-based or destination-based multicast and broadcast rate limits ? mac address blocking ? source port locking ? oui (vendor id) host accept/deny feature ? remapping of priority level of vlan or ports ? vlan support ? 802.1q compliant ? auto add port vlan for untagged frames on ingress ? auto vlan removal on egress and auto pad to minimum frame size ? ethernet statistics: ? etherstats and 802.3stats remote network monitoring (rmon) statistics gathering (shared) ? programmable statistics interrupt mask when a statistic is above one half its 32-bit value ? flow control support (802.3x) ? digital loopback and fifo loopback modes supported ? maximum frame size 2016 bytes (2020 with vlan) ? 8k (2048 32) internal cppi buffer descriptor memory ? management data input/output (mdio) module for phy management ? programmable interrupt control with selected interrupt pacing ? emulation support ? programmable transmit inter packet gap (ipg) ? reset isolation (switch function remains active even in case of all device resets except for por pin reset and icepick cold reset) ? full duplex mode supported in 10/100/1000 mbps. half-duplex mode supported only in 10/100 mbps. ? ieee 802.3 gigabit ethernet conformant for more information, see section gigabit ethernet switch (gmac_sw) in chapter serial communication interfaces of the device trm. 6.14.13 emmc/sd/sdio the emmc/sd/sdio host controller provides an interface between a local host (lh) such as a microprocessor unit (mpu) or digital signal processor (dsp) and either emmc, sd ? memory cards, or sdio cards and handles emmc/sd/sdio transactions with minimal lh intervention. optionally, the controller is connected to the l3_main interconnect to have a direct access to system memory. it also supports two direct memory access (dma) slave channels or a dma master access (in this case, slave dma channels are deactivated) depending on its integration. 364 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated the emmc/sd/sdio host controller deals with emmc/sd/sdio protocol at transmission level, data packing, adding cyclic redundancy checks (crcs), start/end bit, and checking for syntactical correctness. the application interface can send every emmc/sd/sdio command and poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation. the application interface can read card responses or flag registers. it can also mask individual interrupt sources. all these operations can be performed by reading and writing control registers. the emmc/sd/sdio host controller also supports two dma channels. there are four emmc/sd/sdio host controllers inside the device. gives an overview of the emmc/sd/sdioi (i = 1 to 4) controllers. each controller has the following data width: ? emmc/sd/sdio1 - 4-bit wide data bus ? emmc/sd/sdio2 - 8-bit wide data bus ? emmc/sd/sdio3 - 4-bit wide data bus ? emmc/sd/sdio4 - 4-bit wide data bus the emmc/sd/sdioi controller is also referred to as mmci. compliance with standards: ? full compliance with mmc/emmc command/response sets as defined in the jc64 mmc/emmc standard specification, v4.5. ? full compliance with sd command/response sets as defined in the sd physical layer specification v3.01 ? full compliance with sdio command/response sets and interrupt/read-wait suspend-resume operations as defined in the sd part e1 specification v3.00 ? full compliance with sd host controller standard specification sets as defined in the sd card specification part a2 v3.00 main features of the emmc/sd/sdio host controllers: ? flexible architecture allowing support for new command structure ? 32-bit wide access bus to maximize bus throughput ? designed for low power ? programmable clock generation ? dedicated dll to support sdr104 mode (mmc1 only) ? dedicated dll to support hs200 mode (mmc2 only) ? card insertion/removal detection and write protect detection ? l4 slave interface supports: ? 32-bit data bus width ? 8/16/32 bit access supported ? 9-bit address bus width ? streaming burst supported only with burst length up to 7 ? wnp supported ? l3 initiator interface supports: ? 32-bit data bus width ? 8/16/32 bit access supported ? 32-bit address bus width ? burst supported ? built-in 1024-byte buffer for read or write ? two dma channels, one interrupt line ? support jc 64 v4.4.1 boot mode operations 365 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? support sda 3.00 part a2 programming model ? support sda 3.00 part a2 dma feature (adma2) ? supported data transfer rates: ? mmci supports the following sd v3.0 data transfer rates: ? ds mode (3.3v ios): up to 12 mbps (24 mhz clock) ? hs mode (3.3v ios): up to 24 mbps (48 mhz clock) ? sdr12 (1.8v ios): up to 12 mbps (24 mhz clock) ? sdr25 (1.8v ios): up to 24 mbps (48 mhz clock) ? sdr50 (1.8v ios): up to 48 mbps (96 mhz clock) - mmc1 and mmc3 only ? ddr50 (1.8v ios): up to 48 mbps (48 mhz clock) - mmc1 only ? sdr104 (1.8v ios) cards can be supported up to 192 mhz clock (96 mbps max) - mmc1 only ? mmci supports the default sd mode 1-bit data transfer up to 24mbps (3mbps) ? only mmc2 supports also the following jc64 v4.5 data transfer rates: ? up to 192 mbps in emmc mode, 8-bit sdr mode (192 mhz clock frequency) ? up to 96 mbps in emmc mode, 8-bit ddr mode (48 mhz clock frequency) ? all emmc/sd/sdio controllers are connected to 1,8v/3.3v compatible i/os to support 1,8v/3.3v signaling note emmc functionality is supported fully by mmc2 only. the other mmc modules are capable of emmc functionality, but are not timing-optimized for emmc. the differences between the emmc/sd/sdio host controllers and a standard sd host controller defined by the sd card specification, part a2, sd host controller standard specification , v3.00 are: ? the clock divider in the emmc/sd/sdio host controller supports a wider range of frequency than specified in the sd memory card specifications , v3.0. the emmc/sd/sdio host controller supports odd and even clock ratio. ? the emmc/sd/sdio host controller supports configurable busy time-out. ? adma2 64-bit mode is not supported. ? there is no external led control. note only even ratios are supported in ddr mode. for more information, see chapter emmc/sd/sdio of the device trm. 366 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated 6.14.14 gpio the general-purpose interface combines eight general-purpose input/output (gpio) banks. each gpio module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 186 pins. these pins can be configured for the following applications: ? data input (capture)/output (drive) ? keyboard interface with a debounce cell ? interrupt generation in active mode upon the detection of external events. detected events are processed by two parallel independent interrupt-generation submodules to support biprocessor operations. ? wake-up request generation in idle mode upon the detection of external events for more information, see chapter general-purpose interface (gpio) of the device trm. 6.14.15 epwm an effective pwm peripheral must be able to generate complex pulse width waveforms with minimal cpu overhead or intervention. it needs to be highly programmable and very flexible while being easy to understand and use. the epwm unit described here addresses these requirements by allocating all needed timing and control resources on a per pwm channel basis. cross coupling or sharing of resources has been avoided; instead, the epwm is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. this modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly. each epwm module supports the following features: ? dedicated 16-bit time-base counter with period and frequency control ? two pwm outputs (epwmxa and epwmxb) that can be used in the following configurations: ? two independent pwm outputs with single-edge operation ? two independent pwm outputs with dual-edge symmetric operation ? one independent pwm output with dual-edge asymmetric operation ? asynchronous override control of pwm signals through software. ? programmable phase-control support for lag or lead operation relative to other epwm modules. ? hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis. ? dead-band generation with independent rising and falling edge delay control. ? programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions. ? a trip condition can force either high, low, or high-impedance state logic levels at pwm outputs. ? programmable event prescaling minimizes cpu overhead on interrupts. ? pwm chopping by high-frequency carrier signal, useful for pulse transformer gate drives. for more information, see section enhanced pwm (epwm) module in chapter pulse-width modulation subsystem of the device trm. 6.14.16 ecap uses for ecap include: ? sample rate measurements of audio inputs ? speed measurements of rotating machinery (for example, toothed sprockets sensed via hall sensors) ? elapsed time measurements between position sensor pulses ? 4 stage sequencer (mod4 counter) which is synchronized to external events (ecapx pin edges) 367 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? period and duty cycle measurements of pulse train signals ? decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors the ecap module includes the following features: ? 32-bit time base counter ? 4-event time-stamp registers (each 32 bits) ? edge polarity selection for up to four sequenced time-stamp capture events ? interrupt on either of the four events ? single shot capture of up to four event time-stamps ? continuous mode capture of time-stamps in a four-deep circular buffer ? absolute time-stamp capture ? difference (delta) mode time-stamp capture ? all above resources dedicated to a single input pin ? when not used in capture mode, the ecap module can be configured as a single channel pwm output for more information, see section enhanced capture (ecap) module in chapter pulse-width modulation subsystem of the device trm. 6.14.17 eqep a single track of slots patterns the periphery of an incremental encoder disk, as shown in figure 6-2 . these slots create an alternating pattern of dark and light lines. the disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution). as a rule, a second track is added to generate a signal that occurs once per revolution (index signal: qepi), which can be used to indicate an absolute position. encoder manufacturers identify the index pulse using different terms such as index, marker, home position, and zero reference. figure 6-2. optical encoder disk to derive direction information, the lines on the disk are read out by two different photo-elements that "look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. this shift is realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. as the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other. these are commonly called the quadrature qepa and qepb signals. the clockwise direction for most encoders is defined as the qepa channel going positive before the qepb channel. the encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at a geared rotation ratio with respect to the motor. therefore, the frequency of the digital signal coming from the qepa and qepb outputs varies proportionally with the velocity of the motor. for example, a 2000-line encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 khz, so by measuring the frequency of either the qepa or qepb output, the processor can determine the velocity of the motor. qepa qepb qepi eqep-001 368 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated for more information, see section enhanced quadrature encoder pulse (eqep) module in chapter pulse- width modulation subsystem of the device trm. 6.15 on-chip debug debugging a system that contains an embedded processor involves an environment that connects high- level debugging software running on a host computer to a low-level debug interface supported by the target device. between these levels, a debug and trace controller (dtc) facilitates communication between the host debugger and the debug support logic on the target chip. the dtc is a combination of hardware and software that connects the host debugger to the target system. the dtc uses one or more hardware interfaces and/or protocols to convert actions dictated by the debugger user to jtag ? commands and scans that execute the core hardware. the debug software and hardware components let the user control multiple central processing unit (cpu) cores embedded in the device in a global or local manner. this environment provides: ? synchronized global starting and stopping of multiple processors ? starting and stopping of an individual processor ? each processor can generate triggers that can be used to alter the execution flow of other processors system topics include but are not limited to: ? system clocking and power-down issues ? interconnection of multiple devices ? trigger channels for more information, see chapter on-chip debug of the device trm. the device deploys texas instrument's ctools debug technology for on-chip debug and trace support. it provides the following features: ? external debug interfaces: ? primary debug interface - ieee1149.1 (jtag) or ieee1149.7 (complementary superset of jtag) ? used for debugger connection ? default mode is ieee1149.1 but debugger can switch to ieee1149.7 via an ieee1149.7 adapter module ? controls icepick ? (generic test access port [tap] for dynamic tap insertion) to allow the debugger to access several debug resources through its secondary (output) jtag ports (for more information, see icepick secondary taps section of the device trm). ? debug (trace) port ? can be used to export processor or system trace off-chip (to an external trace receiver) ? can be used for cross-triggering with an external device ? configured through debug resources manager (drm) module instantiated in the debug subsystem ? for more information about debug (trace) port, see debug (trace) port and concurrent debug modes sections of the device trm. ? jtag based processor debug on: ? cortex-a15 in mpu ? c66x in dsp1 ? cortex-m4 (x2) in ipu1, ipu2 ? arm968 (x2) in iva ? dynamic tap insertion ? controlled by icepick ? for more information, see , dynamic tap insertion. 369 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? power and clock management ? debugger can get the status of the power domain associated to each tap. ? debugger may prevent the application software switching off the power domain. ? application power management behavior can be preserved during debug across power transitions. ? for more information, see power and clock management section of the device trm. ? reset management ? debugger can configure icepick to assert, block, or extend the reset of a given subsystem. ? for more information, see reset management section of the device trm. ? cross-triggering ? provides a way to propagate debug (trigger) events from one processor, subsystem, or module to another: ? subsystem a can be programmed to generate a debug event, which can then be exported as a global trigger across the device. ? subsystem b can be programmed to be sensitive to the trigger line input and to generate an action on trigger detection. ? two global trigger lines are implemented ? device-level cross-triggering is handled by the xtrig (ti cross-trigger) module implemented in the debug subsystem ? various arm ? coresight ? cross-trigger modules implemented to provide support for coresight triggers distribution ? coresight cross-trigger interface (cs_cti) modules ? coresight cross-trigger matrix (cs_ctm) modules ? for more information about cross-triggering, see cross-triggering section of the device trm. ? suspend ? provides a way to stop a closely coupled hardware process running on a peripheral module when the host processor enters debug state ? for more information about suspend, see suspend section of the device trm. ? mpu watchpoint ? embedded in mpu subsystem ? provides visibility on mpu to emif direct paths ? for more information, see mpu memory adaptor (mpu_ma) watchpoint section of the device trm. ? processor trace ? cortex-a15 (mpu) and c66x (dsp) processor trace is supported ? program trace only for mpu (no data trace) ? mpu trace supported by a coresight program trace macrocell (cs_ptm) module ? three exclusive trace sinks: ? coresight trace port interface unit (cs_tpiu) ? trace export to an external trace receiver ? ctools trace buffer router (ct_tbr) in system bridge mode ? trace export through usb ? ct_tbr in buffer mode ? trace history store into on-chip trace buffer ? for more information, see processor trace section of the device trm. 370 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 detailed description copyright ? 2016 ? 2018, texas instruments incorporated ? system instrumentation (trace) ? supported by a ctools system trace module (ct_stm), implementing mipi system trace protocol (stp) (rev 2.0) ? real-time software trace ? mpu software instrumentation through coresight stm (cs_stm) (stp2.0) ? system-on-chip (soc) software instrumentation through ct_stm (stp2.0) ? ocp watchpoint (ocp_wp_noc) ? ocp target traffic monitoring: ocp_wp_noc can be configured to generate a trigger upon watchpoint match (that is, when target transaction attributes match the user-defined attributes). ? soc events trace ? dma transfer profiling ? statistics collector (performance probes) ? computes traffic statistics within a user-defined window and periodically reports to the user through the ct_stm interface ? embedded in the l3_main interconnect ? 10 instances: ? 1 instance dedicated to target (sdram) load monitoring ? 9 instances dedicated to master latency monitoring ? iva instrumentation (hardware accelerator [hwa] profiling) ? supported through a software message and system trace event (smset) module embedded in the iva subsystem ? power-management events profiling (pm instrumentation [pmi]) ? monitoring major power-management events. the pm state changes are handled as generic events and encapsulated in stp messages. ? clock-management events profiling (cm instrumentation [cmi]) ? monitoring major clock management events. the cm state changes are handled as generic events and encapsulated in stp messages. ? two instances, one per cm ? cm1 instrumentation (cmi1) module mapped in the pd_core_aon power domain ? cm2 instrumentation (cmi2) module mapped in the pd_core power domain ? for more information, see system instrumentation section of the device trm. ? performance monitoring ? supported by subsystem counter timer module (sctm) for ipu ? supported by performance monitoring unit (pmu) for mpu subsystem for more information, see chapter on-chip debug support of the device trm. 371 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7 applications, implementation, and layout note information in the following applications section is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti's customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 7.1 introduction this chapter is intended to communicate, guide and illustrate a pcb design strategy resulting in a pcb that can support ti ? s latest application processor. this processor is a high-performance processor designed for automotive infotainment based on enhanced omap ? architecture integrated on a 28-nm cmos process technology. these guidelines first focus on designing a robust power delivery network (pdn) which is essential to achieve the desirable high performance processing available on device. the general principles and step- by-step approach for implementing good power integrity (pi) with specific requirements will be described for the key device power domains. ti strongly believes that simulating a pcb ? s proposed pdn is required for first pass pcb design success. key device processor high-current power domains need to be evaluated for power rail ir drop, decoupling capacitor loop-inductance and power rail target impedance. only then can a pcb ? s pdn performance be truly accessed by comparing these model pi parameters vs. ti ? s recommended values. ultimately for any high-volume product, ti recommends conducting a ? processor pdn validation ? test on prototype pcbs across processor ? split lots ? to verify pdn robustness meets desired performance goals for each customer ? s worst-case scenario. please contact your ti representative to receive guidance on pdn pi modeling and validation testing. likewise, the methodology and requirements needed to route device high-speed, differential interfaces (i.e. usb2.0, usb3.0, hdmi, pci), single-ended interfaces (i.e. ddr3, qspi) and general purpose interfaces using lvcmos drivers that meet timing requirements while minimizing signal integrity (si) distortions on the pcb ? s signaling traces. signal trace lengths and flight times are aligned with fr-4 standard specification for pcbs. several different pcb layout stack-up examples have been presented to illustrate a typical number of layers, signal assignments and controlled impedance requirements. different device interface signals demand more or less complexity for routing and controlled impedance stack-ups. optimizing the pcb ? s pdn stack-up needs with all of these different types of signal interfaces will ultimately determine the final layer count and layer assignments in each customer ? s pcb design. this guideline must be used as a supplement in complement to ti ? s application processor, power management ic (pmic) and audio companion components along with other ti component technical documentation (i.e. technical reference manual, data manual, data sheets, silicon errata, pin-out spreadsheet, application notes, etc.). note notwithstanding any provision to the contrary, ti makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, for customer boards. the data described in this appendix are intended as guidelines only. note these pcb guidelines are in a draft maturity and consequently, are subject to change depending on design verification testing conducted during ic development and validation. 372 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.1.1 initial requirements and guidelines unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35 and 65 to minimize the overshoot or undershoot on far-end loads. characteristic impedance for differential interfaces must be routed as differential traces on the same layer. the trace width and spacing must be chosen to yield the recommended differential impedance. for more information see section 7.5.1 . the pdn must be optimized for low trace resistance and low trace inductance for all high-current power nets from pmic to the device. an external interface using a connector must be protected following the iec61000-4-2 level 4 system esd. 7.2 power optimizations this section describes the necessary steps for designing a robust power distribution network (pdn): ? section 7.2.1 , step 1: pcb stack-up ? section 7.2.2 , step 2: physical placement ? section 7.2.3 , step 3: static analysis ? section 7.2.4 , step 4: frequency analysis 7.2.1 step 1: pcb stack-up the pcb stack-up (layer assignment) is an important factor in determining the optimal performance of the power distribution system. an optimized pcb stack-up for higher power integrity performance can be achieved by following these recommendations: ? power and ground plane pairs must be closely coupled together. the capacitance formed between the planes can decouple the power supply at high frequencies. whenever possible, the power and ground planes must be solid to provide continuous return path for return current. ? use a thin dielectric between the power and ground plane pair. capacitance is inversely proportional to the separation of the plane pair. minimizing the separation distance (the dielectric thickness) maximizes the capacitance. ? optimize the power and ground plane pair carrying high current supplies to key component power domains as close as possible to the same surface where these components are placed (see figure 7- 1 ). this will help to minimize ? loop inductance ? encountered between supply decoupling capacitors and component supply inputs and between power and ground plane pairs. note 1-2oz cu weight for power / ground plane is preferred to enable better pcb heat spreading, helping to reduce processor junction temperatures. in addition, it is preferable to have the power / ground planes be adjacent to the pcb surface on which the processor is mounted. 373 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-1. minimize loop inductance with proper layer assignment the placement of power and ground planes in the pcb stackup (determined by layer assignment) has a significant impact on the parasitic inductances of power current path as shown in figure 7-1 . for this reason, it is recommended to consider layer order in the early stages of the pcb pdn design cycle, putting high-priority supplies in the top half of the stackup (assuming high load and priority components are mounted on the top-side of pcb) and low-priority supplies in the bottom half of the stackup as shown in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is advised to put the sensitive and high-priority power supplies on the top/same layers). 7.2.2 step 2: physical placement a critical step in designing an optimized pdn is that proper care must be taken to making sure that the initial floor planning of the pcb layout is done with good power integrity design guidelines in mind. the following points are important for optimizing a pcb ? s pdn: ? minimizing the physical distance between power sources and key high load components is the first step toward optimization. placing source and load components on the same side of the pcb is desirable. this will minimize via inductance impact for high current loads and steps ? external trace routing between components must be as wide as possible. the wider the traces, the lower the dc resistance and consequently the lower the static ir drop. ? whenever possible for the internal layers (routing and plane), wide traces and copper area fills are preferred for pdn layout. the routing of power nets in plane provide for more interplane capacitance and improved high frequency performance of the pdn. ? whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling capacitors, power inductors and current sensing resistors). do not share vias among multiple capacitors for connecting power supply and ground planes. ? placement of vias must be as close as possible or even within a component ? s solder pad if the pcb technology you are using provides this capability. ? to avoid any ? ampacity ? issue ? maximum current-carrying capacity of each transitional via should be evaluated to determine the appropriate number of vias required to connect components. adding vias to bring the ? via-to-pad ? ratio to 1:1 will improve pdn performance. ? for noise sensitive power supplies (i.e. phase lock-loops, analog signals like audio and video), a gnd shield can be used to isolate coplanar supplies that may have high step currents or high frequency switching transitions from coupling into low-noise supplies. package die trace capacitor via note: 1. bga via pair loop inductance 2. power/ground net spreading inductance3. capacitor trace inductance loop inductance 1 2 3 power/ground ground/power sprs906_pcb_stackup_01 374 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-2. coplanar shielding of power net using ground guard-band 7.2.3 step 3: static analysis delivering reliable power to circuits is always of critical importance because voltage drops (also known as ir drops) can happen at every level within an electronic system, on-chip, within a package, and across the board. robust system performance can only be ensured by understanding how the system elements will perform under typical stressful use cases. therefore, it is a good practice to perform a static or dc analysis. static or dc analysis and design methodology results in a pdn design that minimizes voltage or ir drops across power and ground planes, traces and vias. this ensures the application processor ? s internal transistors will be operating within their specified voltage ranges for proper functionality. the amount of ir drop that will be encounter is based upon amount power drawn for a desired use case and pcb trace (widths, geometry and number of parallel traces) and via (size, type and number) characteristics. components that are distant from their power source are particularly susceptible to ir drop. designs that rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively impact system performance. early assessments a pdn ? s static (dc) performance helps to determine basic power distribution parameters such as best system input power point, optimal pcb layer stackup, and copper area needed for load currents. figure 7-3. depiction of sheet resistivity and resistance ohm ? s law (v = i r) relates conduction current to voltage drop. at dc, the relation coefficient is a constant and represents the resistance of the conductor. even current carrying conductors will dissipate power at high currents even though their resistance may be very small. both voltage drop and power dissipation are proportional to the resistance of the conductor. figure 7-4 shows a pcb-level static ir drop budget defined between the power management device (pmic) pins and the application processor ? s balls when the pmic is supplying power. ? it is highly recommended to physically place the pmic as close as possible to the processor and on the same side. the orientation of the pmic vs. processor should be aligned to minimize distance for the highest current rail. l w t the resistance rs of a plane conductorfor a unit length and unit width is called the (ohms per square). surface resistivity 1 rs = = t l r = rs w r t sprs906_pcb_static_01 vdd vdd_mpu vss pcb_po_8 375 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-4. static ir drop budget for pcb only the system-level ir drop budget is made up of three portions: on-chip, package, and pcb board. static ir or dc analysis/design methodology consists of designing the pdn such that the voltage drop (under dc operating conditions) across power and ground pads of the transistors of the application processor device is within a specified value of the nominal voltage for proper functionality of the device. a pcb system-level voltage drop budget for proper device functionality is typically 1.5% of nominal voltage. for a 1.35-v supply, this would be 20 mv. to accurately analyze pcb static ir drop, the actual geometry of the pdn must be modeled properly and simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration violations of current-carrying vias, and ? swiss-cheese ? effects via placement has on power rails. it is recommended to perform the following analyses: ? lumped resistance/ir drop analysis ? distributed resistance/ir drop analysis note the pmic companion device supporting this processor has been designed with voltage sensing feedback loop capabilities that enable a remote sense of the smps output voltage at the point of use. the note above means the smps feedback signals and returns must be routed across pcb and connected to the device input power ball for which a particular smps is supplying power. this feedback loop provides compensation for some of the voltage drop encountered across the pdn within limits. as such, the effective resistance of the pdn within this loop should be determined in order to optimize voltage compensation loop performance. the resistance of two pdn segments are of interest: one from the power inductor/bulk power filtering capacitor node to the processor ? s input power and second is the entire pdn route from smps output pin/ball to the processor input power. in the following sections each methodology is described in detail and an example has been provided of analysis flow that can be used by the pcb designer to validate compliance to the requirements on their pcb pdn design. bga pad on pcb source component load component static ir drop and effective resistance pcb sprs906_pcb_static_02 376 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.2.3.1 pdn resistance and ir drop lumped methodology consists of grouping all of the power pins on both the pmic (voltage source) and processor (current sink) devices. then the pmic source is set to an expected use case voltage level and the processor load has its use case current sink value set as well. now the lumped/effective resistance for the power rail trace/plane routes can be determine based upon the actual layout ? s power rail etch wide, shape, length, via count and placement figure 7-5 illustrates the pin-grouping/lumped concept. the lumped methodology consists of importing the pcb layout database (from cadence allegro tool or any other layout design tool) into the static ir drop modeling and simulation tool of preference for the pcb designer. this is followed by applying the correct pcb stack-up information (thickness, material properties) of the pcb dielectric and metallization layers. the material properties of dielectric consist of permittivity (dk) and loss tangent (df). for the conductor layers, the correct conductivity needs to be programmed into the simulation tool. this is followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources. the current and voltage information can be obtained from the power and voltage specifications of the device under different operating conditions / use cases. figure 7-5. pin-grouping concept: lumped and distributed methodologies 7.2.4 step 4: frequency analysis delivering low noise voltage sources are very important to allowing a system to operate at the lowest possible operational performance point (opp) for any one use case. an opp is a combination of the supply voltage level and clocking rate for key internal processor domains. a sch and pcb designed to provide low noise voltage supplies will then enable the processor to enter optimal opps for each use case that in turn will minimize power dissipation and junction temperatures on-die. therefore, it is a good engineering practice to perform a frequency analysis over the key power domains. frequency analysis and design methodology results in a pdn design that minimizes transient noise voltages at the processor ? s input power balls. this allows the processor ? s internal transistors to operate near the minimum specified operating supply voltage levels. to accomplish this one must evaluate how a voltage supply will change due to impedance variations over frequency. this analysis will focus on the decoupling capacitor network (vdd_xxx and vss/gnd rails) at the load. sufficient capacitance with a distribution of self-resonant points will provide for an overall lower impedance vs frequency response for each power domain. decoupling components that are distant from their load ? s input power are susceptible to encountering spreading loop inductance from the pcb design. early analysis of each key power domain ? s frequency response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment, and types needed for minimizing supply voltage noise/fluctuations due to switching and load current transients. note evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the load ? s input power balls has shown an 18% reduction in loop inductance due to reduced distance. grouped power/ground pins to create 1 equivalent resistive branch multiport net branch port/pin sources sinks sources sinks sprs906_pcb_pdn_01 377 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply voltage transients. a real capacitor has characteristics not only of capacitance but also inductance and resistance. figure 7-6 shows the parasitic model of a real capacitor. a real capacitor must be treated as an rlc circuit with effective series resistance (esr) and effective series inductance (esl). figure 7-6. characteristics of a real capacitor with esl and esr the magnitude of the impedance of this series model is given as: figure 7-7. series model impedance equation figure 7-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of 55 mhz. the impedance of the capacitor is a combination of its series resistance and reactive capacitance and inductance as shown in the equation above. figure 7-8. typical impedance profile of a capacitor sprs906_pcb_freq_03 1.0e+011.0e+00 1.0eC01 1.0eC02 1.0eC03 1.0eC04 1.00eC002 1.00e+000 1.00e+002 frequency (mhz) 1.00e+004 1.00e+006 1.00e+008 s-parameter magnitude job: gcm155r71e153ka55_15nf; x =1/ c c x = l l resonant frequency(55 mhz) (minimum) = where : ? ? - ? ? w = 2 2 1 z esr +esl c 2 ? ? - ? ? 2 1 esl c sprs906_pcb_freq_02 | c esl esr sprs906_pcb_freq_01 378 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated because a capacitor has series inductance and resistance that impacts its effectiveness, it is important that the following recommendations are adopted in placing capacitors on the pdn. wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and resistance. this was shown earlier in figure 7-1 . the capacitor mounting inductance and resistance values include the inductance and resistance of the pads, trace, and vias. whenever possible, use footprints that have the lowest inductance configuration as shown in figure 7-9 the length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance of the mounting. this trace must be as short and as wide as possible. wherever possible, minimize distance to supply and gnd vias by locating vias nearby or within the capacitor ? s solder pad landing. further improvements can be made to the mounting by placing vias to the side of capacitor lands or doubling the number of vias as shown in figure 7-9 . if the pcb manufacturing processes allow it and if cost-effective, via-in-pad (vip) geometries are strongly recommended. in addition to mounting inductance and resistance associated with placing a capacitor on the pcb, the effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the capacitor sees with respect to the load. the spreading inductance and resistance is strongly dependent on the layer assignment in the pcb stack-up. therefore, try to minimize x, y and z dimensions where the z is due to pcb thickness (as shown in figure 7-9 ). from left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in figure 7- 9 are known as: ? 2-via, skinny end exit (2vsee) ? 2-via, wide end exit (2vwee) ? 2-via, wide side exit (2vwse) ? 4-via, wide side exit (4vwse) ? 2-via, in-pad (2vip) figure 7-9. capacitor placement geometry for improved mounting inductance note evaluation of loop inductance values for decoupling capacitor footprints 2vsee (worst case) vs 4vwse (2nd best) has shown a 30% reduction in inductance when 4vwse footprint was used in place of 2vsee. decoupling capacitor (dcap) strategy: trace pad via mounting geometry for reduced inductance via-in-pad sprs906_pcb_freq_04 379 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 1. use lowest inductance footprint and trace connection scheme possible for given pcb technology and layout area in order to minimize dcap loop inductance to power pin as much as possible (see figure 7- 9 ). 2. place dcaps on ? same-side ? as component within their power plane outline to minimize ? decoupling loop inductance ? . target distance to power pin should be less than ~500mils depending upon pcb layout characteristics (plane's layer assignment and solid nature). use pi modeling cad tool to verify minimum inductance for top vs bottom-side placement. 3. place dcaps on ? opposite-side ? as component within their power plane outline if ? same-side ? is not feasible or if distance to power pin is greater than ~500mils for top-side location. use pi modeling cad tool to verify minimum inductance for top vs bottom-side placement. 4. use minimum 10mil trace width for all voltage and gnd planes connections (i.e. dcap pads, component power pins, etc.). 5. place all voltage and gnd plane vias ? as close as possible ? to point of use (i.e. dcap pads, component power pins, etc.). 6. use a ? power/gnd pad/pin to via ? ratio of 1:1 whenever possible. do not exceed 2:1 ratio for small number of vias within restricted pcb areas (i.e. underneath bga components). frequency analysis for the core power domain has yielded the vdd impedance vs frequency response shown in section 7.3.8.2 , vdd example analysis. as the example shows the overall core pdn r eff meets the maximum recommended pdn resistance of 10m . 7.2.5 system esd generic guidelines 7.2.5.1 system esd generic pcb guideline protection devices must be placed close to the esd source which means close to the connector. this allows the device to subtract the energy associated with an esd strike before it reaches the internal circuitry of the application board. to help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero turn-on impedance, it is mandatory to route the esd device with minimum stub length so that the low- resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance between signal and ground. for esd protection array being railed to a power supply when no decoupling capacitor is available in close vicinity, consider using a decoupling capacitor ( 0.1 f) tight to the vcc pin of the esd protection. a positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse. ensure that there is sufficient metallization for the supply of signals at the interconnect side (vcc and gnd in figure 7-10 ) from connector to external protection because the interconnect may see between 15- a to 30-a current in a short period of time during the esd event. 380 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-10. placement recommendation for an esd external protection note to ensure normal behavior of the esd protection (unwanted leakage), it is better to ground the esd protection to the board ground rather than any local ground (example isolated shield or audio ground). 7.2.5.2 miscellaneous emc guidelines to mitigate esd immunity ? avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near pcb edges. ? add high frequency filtering: decoupling capacitors close to the receivers rather than close to the drivers to minimize esd coupling. ? put a ground (guard) ring around the entire periphery of the pcb to act as a lightning rod. ? connect the guard ring to the pcb ground plane to provide a low impedance path for esd-coupled current on the ring. ? fill unused portions of the pcb with ground plane. ? minimize circuit loops between power and ground by using multilayer pcb with dedicated power and ground planes. ? shield long line length (strip lines) to minimize radiated esd. ? avoid running traces over split ground planes. it is better to use a bridge connecting the two planes in one area. minimize such inductance by optimizing layout keep distance between protected circuit and external protection keep protection closed by connector external external protection stub inductance ground inductance signal esd strike vcc connector stub inductance stub inductance bypass capacitor 0.1 f (minimum) m interconnection inductance vcc vcc signal protected circuit sprs906_pcb_esd_01 381 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-11. trace examples ? always route signal traces and their associated ground returns as close to one another as possible to minimize the loop area enclosed by current flow: ? at high frequencies current follows the path of least inductance. ? at low frequencies current flows through the path of least resistance. 7.2.5.3 esd protection system design consideration esd protection system design consideration is covered in section 7.5.2.2 of this document. the following are additional considerations for esd protection in a system. ? metallic shielding for both esd and emi ? chassis gnd isolation from the board gnd ? air gap designed on board to absorb esd energy ? clamping diodes to absorb esd energy ? capacitors to divert esd energy ? the use of external esd components on the dp/dm lines may affect signal quality and are not recommended. 7.2.6 emi / emc issues prevention all high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed by the emc regulations if some preventative steps are not taken. likewise, analog and digital circuits can be susceptible to interference from the outside world and picked up by the circuitry interconnections. to minimize the potential for emi/emc issues, the following guidelines are recommended to be followed. 7.2.6.1 signal bandwidth to evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth f bw with respect to its rise time, t r : f bw 0.35 / t r this frequency actually corresponds to the break point in the signal spectrum, where the harmonics start to decay at 40 db per decade instead of 20 db per decade. bad better sprs906_pcb_emc_01 382 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.2.6.2 signal routing 7.2.6.2.1 signal routing ? sensitive signals and shielding keep radio frequency (rf) sensitive circuitry (like gps receivers, gsm/wcdma, bluetooth/wlan transceivers, frequency modulation (fm) radio) away from high-speed ics (the device, power and audio manager, chargers, memories, and so forth) and ideally on the opposite side of the pcb. for improved protection it is recommended to place these emission sources in a shield can. if the shield can have a removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid. leave some space between the lid and the components under it to limit the high-frequency currents induced in the lid. limit the shield size to put any potential shield resonances above the frequencies of interest; see figure 7-8 , typical impedance profile of a capacitor . 7.2.6.2.2 signal routing ? outer layer routing in case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to route only static signals and ensure that these static signals do not carry any high-frequency components (due to parasitic coupling with other signals). in case of long traces, make provision for a bypass capacitor near the signal source. routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged, because their emissions energy is concentrated at the discrete harmonics and can become significant even with poor radiators. coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is effective only if the distance between the trace sides and the ground is smaller that the trace height above the ground reference plane. for modern multilayer pcbs this is often not possible, so coplanar shielding will not be effective. do not route high-frequency traces near the periphery of the pcb, as the lack of a ground reference near the trace edges can increase emi: see section 7.2.6.3 , ground guidelines . 7.2.6.3 ground guidelines 7.2.6.3.1 pcb outer layers ideally the areas on the top and bottom layers of the pcb that are not enclosed by a shield should be filled with ground after the routing is completed and connected with an adequate number of vias to the ground on the inner ground planes. 7.2.6.3.2 metallic frames ensure that all metallic parts are well connected to the pcb ground (like lcd screens metallic frames, antennas reference planes, connector cages, flex cables grounds, and so forth). if using flex pcb ribbon cables to bring high-frequency signals off the pcb, ensure they are adequately shielded (coaxial cables or flex ribbons with a solid reference ground). 7.2.6.3.3 connectors for high-frequency signals going to connectors choose a fully shielded connector, if possible (for example, sd card connectors). for signals going to external connectors or which are routed over long distances, it is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (rc) combinations or lossy ferrite inductors). these filters will help to prevent emissions from the board and can also improve the immunity from external disturbances. 7.2.6.3.4 guard ring on pcb edges the major advantage of a multilayer pcb with ground-plane is the ground return path below each and every signal or power trace. as shown in figure 7-12 the field lines of the signal return to pcb ground as long as an infinite ground is available. 383 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated traces near the pcb-edges do not have this infinite ground and therefore may radiate more than the others. thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in the vicinity of pcb edges, or, if not avoidable, must be accompanied by a guard ring on the pcb edge. figure 7-12. field lines of a signal above ground figure 7-13. guard ring routing the intention of the guard ring is that hf-energy, that otherwise would have been emitted from the pcb edge, is reflected back into the board where it partially will be absorbed. for this purpose ground traces on the borders of all layers (including power layer) must be applied as shown in figure 7-13 . as these traces must have the same (hf ? ) potential as the ground plane they must be connected to the ground plane at least every 10 mm. 7.2.6.3.5 analog and digital ground for the optimum solution, the agnd and the dgnd planes must be connected together at the power supply source in a same point. this ensures that both planes are at the same potential, while the transfer of noise from the digital to the analog domain is minimized. 7.3 core power domains this section provides boundary conditions and theoretical background to be applied as a guide for optimizing a pcb design. the decoupling capacitor and pdn characteristics tables shown below give recommended capacitors and pcb parameters to be followed for schematic and pcb designs. board designs that meet the static and dynamic pdn characteristics shown in tables below will be aligned to the expected pdn performance needed to optimize soc performance. 7.3.1 general constraints and theory ? max pcb static/dc voltage drop (ird) budget of 1.5% of supply voltage when using ti recommended pmics without remote sensing as measured from pmic ? s power inductor and filter capacitor node to processor input including any ground return losses. ? max pcb static/dc voltage drop (ird) budget can be relaxed to 7.5% of supply voltage when using pmics with remote sensing at the load as measured from pmic ? s power inductor and filter capacitor node to device ? s supply input including any ground return losses. signal power ground signal sprs906_pcb_emc_03 sprs906_pcb_emc_02 384 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? pmic component dm and guidelines should be referenced for the following: ? routing remote feedback sensing to optimize per each smps ? s implementation ? selecting power filtering capacitor values and pcb placement. ? max effective resistance (reff) budget can range from 4 ? 100m ? for key device power rails not including ground returns depending upon maximum load currents and maximum dc voltage drop budget (as discussed above). ? max device supply input voltage difference budget of 5mv under max current loading shall be maintained across all balls connected to a common power rail. this represents any voltage difference that may exist between a remote sense point to any power input. ? max pcb loop inductance (ll) budget between device ? s power inputs and local bulk and high frequency decoupling capacitors including ground returns should range from 0.4 ? 2.5nh depending upon maximum transient load currents. ? max pcb dynamic/ac peak-to-peak transient noise voltage budgets between pmic and device including ground returns are as follows: ? +/-3% of nominal supply voltage for frequencies below the pmic bandwidth (typ fpmic ~ 200khz) ? +/-5% of nominal supply voltage for frequencies between fpmic to fpcb (typ 20 ? 100mhz) ? max pcb impedance (z) vs frequency (f) budget between device ? s power inputs and pmic ? s output power filter node including ground return is determined by applying the frequency domain target impedance method to determine the pcb ? s maximum frequency of interest (fpcb). ideally a properly designed and decoupled pdn will exhibit smoothly increasing z vs. f curve. there are 2 general regions of interest as can be seen in figure 7-14 . ? 1 st area is from dc (0hz) up to fpmic (typ a few 100 khz) where a pmic ? s transient response characteristic (i.e. switching freq, compensation loop bw) dominate. a pdn ? s z is typically very low due to power filtering & bulk capacitor values when pdn has very low trace resistance (i.e. good reff performance). the goal is to maintain a smoothly increasing z that is less than zt1 over this low frequency range. this will ensure that a max transient current event will not cause a voltage drop more than the pmic ? s current step response can support (typ 3%). ? 2 nd area is from fpmic up to fpcb (typ 20-100mhz) where a pcb ? s inherent characteristics (i.e. parasitic capacitance, planar spreading inductances) dominate. a pdn ? s z will naturally increase with frequency. at frequencies between fpmic up to fpcb, the goal is to maintain a smoothly increasing z to be less than zt2. this will ensue that the high frequency content of a max transient current event will not cause a voltage drop to be more than 5% of the min supply voltage. 385 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-14. pdn ? s target impedance 1.voltage rail drop includes regulation accuracy, voltage distribution drops, and all dynamic events such as transient noise, ac ripple, voltage dips etc. 2.typical max transient current is defined as 50% of max current draw possible. 7.3.2 voltage decoupling recommended power supply decoupling capacitors main characteristics for commercial products whose ambient temperature is not to exceed +85c are shown in table below: table 7-1. commercial applications recommended decoupling capacitors characteristics (1) (2) (3) value voltage [v] package stability dielectric capacitanc e tolerance temp range [ c] temp sensitivity [%] reference 22 f 6,3 0603 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm188r60j226mea0l 10 f 4,0 0402 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm155r60g106me44 4.7 f 6,3 0402 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm155r60j475me95 2.2 f 6,3 0402 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm155r60j225me95 1 f 6,3 0201 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm033r60j105mea2 386 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-1. commercial applications recommended decoupling capacitors characteristics (1) (2) (3) (continued) value voltage [v] package stability dielectric capacitanc e tolerance temp range [ c] temp sensitivity [%] reference 470nf 6,3 0201 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm033r60g474me90 220nf 6,3 0201 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm033r60j224me90 100nf 6,3 0201 class 2 x5r - / + 20% -55 to + 85 - / + 15 grm033r60j104me19 (1) minimum value for each pcb capacitor: 100 nf. (2) among the different capacitors, 470 nf is recommended (not required) to filter at 5-mhz to 10-mhz frequency range. (3) in comparison with the eia class 1 dielectrics, class 2 dielectric capacitors tend to have severe temperature drift, high dependence of capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with aging due to gradual change of crystal structure. aging causes gradual exponential loss of capacitance and decrease of dissipation factor. recommended power supply decoupling capacitors main characteristics for automotive products are shown in table below: table 7-2. automotive applications recommended decoupling capacitors characteristics (1) (2) value voltage [v] package aec-q200 dielectric capacitance tolerance temp range [ c] temp sensitivity [%] reference 22 f 10 1206 yes x7r - / + 10% -55 to + 125 - / + 15 gcm31cr71a226ke02 10 f 10 0805 yes x7r - / + 10% -55 to + 125 - / + 15 gcm21br71a106ke22 4.7 f 10 0805 yes x7s - / + 10% -55 to + 125 - / + 22 gcm21bc71a475ka73 2.2 f 6,3 0603 yes x7r - / + 10% -55 to + 125 - / + 15 gcm188r70j225ke22 1 f 10 0402 yes x7s - / + 10% -55 to + 125 - / + 22 gcm155c71a105ke38 470nf 10 0402 yes x7s - / + 10% -55 to + 125 - / + 22 gcm155c71a474ke36 220nf 25 0603 yes x7r - / + 10% -55 to + 125 - / + 15 gcm155r71a104ka55 100nf 10 0402 yes x7r - / + 10% -55 to + 125 - / + 15 gcm155r71c104ma55 100nf 6.3 0201 yes x7s - / + 10% -55 to + 125 - / + 15 gcm033c70j104k 1.0 f 10 3t-0805 (3) yes - / + 20% -55 to + 125 nfm21hc105r1c3 0.47 f 10 3t-0805 (3) yes - / + 20% -55 to + 125 nfm21hc474r1c3 0.22 f 10 3t-0805 (3) yes - / + 20% -55 to + 125 nfm21hc224r1c3 0.1 f 10 3t-0805 (3) yes - / + 20% -55 to + 125 nfm21hc104r1c3 (1) minimum value for each pcb capacitor: 100 nf. (2) among the different capacitors, 470 nf is recommended (not required) to filter at 5-mhz to 10-mhz frequency range. (3) 3t designates this as a "3-terminal, low inductance type package ? . 7.3.3 static pdn analysis one power net parameter derived from a pcb ? s pdn static analysis is the effective resistance (reff). this is the total pcb power net routing resistance that is the sum of all the individual power net segments used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current sensing resistor) that may be installed between the pmic outputs and processor inputs. 7.3.4 dynamic pdn analysis three power net parameters derived from a pcb ? s pdn dynamic analysis are the loop inductance (ll), impedance (z) and pcb frequency of interest (fpcb). ? ll values shown are the recommended max pcb trace inductance between a decoupling capacitor ? s power supply and ground reference terminals when viewed from the decoupling capacitor with a ? theoretical shorted ? applied across the processor ? s supply inputs to ground reference. 387 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? z values shown are the recommended max pcb trace impedances allowed between fpmic up to fpcb frequency range that limits transient noise drops to no more than 5% of min supply voltage during max transient current events. ? fpcb (frequency of interest) is defined to be a power rail ? s max frequency after which adding a reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance below the desired impedance target (zt2). this is due to the dominance of the pcb ? s parasitic planar spreading and internal package inductances. table 7-3. recommended pdn and decoupling characteristics (1) (2) (3) (4) pdn analysis: static dynamic number of recommended decoupling capacitors per supply supply max r eff (5) [m ] dec. cap. max ll (6) [nh] max impedance [m ] frequency range of interest [mhz] 100 nf 220 nf 470 nf 1 f 2.2 f 4.7 f 10 f 22 f vdd_dsp 22 2.5 54 20 6 1 1 1 1 1 1 vdd 18 2 57 20 6 1 1 1 1 1 vdds_ddr1 33 2.5 200 100 8 3 2 2 1 cap_vbbldo_dsp n/a 6 n/a n/a 1 cap_vbbldo_gpu n/a 6 n/a n/a 1 cap_vbbldo_iva n/a 6 n/a n/a 1 cap_vbbldo_mpu n/a 6 n/a n/a 1 cap_vddram_core1 n/a 6 n/a n/a 1 cap_vddram_core3 n/a 6 n/a n/a 1 cap_vddram_core4 n/a 6 n/a n/a 1 cap_vddram_dsp n/a 6 n/a n/a 1 cap_vddram_gpu n/a 6 n/a n/a 1 cap_vddram_iva n/a 6 n/a n/a 1 cap_vddram_mpu n/a 6 n/a n/a 1 (1) for more information on peak-to-peak noise values, see the recommended operating conditions table of the specifications chapter. (2) esl must be as low as possible and must not exceed 0.5 nh. (3) the pdn (power delivery network) impedance characteristics are defined versus the device activity (that runs at different frequency) based on the recommended operating conditions table of the specifications chapter. (4) maximum static voltage drop allowed drives the maximum acceptable power net resistance (r eff ) between the pmic or the external smps and the processor power balls. (5) maximum r eff (from smps to processor) allows for max supply voltage drop when both remote voltage sensing very close to processor power balls and ti recommended pmics are used. (6) maximum loop inductance to each high-frequency (30-70mhz) decoupling capacitor. 7.3.5 power supply mapping tps65919 or lp8733 are the power management ics (pmics) that should be used for the device designs. ti requires use of these pmics for the following reasons: ? ti has validated their use with the device ? board level margins including transient response and output accuracy are analyzed and optimized for the entire system ? support for power sequencing requirements (refer to section 5.10.3 power supply sequences) ? support for adaptive voltage scaling (avs) class 0 requirements, including ti provided software ? remote sensing at point of load with output voltage compensation allows for the maximum ir drop budget 388 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated whenever one smps supplies multiple soc voltage domains from a common power rail, the most stringent pdn guideline across the voltage domains being combined should be applied to the common power rail. it is possible that some voltage domains on the device are unused in some systems. in such cases, to ensure device reliability, it is still required that the supply pins for the specific voltage domains are connected to some core power supply output. these unused supplies though can be combined with any of the core supplies that are used (active) in the system. e.g. if the dsp domain is not used, it can be combined with the core domain, thereby having a single power supply driving the combined core and dsp domains. for the combined rail, the following relaxations do apply: ? the avs voltage of active voltage domain in the combined rail needs to be used to set the power supply ? the decoupling capacitance should be set according to the active voltage domain in the combined rail ? the pdn guideline should be set according to the active voltage domain in the combined rail table 7-4 illustrates the approved and validated power supply connections to the device for the smps outputs of the tps656919 pmic. table 7-4. tps65919 power supply connections (1) smps valid combination tps65919 current limitation (2) (3) smps1 vd_core 3.5a smps2 free (ddr memory) 3.5a smps3 vd_dsp 3a smps4 vdds18v 1.5a (1) power consumption is highly application-specific. separate analysis must be performed to ensure output current ratings (average and peak) is within the limits of the pmic for all rails of the device. (2) refer to the pmic data manual for the latest tps65919 specifications. (3) a product ? s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power dissipation below the full pmic capacity in order to not exceed recommended soc max tj. table 7-5 illustrates the approved and validated power supply connections to the device for the smps outputs of the lp8733 pmic. table 7-5. lp8733 power supply connections smps valid combination lp8733 current limitation (1) (2) smps1 vd_core 3a smps2 vd_dsp 3a (1) refer to the lp8733 data manual for exact current rating limitations, including assumed vin and other parameters. values provided in this table are for comparison purposes. (2) highly application-specific. separate analysis must be performed to ensure average and peak power is within the limits of the pmic. 7.3.6 dpll voltage requirement the voltage input to the dplls has a low noise requirement. board designs should supply these voltage inputs with a low noise ldo to ensure they are isolated from any potential digital switching noise. the tps65919 pmic ldoln output is specifically designed to meet this low noise requirement. 389 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated note for more information about input voltage sources, see section 5.10.4.3 dplls, dlls specifications . table 7-6 presents the voltage inputs that supply the dplls. table 7-6. input voltage power supplies for the dplls power supply dplls vdda_per dpll_per and per hsdivider analog power supply vdda_ddr dpll_ddr and ddr hsdivider analog power supply vdda_debug dpll_debug analog power supply vdda_core_gmac dpll_core and hsdivider analog power supply vdda_gpu dpll_gpu analog power supply vdda_video dpll_video1 analog power supply vdda_mpu_abe dpll_mpu and dpll_abe analog power supply vdda_osc not dpll input but is required to be supplied by low noise input voltage vdda_dsp_iva dsp pll and iva pll analog power supply 7.3.7 loss of input power event a few key pdn design items needed to enable a controlled and compliant soc power down sequence for a ? loss of input power ? event are: ? ? loss of input power ? early warning ? ti evm and reference design study schs and pdns achieve this by using the first stage converter ? s (i.e. lm536033-q1) power good status output to enable and disable the second stage pmic devices (i.e. tps65917/919, lp8733, and lp8732). if a different first stage converter is used, care must be taken to ensure an adequate ? pg_status ? or ? vbatt_status ? signal is provided that can disable second stage pmic to begin a controlled and compliant soc power down sequence. the total elapsed time from asserting ? pg_status ? low until soc ? s pmic input voltage reaches minimum level of 2.75 v should be minimum of 1.5ms and 2ms preferred. ? maximize discharge time of first stage vout (vsys_3v3 power rail = input voltage to soc pmic). ? ti evm and reference design study schs and pdns achieve this by opening an in-line load switch immediately upon ? pg_status ? low assertion in order to remove the soc ? s 3.3v io load current from vsys_3v3. this will extend the vsys_3v3 power rail ? s discharge time in order to maximize elapsed time for allowing soc pmic to execute a controlled and compliant power down sequence. care should be taken to either disable or isolate any additional peripheral components that may be loading the vsys_3v3 rail as well. ? sufficient bulk decoupling capacitance on the first stage vout (vsys_3v3 per pdn) that allows for desired 1.5 ? 2 ms elapsed time as described above. ? ti evm and reference design study schs and pdns achieve this by using 200 f of total capacitance on vsys_3v3. the first stage converter (i.e. lm536033-q1) can typically drive a max of 400 f to help extend vsys_3v3 discharge time for a compliant soc power down sequence. ? optimizing the second stage soc pmic ? s otp settings that determines soc power up and down sequences and total elapsed time needed for a controlled sequence. ? ti evm and reference design study schs and pdns achieve this by using optimized otps per the sch and components used. the definition of these otps is captured in the detailed timing diagrams for both power up and down sequences. the pdn diagram typically shows a recommended pmic otp id based upon the soc and ddr memory types. 390 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.3.8 example pcb design the following sections describe an example pcb design and its resulting pdn performance for the vdd processor power domain. note materials presented in this section are based on generic pdn analysis on pcb boards and are not specific to systems integrating the device. 7.3.8.1 example stack-up layer assignments: ? layer top: signal and segmented power plane ? processor and pmic components placed on top-side ? layer 2: gnd plane1 ? layer 3: signals ? layer n: power plane1 ? layer n+1: power plane 2 ? layer n+2: signal ? layer n+3: gnd plane2 ? layer bottom: signal and segmented power planes ? decoupling caps, etc. via technology: through-hole copper weight: ? ? oz for all signal layers. ? 1-2oz for all power plane for improved pcb heat spreading. 7.3.8.2 vdd example analysis maximum acceptable pcb resistance (r eff ) between the pmic and processor input power balls should not exceed 10m . maximum decoupling capacitance loop inductance (ll) between processor input power balls and decoupling capacitances should not exceed 2.0nh (esl not included) impedance target for key frequency of interest between processor input power balls and pmic ? s smps output power balls should not exceed 57m at 20mhz. table 7-7. example pcb vdd pi analysis summary parameter recommendation example pcb opp opp_nom clocking rate 266 mhz voltage level 1 v 1 v max current draw 1 a 1 a max effective resistance: power inductor segment total r eff 10m 9.7 m max loop inductance 2.0nh 0.97 ? 1.75nh impedance target 57m f < 20mhz 57m f < 20mhz 391 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-15 show a pcb layout example and the resulting pi analysis results. figure 7-15. vdd simplified sch diagram note pcb etch resistance breakdown, pdn effective resistance, and vdd routings are under development! ir drop: vdd (pcb rev oct25, cad spsi v13.1.1) ? source conditions: 1v @ 1a ? power plane/trace effective resistances ? from pmic smps to soc load = 9.7mohm ? from power inductor to soc load = 6mohm ? "open-loop" voltage/ir drop for 1a = 6mv smps2 c1014 47uf, 6.3v, x7r, 1210 gcm32er70j476me19 l1002 1.0uh, 4.5a, 1616 ihlp-1616aber1r0m11 core_vdd soc vdd smps2_sw c363 , 364, 386, 388 , 390, 498 0.1uf, 16v, x7r, 0402 gcm155r71c104ka55 c395 0.22uf, 25v, x7r, 0603 gcm188r71e224ka55 c394 0.47uf, 16v, x7r, 0603 gcm188r71c474ka55 c393 1.0uf, 16v, x7r, 0603 gcm188r71c105ka64 c456 2.2uf, 6.3v, x7r, 0603 gcm188r70j225ke22 c487 4.7uf, 16v, x7r, 0805 gcm21br71c475ka73 pmic 392 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-16. vdd voltage/ir drop [all layers] dynamic analysis of this pcb design for the core power domain determined the vdd decoupling capacitor loop inductance and impedance vs frequency analysis shown below. as you can see, the loop inductance values ranged from 0.97 ? 1.75nh and were less than maximum 2.0nh recommended. note comparing loop inductances for capacitors at different distances from the soc ? s input power balls shows an 18% reduction for caps placed closer. this was derived by averaging the inductances for the 3 caps with distances over 800mils (avg ll = 1.33nh) vs the 3 caps with distances less than 600mils (avg ll = 1.096nh). table 7-8. rail - vdd cap ref des model port # loop inductacne [nh] footprint types pcb side distance to ball-field [mils] value [ f] size c487 10 0.97 4vwse top 521 4.7 0805 c393 6 1.11 4vwse bottom 358 1.0 0603 c394 7 1.12 4vwse bottom 357 0.47 0603 c456 9 1.13 4vwse bottom 403 2.2 0603 c386 3 1.16 2vwse bottom 40 0.1 0402 c395 8 1.18 4vwse bottom 460 0.22 0603 c363 1 1.46 2vwse bottom 40 0.1 0402 c390 5 1.48 2vwse bottom 40 0.1 0402 c364 2 1.74 2vwse bottom 40 0.1 0402 c498 11 1.74 2vwse bottom 40 0.1 0402 c388 4 1.75 2vwse bottom 40 0.1 0402 393 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated loop inductance range: 0.97 ? 1.75nh figure 7-17. vdd decoupling cap loop inductances figure 7-18 shows vdd impedance vs frequency characteristics. 394 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-18. vdd impedance vs frequency 7.4 single-ended interfaces 7.4.1 general routing guidelines the following paragraphs detail the routing guidelines that must be observed when routing the various functional lvcmos interfaces. 9.9mohm @ 10mhz 27mohm @ 20mhz 173mohm @ 100mhz 87mohm @ 50mhz 395 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? line spacing: ? for a line width equal to w, the spacing between two lines must be 2w, at least. this minimizes the crosstalk between switching signals between the different lines. on the pcb, this is not achievable everywhere (for example, when breaking signals out from the device package), but it is recommended to follow this rule as much as possible. when violating this guideline, minimize the length of the traces running parallel to each other (see figure 7-19 ). figure 7-19. ground guard illustration ? length matching (unless otherwise specified): ? for bus or traces at frequencies less than 10 mhz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 25 mm. ? for bus or traces at frequencies greater than 10 mhz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 2.5 mm. ? characteristic impedance ? unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35- and 65- . ? multiple peripheral support ? for interfaces where multiple peripherals have to be supported in the star topology, the length of each branch has to be balanced. before closing the pcb design, it is highly recommended to verify signal integrity based on simulations including actual pcb extraction. 7.4.2 qspi board design and layout guidelines the following section details the routing guidelines that must be observed when routing the qspi interfaces. ? the qspi1_sclk output signal must be looped back into the qspi1_rtclk input. ? the signal propagation delay from the qspi1_sclk ball to the qspi device clk input pin (a to c) must be approximately equal to the signal propagation delay from the qspi device clk pin to the qspi1_rtclk ball (c to d). ? the signal propagation delay from the qspi device clk pin to the qspi1_rtclk ball (c to d) must be approximately equal to the signal propagation delay of the control and data signals between the qspi device and the soc device (e to f, or f to e). ? the signal propagation delay from the qspi1_sclk signal to the series terminators (r2 = 10 ) near the qspi device must be < 450ps (~7cm as stripline or ~8cm as microstrip) ? 50 pcb routing is recommended along with series terminations, as shown in figure 7-20 . w d+ s = 2 w = 200 m sprs906_pcb_se_gnd_01 396 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? propagation delays and matching: ? a to c = c to d = e to f. ? matching skew: < 60ps ? a to b < 450ps ? b to c = as small as possible ( < 60ps) figure 7-20. qspi interface high level schematic note *0 resistor (r1), located as close as possible to the qspi1_sclk pin, is placeholder for fine- tuning if needed. 7.5 differential interfaces 7.5.1 general routing guidelines to maximize signal integrity, proper routing techniques for differential signals are important for high-speed designs. the following general routing guidelines describe the routing guidelines for differential lanes and differential signals. ? as much as possible, no other high-frequency signals must be routed in close proximity to the differential pair. ? must be routed as differential traces on the same layer. the trace width and spacing must be chosen to yield the differential impedance value recommended. ? minimize external components on differential lanes (like external esd, probe points). ? through-hole pins are not recommended. ? differential lanes mustn ? t cross image planes (ground planes). ? no sharp bend on differential lanes. a b c d e f qspi1_sclkqspi1_rtclk r2 r2 r1 qspi deviceclock input qspi deviceiox, cs# qspi1_d[x], qspi1_cs[y] 0 * 10 10 locate both r2 resistorsclose together near the qspi device sprs906_pcb_qspi_01 397 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated ? number of vias on the differential pairs must be minimized, and identical on each line of the differential pair. in case of multiple differential lanes in the same interface, all lines should have the same number of vias. ? shielded routing is to be promoted as much as possible (for instance, signals must be routed on internal layers that are inside power and/or ground planes). 7.5.2 usb 2.0 board design and layout guidelines this section discusses schematic guidelines when designing a universal serial bus (usb) system. 7.5.2.1 background clock frequencies generate the main source of energy in a usb design. the usb differential dp/dm pairs operate in high-speed mode at 480 mbps. system clocks can operate at 12 mhz, 48 mhz, and 60 mhz. the usb cable can behave as a monopole antenna; take care to prevent rf currents from coupling onto the cable. when designing a usb board, the signals of most interest are: ? device interface signals: clocks and other signal/data lines that run between devices on the pcb. ? power going into and out of the cable: the usb connector socket pin 1 (vbus ) may be heavily filtered and need only pass low frequency signals of less than ~100 khz. the usb socket pin 4 (analog ground) must be able to return the current during data transmission, and must be filtered sparingly. ? differential twisted pair signals going out on cable, dp and dm: depending upon the data transfer rate, these device terminals can have signals with fundamental frequencies of 240 mhz (high speed), 6 mhz (full speed), and 750 khz (low speed). ? external crystal circuit (device terminals xi and x0): 12 mhz, 19.2 mhz, 24 mhz, and 48 mhz fundamental. when using an external crystal as a reference clock, a 24 mhz and higher crystal is highly recommended. 7.5.2.2 usb phy layout guide the following sections describe in detail the specific guidelines for usb phy layout. 7.5.2.2.1 general routing and placement use the following routing and placement guidelines when laying out a new design for the usb physical layer (phy). these guidelines help minimize signal quality and electromagnetic interference (emi) problems on a four-or-more layer evaluation module (evm). ? place the usb phy and major components on the un-routed board first. for more details, see section 7.5.2.2.2.3 . ? route the high-speed clock and high-speed usb differential signals with minimum trace lengths. ? route the high-speed usb signals on the plane closest to the ground plane, whenever possible. ? route the high-speed usb signals using a minimum of vias and corners. this reduces signal reflections and impedance changes. ? when it becomes necessary to turn 90 , use two 45 turns or an arc instead of making a single 90 turn. this reduces reflections on the signal traces by minimizing impedance discontinuities. ? do not route usb traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ic ? s that use or duplicate clock signals. ? avoid stubs on the high-speed usb signals because they cause signal reflections. if a stub is unavoidable, then the stub should be less than 200 mils. ? route all high-speed usb signal traces over continuous planes (v cc or gnd), with no interruptions. avoid crossing over anti-etch, commonly found with plane splits. 398 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.5.2.2.2 specific guidelines for usb phy layout the following sections describe in detail the specific guidelines for usb phy layout. 7.5.2.2.2.1 analog, pll, and digital power supply filtering to minimize emi emissions, add decoupling capacitors with a ferrite bead at power supply terminals for the analog, phase-locked loop (pll), and digital portions of the chip. place this array as close to the chip as possible to minimize the inductance of the line and noise contributions to the system. an analog and digital supply example is shown in figure 7-21 . in case of multiple power supply pins with the same function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in addition to the ferrite bead. this array of caps and ferrite bead improve emi and jitter performance. take both emi and jitter into account before altering the configuration. figure 7-21. suggested array capacitors and a ferrite bead to minimize emi consider the recommendations listed below to achieve proper esd/emi performance: ? use a 0.01 f cap on each cable power vbus line to chassis gnd close to the usb connector pin. ? use a 0.01 f cap on each cable ground line to chassis gnd next to the usb connector pin. ? if voltage regulators are used, place a 0.01 f cap on both input and output. this is to increase the immunity to esd and reduce emi. for other requirements, see the device-specific datasheet. 7.5.2.2.2.2 analog, digital, and pll partitioning if separate power planes are used, they must be tied together at one point through a low-impedance bridge or preferably through a ferrite bead. care must be taken to capacitively decouple each power rail close to the device. the analog ground, digital ground, and pll ground must be tied together to the low- impedance circuit board ground plane. 7.5.2.2.2.3 board stackup because of the high frequencies associated with the usb, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown in figure 7-22 . analog power supply soc board ferrite bead digital power supply ferrite bead 0.1 f 0.01 f 0.001 f 1 f 0.1 f 0.01 f 0.001 f 1 f sprs906_pcb_usb20_01 agnd dgnd 399 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-22. four-layer board stack-up the majority of signal traces should run on a single layer, preferably signal1. immediately next to this layer should be the gnd plane, which is solid with no cuts. avoid running signal traces across a split in the ground or power plane. when running across split planes is unavoidable, sufficient decoupling must be used. minimizing the number of signal vias reduces emi by reducing inductance at high frequencies. 7.5.2.2.2.4 cable connector socket short the cable connector sockets directly to a small chassis ground plane (gnd strap ) that exists immediately underneath the connector sockets. this shorts emi (and esd) directly to the chassis ground before it gets onto the usb cable. this etch plane should be as large as possible, but all the conductors coming off connector pins 1 through 6 must have the board signal gnd plane run under. if needed, scoop out the chassis gnd strap etch to allow for the signal ground to extend under the connector pins. note that the etches coming from pins 1 and 4 (vbus power and gnd) should be wide and via-ed to their respective planes as soon as possible, respecting the filtering that may be in place between the connector pin and the plane. see figure 7-23 for a schematic example. place a ferrite in series with the cable shield pins near the usb connector socket to keep emi from getting onto the cable shield. the ferrite bead between the cable shield and ground may be valued between 10 ? and 50 ? at 100 mhz; it should be resistive to approximately 1 ghz. to keep emi from getting onto the cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power, vbus, near the usb connector pin 1. the ferrite bead between connector pin 1 and bus power may be valued between 47 ? and approximately 1000 ? at 100 mhz. it should continue being resistive out to approximately 1 ghz, as shown in figure 7-23 . signal 1 power plane gnd plane signal 2 sprs906_pcb_usb20_02 400 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-23. usb connector 7.5.2.2.2.5 clock routings to address the system clock emissions between devices, place a ~10 to 130 ? resistor in series with the clock signal. use a trial and error method of looking at the shape of the clock waveform on a high-speed oscilloscope and of tuning the value of the resistance to minimize waveform distortion. the value on this resistor should be as small as possible to get the desired effect. place the resistor close to the device generating the clock signal. if an external crystal is used, follow the guidelines detailed in the selection and specification of crystals for texas instruments usb 2.0 devices ( slla122 ). when routing the clock traces from one device to another, try to use the 3w spacing rule. the distance from the center of the clock trace to the center of any adjacent signal trace should be at least three times the width of the clock trace. many clocks, including slow frequency clocks, can have fast rise and fall times. using the 3w rule cuts down on crosstalk between traces. in general, leave space between each of the traces running parallel between the devices. avoid using right angles when routing traces to minimize the routing distance and impedance discontinuities. for further protection from crosstalk, run guard traces beside the clock signals (gnd pin to gnd pin), if possible. this lessens clock signal coupling, as shown in figure 7-24 . figure 7-24. 3w spacing rule u2 ferrite bead vbus u1 usb socket 5 4 3 2 1 6 shield_gnd gnd dpdm +5 v shield_gnd ferrite bead sprs906_pcb_usb20_03 trace 3w 3w w sprs906_pcb_usb20_04 401 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.5.2.2.2.6 crystals/oscillator keep the crystal and its load capacitors close to the usb phy pins, xi and xo (see figure 7-25 ). note that frequencies from power sources or large capacitors can cause modulations within the clock and should not be placed near the crystal. in these instances, errors such as dropped packets occur. a placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup. power is proportional to the current squared. the current is i = c dv/dt , because dv/dt is a function of the phy, current is proportional to the capacitive load. cutting the load to 1/2 decreases the current by 1/2 and the power to 1/4 of the original value. for more details on crystal selection, see the selection and specification of crystals for texas instruments usb 2.0 devices ( slla122 ). figure 7-25. power supply and clock connection to the usb phy 7.5.2.2.2.7 dp/dm trace place the usb phy as close as possible to the usb 2.0 connector. the signal swing during high-speed operation on the dp/dm lines is relatively small (400 mv 10%), so any differential noise picked up on the twisted pair can affect the received signal. when the dp/dm traces do not have any shielding, the traces tend to behave like an antenna and picks up noise generated by the surrounding components in the environment. to minimize the effect of this behavior: ? dp/dm traces should always be matched lengths and must be no more than 4 inches in length; otherwise, the eye opening may be degraded (see figure 7-26 ). ? route dp/dm traces close together for noise rejection on differential signals, parallel to each other and within two mils in length of each other. the measurement for trace length must be started from device's balls. ? a high-speed usb connection is made through a shielded, twisted pair cable with a differential characteristic impedance of 90 ? 15%. in layout, the impedance of dp and dm should each be 45 ? 10%. ? dp/dm traces should not have any extra components to maintain signal integrity. for example, traces cannot be routed to two usb connectors. power pins usb phy 0.1 f 0.001 f x1x0 xtal sprs906_pcb_usb20_05 402 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-26. usb phy connector and cable connector 7.5.2.2.2.8 dp/dm vias when a via must be used, increase the clearance size around it to minimize its capacitance. each via introduces discontinuities in the signal ? s transmission line and increases the chance of picking up interference from the other layers of the board. be careful when designing test points on twisted pair lines; through-hole pins are not recommended. 7.5.2.2.2.9 image planes an image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing plane. use of image planes provides a low impedance, shortest possible return path for rf currents. for a usb board, the best image plane is the ground plane because it can be used for both analog and digital circuits. ? do not route traces so they cross from one plane to the other. this can cause a broken rf return path resulting in an emi radiating loop as shown in figure 7-27 . this is important for higher frequency or repetitive signals. therefore, on a multi-layer board, it is best to run all clock signals on the signal plane above a solid ground plane. ? avoid crossing the image power or ground plane boundaries with high-speed clock signal traces immediately above or below the separated planes. this also holds true for the twisted pair signals (dp, dm). any unused area of the top and bottom signal layers of the pcb can be filled with copper that is connected to the ground plane through vias. minimize this distance usb phy connector d+ d- vbus gnd d- d+ cable connector sprs906_pcb_usb20_06 403 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-27. do not cross plane boundaries ? do not overlap planes that do not reference each other. for example, do not overlap a digital power plane with an analog power plane as this produces a capacitance between the overlapping areas that could pass rf emissions from one plane to the other, as shown in figure 7-28 . figure 7-28. do not overlap planes ? avoid image plane violations. traces that route over a slot in an image plane results in a possible rf return loop, as shown in figure 7-29 . analog power plane unwanted capacitance digital power plane sprs906_pcb_usb20_08 don't do sprs906_pcb_usb20_07 404 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-29. do not violate image planes 7.5.2.2.2.10 power regulators switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive areas on a circuit board. therefore, the switching power regulator should be kept away from the dp/dm signals, the external clock crystal (or clock oscillator), and the usb phy. 7.5.2.3 references ? usb 2.0 specification , intel, 2000, http://www.usb.org/developers/docs/ ? high speed usb platform design guidelines , intel, 2000, http://www.intel.com/technology/usb/download/usb2dg_r1_0.pdf ? selection and specification of crystals for texas instruments usb 2.0 devices ( slla122 ) 7.5.3 usb 3.0 board design and layout guidelines this section provides the timing specification for the usb3.0 (usb1 in the device) interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. ti has performed the simulation and system design work to ensure the usb3.0 interface requirements are met. the design rules stated within this document are targeted at device mode electrical compliance. host mode and/or systems that do not include the 3m usb cable and far-end 11-inch pcb trace required by device mode compliance testing may not need the complete list of optimizations shown in this document; however, applying these optimizations to host mode systems will lead to optimal device mode performance. 7.5.3.1 usb 3.0 interface introduction the usb 3.0 has two unidirectional differential pairs: txp/txn pair and rxp/rxn pair. ac coupling caps are needed on the board for tx traces. figure 7-30 present high level schematic diagram for usb 3.0 interface. slot in image plane rf return current bad slot in image plane rf return current better sprs906_pcb_usb20_09 405 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-30. usb 3.0 interface high level schematic note esd components should be on a pcb layer next to a system gnd plane layer so the inductance of the via to gnd will be minimal. if vias are used, place the vias near the ac caps or cmfs and under the soc bga, if necessary. figure 7-31 present placement diagram for usb 3.0 interface. figure 7-31. usb 3.0 placement diagram table 7-9. usb1 component reference interface component supplier part number usb3 phy esd ti tpd1e05u06 cmf murata dlw21sn900hq2 c - 100nf (typical size: 0201) device usb_txp0 usb_txn0 usb_rxp0 usb_rxn0 cmf cmf ac caps place near connector, and keep routing short vias (if necessary) vias (if necessary) vias (if necessary) vias (if necessary) usb 3.0 gnd gnd gnd gnd usb 3.0 connector sprs85x_pcb_usb30_1 cmf cmf ac capac cap soc tx soc rx via via via via usb 3.0 connector sprs85x_pcb_usb30_2 406 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.5.3.2 usb 3.0 general routing rules some general routing guidelines regarding usb 3.0: ? avoid crossing splits reference plane(s). ? shorter trace length is preferred. ? minimize the via usage and layer transition ? keep large spacing between tx and rx pairs. ? intra-lane delay mismatch between dp and dm less than 1ps. same for rxp and rxn. ? distance between common mode filter (cmf) and esd protection device should be as short as possible ? distance between esd protection device and usb connector should be as short as possible. ? distance between ac capacitors (tx only) and cmf should be as short as possible. ? usb 3.0 signals should always be routed over an adjacent ground plane. table 7-10 and table 7-11 present routing specification and recommendations for usb1 in the device. table 7-10. usb1 routing specifications parameter min typ max unit device balls to usb 3.0 connector trace length 3500 mils skew within a differential pair 3 6 mils number of stubs allowed on tx/rx traces 0 stubs tx/rx pair differential impedance 83 90 97 number of vias on each tx/rx trace 2 vias differential pair to any other trace spacing 2xds 3xds number of ground plane cuts allowed within usb3 routing region (except for specific ground carving as explained in this document) 0 cuts number of layers between usb3.0 routing region and reference ground plane 0 layers pcb trace width 6 mils pcb bga escape via pad size 18 mils pcb bga escape via hole size 10 mils 1. vias must be used in pairs and spaced equally along a signal path. 2. ds = differential spacing of the traces. 3. exceptions may be necessary in the soc package bga area. 4. gnd guard-bands on the same layer may be closer, but should not be allowed to affect the impedance of the differential pair routing. gnd guard-bands to isolate usb3.0 differential pairs from all other signals are recommended. table 7-11. usb1 routing recommendations item description reason esd location place esd component on same layer as connector (no via or stub to esd component) eliminate reflection loss from via & stub to esd esd part number tpd1e05u06 minimize capacitance (0.42pf) cmf part number dlw21sn900hq2 manufacturer ? s recommended device connector use usb3.0 connector with supporting s-parameter model enable full signal chain simulation carve ground carve gnd underneath ac caps, esd, cmf, and connector minimize capacitance under esd and cmf 407 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-11. usb1 routing recommendations (continued) item description reason round pads minimize pad size and round the corners of the pads for the esd and cmf components minimize capacitance vias max 2 vias per signal trace. if vias are required, place vias close to the ac caps and cmfs. vias under the soc grid array may be used if necessary to route signals away from bga pattern. vias significantly degrade signal integrity at 2.5ghz figure 7-32 presents an example layout, demonstrating the ? carve gnd ? concept. figure 7-32. usb 3.0 example ? carve gnd ? layout 7.5.4 hdmi board design and layout guidelines this section provides the timing specification for the hdmi interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. ti has performed the simulation and system design work to ensure the hdmi interface requirements are met. the design rules stated within this document are targeted at resolutions less than or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization. 7.5.4.1 hdmi interface schematic the hdmi bus is separated into three main sections (hdmi ethernet and the optional audio return channel are not specifically supported by this device): layer2 , gnd: gaps carved in gnd underneath ac caps, cmf, esd, and connector. layer3 , signal: implement as keep-out zone underneath carved gnd areas. layer4 , gnd plane underneath ac caps, cmf, esd, and connector. sprs85x_pcb_usb30_3 top layer : routing from soc through ac caps, cmf, and esd to connector. ac cap cmf cmf ac cap via via via via usb 3.0 connector 408 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 1. transition minimized differential signaling (tmds) high speed digital video interface 2. display data channel (i2c bus for configuration and status exchange between two devices) 3. consumer electronics control (optional) for remote control of connected devices. the ddc and cec are low speed interfaces, so nothing special is required for pcb layout of these signals. the tmds channels are high speed differential pairs and therefore require the most care in layout. specifications for tmds layout are below. figure 7-33 shows the hdmi interface schematic. figure 7-33. hdmi interface high level schematic figure 7-34 presents placement diagram for hdmi interface. figure 7-34. hdmi placement diagram table 7-12. hdmi component reference interface device supplier part number hdmi esd ti tpd1e05u06 cmf murata dlw21sn900hq2 cmf cmf cmf cmf hdmi connector sprs85x_pcb_hdmi_2 device hdmi hdmi_tx*- hdmi_tx*+ cmf place near connector, and keep routing short gnd gnd hdmi connector sprs85x_pcb_hdmi_1 409 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.5.4.2 tmds general routing guidelines the tmds signals are high speed differential pairs. care must be taken in the pcb layout of these signals to ensure good signal integrity. the tmds differential signal traces must be routed to achieve 100 ohms (+/- 10%) differential impedance and 60 ohms (+/-10%) single ended impedance. single ended impedance control is required because differential signals can ? t be closely coupled on pcbs and therefore single ended impedance becomes important. these impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric material. verify with a pcb design tool that the trace geometry for both data signal pairs results in as close to 60 ohms impedance traces as possible. for best accuracy, work with your pcb fabricator to ensure this impedance is met. in general, closely coupled differential signal traces are not an advantage on pcbs. when differential signals are closely coupled, tight spacing and width control is necessary. very small width and spacing variations affect impedance dramatically, so tight impedance control can be more problematic to maintain in production. loosely coupled pcb differential signals make impedance control much easier. wider traces and spacing make obstacle avoidance easier, and trace width variations don ? t affect impedance as much, therefore it ? s easier to maintain accurate impedance over the length of the signal. the wider traces also show reduced skin effect and therefore often result in better signal integrity. some general routing guidelines regarding tmds: ? avoid crossing splits reference plane(s). ? shorter trace length is preferred. ? distance between common mode filter (cmf) and esd protection device should be as short as possible ? distance between esd protection device and hdmi connector should be as short as possible. table 7-13 shows the routing specifications for the tmds signals. table 7-13. tmds routing specifications parameter min typ max unit device balls to hdmi header trace length 4000 mils skew within a differential pair 3 5 mils number of stubs allowed on tmds traces 0 stubs tmds pair differential impedance 90 100 110 tmds single-ended impedance 54 60 66 number of vias on each tmds trace 0 vias tmds differential pair to any other trace spacing (1) (2) (3) 2 ds 3xds mils number of ground plane cuts allowed within hdmi routing region (except for specific ground carving as explained in this document) 0 cuts number of layers between hdmi routing region and reference ground plane 0 layers pcb trace width 4.4 mils (1) ds = differential spacing of the traces. (2) exceptions may be necessary in the soc package bga area. (3) gnd guard-bands may be closer, but should not be allowed to affect the impedance of the differential pair routing. gnd guard-bands to isolate hdmi differential pairs from all other signals is recommended. table 7-14. tdms routing recommendations item description reason esd part number tpd1e05u06 minimize capacitance (0.42pf) 410 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-14. tdms routing recommendations (continued) item description reason carve ground carve gnd underneath esd and cmf minimize capacitance under esd and cmf round pads reduce pad size and round the corners of the pads for the esd and cmf components minimize capacitance routing layer route all signals only on the same layer as soc minimize reflection loss figure 7-35 presents an example layout, demonstrating the ? carve gnd ? concept. figure 7-35. hdmi example ? carve gnd ? layout 7.5.4.3 tpd5s115 the tpd5s115 is an integrated hdmi companion chip solution. the device provides a regulated 5 v output (5vout) for sourcing the hdmi power line. the tpd5s115 exceeds the iec61000-4-2 (level 4) esd protection level. 7.5.4.4 hdmi esd protection device (required) interfaces that connect to a cable such as hdmi generally require more esd protection than can be built into the processor ? s outputs. therefore this hdmi interface requires the use of an esd protection chip to provide adequate esd. when selecting an esd protection chip, choose the lowest capacitance esd protection available to minimize signal degradation. in no case should be esd protection circuit capacitance be more than 5pf. ti manufactures these devices that provide esd protection for hdmi signals such as the tpdxe05u06. for more information see the www.ti.com website. 7.5.4.5 pcb stackup specifications table 7-15 shows the stackup and feature sizes required for hdmi. table 7-15. hdmi pcb stackup specifications parameter min typ max unit pcb routing/plane layers 4 6 - layers top layer : routing from soc through cmf, and esd to connector. layer2 , gnd: gaps carved in gnd underneath, cmf, esd, and connector. ac cap cmf cmf v i a v i a ac cap v i a v i a cmf cmf cmf cmf hdmi connector sprs85x_pcb_hdmi_3 411 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-15. hdmi pcb stackup specifications (continued) parameter min typ max unit signal routing layers 2 3 - layers number of ground plane cuts allowed within hdmi routing region - - 0 cuts number of layers between hdmi routing region and reference ground plane - - 0 layers pcb trace width 4 mils 7.5.4.6 grounding each tmds channel has its own shield pin and they should be grounded to provide a return current path for the tmds signal. 7.5.5 pcie board design and layout guidelines the pcie interface on the device provides support for a 5.0 gbps lane with polarity inversion. 7.5.5.1 pcie connections and interface compliance the pcie interface on the device is compliant with the pcie revision 3.0 specification. please refer to the pcie specifications for all connections that are described in it. those recommendations are more descriptive and exhaustive than what is possible here. the use of pcie compatible bridges and switches is allowed for interfacing with more than one other processor or pcie device. 7.5.5.1.1 coupling capacitors ac coupling capacitors are required on the transmit data pair. table 7-16 shows the requirements for these capacitors. table 7-16. pcie ac coupling capacitors requirements parameter min typ max unit pcie ac coupling capacitor value 90 100 110 nf pcie ac coupling capacitor package size 0402 0603 eia (1) (2) (1) eia lxw units, i.e., a 0402 is a 40x20 mils surface mount capacitor. (2) the physical size of the capacitor should be as small as practical. use the same size on both lines in each pair placed side by side. 7.5.5.1.2 polarity inversion the pcie specification requires polarity inversion support. this means for layout purposes, polarity is unimportant because each signal can change its polarity on die inside the chip. this means polarity within a lane is unimportant for layout. 7.5.5.2 non-standard pcie connections the following sections contain suggestions for any pcie connection that is not described in the official pcie specification, such as an on-board device to device or device to other pcie compliant processor connection. 7.5.5.2.1 pcb stackup specifications table 7-17 shows the stackup and feature sizes required for these types of pcie connections. 412 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-17. pcie pcb stackup specifications parameter min typ max unit number of ground plane cuts allowed within pcie routing region - - 0 cuts number of layers between pcie routing area and reference plane (1) - - 0 layers pcb routing clearance 4 mils pcb trace width 4 mils (1) a reference plane may be a ground plane or the power plane referencing the pcie signals. 7.5.5.2.2 routing specifications 7.5.5.2.2.1 impedance the pcie data signal traces must be routed to achieve 100- ( 10%) differential impedance and 60- ( 10%) single-ended impedance. the single-ended impedance is required because differential signals are extremely difficult to closely couple on pcbs and, therefore, single-ended impedance becomes important. these requirements are the same as those recommended in the pcie motherboard checklist 1.0 document, available from pci-sig ( www.pcisig.com ). these impedances are impacted by trace width, trace spacing, distance between signals and referencing planes, and dielectric material. verify with a pcb design tool that the trace geometry for both data signal pairs result in as close to 100- differential impedance and 60- single-ended impedance as possible. for best accuracy, work with your pcb fabricator to ensure this impedance is met. see table 7-18 below. 7.5.5.2.2.2 differential coupling in general, closely coupled differential signal traces are not an advantage on pcbs. when differential signals are closely coupled, tight spacing and width control is necessary. very small width and spacing variations affect impedance dramatically, so tight impedance control can be more problematic to maintain in production. for pcbs with very tight space limitations (which are usually small) this can work, but for most pcbs, the loosely coupled option is probably best. loosely coupled pcb differential signals make impedance control much easier. wider traces and spacing make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and trace width variations don ? t affect impedance as much, therefore it ? s easier to maintain an accurate impedance over the length of the signal. for longer routes, the wider traces also show reduced skin effect and therefore often result in better signal integrity with a larger eye diagram opening. table 7-18 shows the routing specifications for the pcie data signals. table 7-18. pci-e routing specifications parameter min typ max unit pcie signal trace length (device balls to pcie connector) 4700 (1) mils differential pair trace matching 5 (2) mils number of stubs allowed on pcie traces (3) 0 stubs tx/rx pair differential impedance 90 100 110 tx/rx single-ended impedance 54 60 66 pad size of vias on pcie trace 25 (4) mils hole size of vias on pcie trace 14 mils number of vias on each pcie trace 0 vias pcie differential pair to any other trace spacing 2 ds (5) 413 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated (1) beyond this, signal integrity may suffer. (2) for example, rxp0 within 5 mils of rxn0. (3) inline pads may be used for probing. (4) 35-mil antipad maximum recommended. (5) ds = differential spacing of the pcie traces. table 7-19. pci-e routing recommendations item description reason esd part number none esd suppression generally not used on pcie 7.5.5.2.2.3 pair length matching each signal in the differential pair should be matched to within 5 mils of its matching differential signal. length matching should be done as close to the mismatch as possible. 7.5.5.3 ljcb_refn/p connections a common refclk rx architecture is required to be used for the device pcie interface. specifically, two modes of common refclk rx architecture are supported: ? external refclk mode : an common external 100mhz clock source is distributed to both the device and the link partner ? output refclk mode : a 100mhz hcsl clock source is output by the device and used by the link partner in external refclk mode , a high-quality, low-jitter, differential hcsl 100mhz clock source compliant to the pcie refclk ac specifications should be provided on the device ? s ljcb_clkn / ljcb_clkp inputs. alternatively, an lvds clock source can be used with the following additional requirements: ? external ac coupling capacitors described in table 7-20 should be populated at the ljcb_clkn / ljcb_clkp inputs. ? all termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer should be followed. in output refclk mode , the 100mhz clock from the device ? s dpll_pcie_ref should be output on the device ? s ljcb_clkn / ljcb_clkp pins and used as the hcsl refclk by the link partner. external near- side termination to ground described in table 7-21 is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode. table 7-20. ljcb_refn/p requirements in external lvds refclk mode parameter min typ max unit ljcb_clkn / ljcb_clkp ac coupling capacitor value 100 nf ljcb_clkn / ljcb_clkp ac coupling capacitor package size 0402 0603 eia (1) (2) (1) eia lxw units, i.e., a 0402 is a 40x20 mils surface mount capacitor. (2) the physical size of the capacitor should be as small as practical. use the same size on both lines in each pair placed side by side. table 7-21. ljcb_refn/p requirements in output refclk mode parameter min typ max unit ljcb_clkn / ljcb_clkp near-side termination to ground value 47.5 50 52.5 ohms 7.5.6 csi2 board design and routing guidelines the mipi d-phy signals include the csi2_0 camera serial interfaces to or from the device. for more information regarding the mipi-phy signals and corresponding balls, see table 4-5 , csi2 signal descriptions . 414 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated for more information, you can also see the mipi d-phy specification v1-01-00_r0-03 (specifically the interconnect and lane configuration and annex b interconnect design guidelines chapters). in the next section, the pcb guidelines of the following differential interfaces are presented: ? csi2_0 mipi csi-2 at 1.5 gbps table 7-22 lists the mipi d-phy interface signals in the device. table 7-22. mipi d-phy interface signals in the device signal name bottom ball signal name bottom ball csi2_0_dx0 ac1 csi2_0_dy0 ab2 csi2_0_dx1 ad1 csi2_0_dy1 ac2 csi2_0_dx2 ae2 csi2_0_dy2 ad2 7.5.6.1 csi2_0 mipi csi-2 (1.5 gbps) 7.5.6.1.1 general guidelines the general guidelines for the pcb differential lines are: ? differential trace impedance z 0 = 100 (minimum = 85 , maximum = 115 ) ? total conductor length from the device package pins to the peripheral device package pins is 25 to 30 cm with common fr4 pcb and flex materials. note longer interconnect length can be supported at the expense of detailed simulations of the complete link including driver and receiver models. the general rule of thumb for the space s = 2 w is not designated (see figure 7-19 , guard illustration ). it is because although the s = 2 w rule is a good rule of thumb, it is not always the best solution. the electrical performance will be checked with the frequency-domain specification. even though the designer does not follow the s = 2 w rule, the differential lines are ok if the lines satisfy the frequency-domain specification. because the mipi signals are used for low-power, single-ended signaling in addition to their high-speed differential implementation, the pairs must be loosely coupled. 7.5.6.1.2 length mismatch guidelines 7.5.6.1.2.1 csi2_0 mipi csi-2 (1.5 gbps) the guidelines of the length mismatch for csi-2 are presented in table 7-23 . table 7-23. length mismatch guidelines for csi-2 (1.5 gbps) parameter typical value unit operating speed 1500 mbps ui (bit time) 667 ps intralane skew have to satisfy mode-conversion s parameters (1) interlane skew (ui / 50) 13.34 ps pcb lane-to-lane skew (0.1 ui) 66.7 ps 415 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated (1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22 7.5.6.1.3 frequency-domain specification guidelines after the pcb design is finished, the s-parameters of the pcb differential lines will be extracted with a 3d maxwell equation solver such as the high-frequency structure simulator (hfss) or equivalent, and compared to the frequency-domain specification as defined in the section 7 of the mipi alliance specification for d-phy version v1-01-00_r0-03. if the pcb lines satisfy the frequency-domain specification, the design is finished. otherwise, the design needs to be improved. 7.6 clock routing guidelines 7.6.1 oscillator ground connection although the impedance of a ground plane is low it is, of course, not zero. therefore, any noise current in the ground plane causes a voltage drop in the ground. figure 7-36 shows the grounding scheme for high-frequency clock. (1) j in *_osc = 0 or 1 figure 7-36. grounding scheme for high-frequency clock 7.7 ddr3 board design and layout guidelines 7.7.1 ddr3 general board layout guidelines to help ensure good signaling performance, consider the following board design guidelines: ? avoid crossing splits in the power plane. ? minimize vref noise. ? use the widest trace that is practical between decoupling capacitors and memory module. ? maintain a single reference. ? minimize isi by keeping impedances matched. ? minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities. ? use proper low-pass filtering on the vref pins. ? keep the stub length as short as possible. ? add additional spacing for on-clock and strobe nets to eliminate crosstalk. ? maintain a common ground reference for all bypass and decoupling capacitors. ? take into account the differences in propagation delays between microstrip and stripline nets when evaluating timing constraints. xi_oscj vssa_oscj device xo_oscj c f1 crystal rd c f2 (optional) sprs906_pcb_clk_osc_03 416 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2 ddr3 board design and layout guidelines 7.7.2.1 board designs ti only supports board designs using ddr3 memory that follow the guidelines in this document. the switching characteristics and timing diagram for the ddr3 memory controller are shown in table 7-24 and figure 7-37 . table 7-24. switching characteristics over recommended operating conditions for ddr3 memory controller no. parameter min max unit 1 t c(ddr_clk) cycle time, ddr_clk 1.5 2.5 (1) ns (1) this is the absolute maximum the clock period can be. actual maximum clock period may be limited by ddr3 speed grade and operating frequency (see the ddr3 memory device data sheet). figure 7-37. ddr3 memory controller clock timing 7.7.2.2 ddr3 emif the processor contains one ddr3 emif with one chip select. 7.7.2.3 ddr3 device combinations because there are several possible combinations of device counts and single- or dual-side mounting, table 7-25 summarizes the supported device configurations. table 7-25. supported ddr3 device combinations number of ddr3 devices ddr3 device width (bits) mirrored? ddr3 emif width (bits) 1 16 n 16 2 8 y (1) 16 2 16 n 32 2 16 y (1) 32 3 16 n (3) 32 4 8 n 32 4 8 y (2) 32 5 8 n (3) 32 (1) two ddr3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of the board. (2) this is two mirrored pairs of ddr3 devices. (3) three or five ddr3 device combination is not available on this device, but combination types are retained for consistency with the dra7xx family of devices. 7.7.2.4 ddr3 interface schematic 7.7.2.4.1 32-bit ddr3 interface the ddr3 interface schematic varies, depending upon the width of the ddr3 devices used and the width of the bus used (16 or 32 bits). general connectivity is straightforward and very similar. 16-bit ddr devices look like two 8-bit devices. figure 7-38 and figure 7-39 show the schematic connections for 32-bit interfaces using x16 devices. ddr_clk 1 sprs906_pcb_ddr3_01 417 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2.4.2 16-bit ddr3 interface note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see figure 7-38 and figure 7-39 ); only the high-word ddr memories are removed and the unused dqs inputs are tied off. when not using all or part of a ddr interface, the proper method of handling the unused pins is to tie off the ddrx_dqs i pins to ground via a 1k- ? resistor and to tie off the ddrx_dqsn i pins to the corresponding vdds_ddr x supply via a 1k- ? resistor. this needs to be done for each byte not used. although these signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection against external electrical noise causing activity on the signals. the vdds_ddr x and ddrx_vref0 power supply pins need to be connected to their respective power supplies even if ddrx is not being used. all other ddr interface pins can be left unconnected. note that the supported modes for use of the ddr emif are 32-bits wide, 16-bits wide, or not used. 418 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-38. 32-bit, one-bank ddr3 interface schematic using two 16-bit ddr3 devices dq15dq8 udm udqs udqs dq7dq0 ldm ldqs ldqs ck dq15udm udqs udqs ddr1_d31ddr1_d24 16-bit ddr3 devices 0.1 f 0.1 f 0.1 f 32-bit ddr3 emif ddr1_odt1 ddr1_csn1 ddr1_dqm3 ddr1_dqs3 ddr1_dqsn3 ddr1_d23ddr1_d16 ddr1_dqm2 ddr1_dqs2 ddr1_dqsn2 ddr1_d15 ddr1_d8 ddr1_dqm1 ddr1_dqs1 ddr1_dqsn1 ddr1_d7 ddr1_d0 ddr1_dqm0 ddr1_dqs0 ddr1_dqsn0 ddr1_ck ddr1_nck ddr1_odt0 ddr1_csn0 ddr1_ba0ddr1_ba1 ddr1_ba2 ddr1_a0 ddr1_a15 ddr1_casn ddr1_rasn ddr1_wen ddr1_cke ddr1_rst ddr1_vref0 8 88 8 16 dq8 dq7d08 ldmldqs ldqs ck odt ba1 ba0ba2 cs a0 a15 cas ras we rst cke zq vrefdq vrefca zq ck ckodt ba1 ba0ba2 cs a0a15 cas ras we rst cke zq vrefdqvrefca zq zo zo zo zo ddr_vref ddr_vtt ddr_1v5 termination is required. see terminator comments. zo value determined according to the ddr memory device data sheet. zq 0.1 f sprs906_pcb_ddr3_02 nc nc 419 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-39. 32-bit, one-bank ddr3 interface schematic using four 8-bit ddr3 devices dq7dq0 dm/tqs dqs dqs dq7dq0 dm/tqs dqs dqs ck ddrx_d31ddrx_d24 8-bit ddr3 devices 0.1 f 0.1 f 0.1 f 32-bit ddr3 emif ddrx_dqm3 ddrx_dqs3 ddrx_dqsn3 ddrx_d23ddrx_d16 ddrx_dqm2 ddrx_dqs2 ddrx_dqsn2 ddrx_d15 ddrx_d8 ddrx_dqm1 ddrx_dqs1 ddrx_dqsn1 ddrx_d7ddrx_d0 ddrx_dqm0 ddrx_dqs0 ddrx_dqsn0 ddrx_ck ddrx_nck ddrx_odt0 ddrx_csn0 ddrx_ba0ddrx_ba1 ddrx_ba2 ddrx_a0 ddrx_a15 ddrx_casn ddrx_rasn ddrx_wen ddrx_cke ddrx_rst ddrx_vref0 ddrx_odt1 ddrx_csn1 8 88 8 16 ck odt ba1 ba0ba2 cs a0 a15 cas ras we rst cke zq vrefdq vrefca zq ck ckodt ba1 ba0ba2 cs a0a15 cas ras we rst cke zq vrefdqvrefca termination is required. see terminator comments. zo value determined according to the ddr memory device data sheet. zq dq7dq0 dm/tqs dqs dqs ck dq7dm/tqs dqs dqs 8-bit ddr3 devices 0.1 f 0.1 f dq0 ck odt ba1 ba0ba2 cs a0 a15 cas ras we rst cke zqvrefdq vrefca ck ck odt ba1 ba0ba2 cs a0a15 cas ras we rst cke zq vrefdqvrefca zq zo zo zo zo ddr_vref ddr_vtt ddr_1v5 zq zq tdqs nc nc tdqs tdqs nc tdqs nc 0.1 f sprs906_pcb_ddr3_03 nc nc 420 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2.5 compatible jedec ddr3 devices table 7-26 shows the parameters of the jedec ddr3 devices that are compatible with this interface. generally, the ddr3 interface is compatible with ddr3-1333 devices in the x8 or x16 widths. table 7-26. compatible jedec ddr3 devices (per interface) n o. parameter condition min max unit 1 jedec ddr3 device speed grade (1) ddr clock rate = 400mhz ddr3-800 ddr3-1600 400mhz < ddr clock rate 533mhz ddr3-1066 ddr3-1600 533mhz < ddr clock rate 667mhz ddr3-1333 ddr3-1600 2 jedec ddr3 device bit width x8 x16 bits 3 jedec ddr3 device count (2) 2 4 devices (1) refer to table 7-24 switching characteristics over recommended operating conditions for ddr3 memory controller for the range of supported ddr clock rates. (2) for valid ddr3 device configurations and device counts, see section 7.7.2.4 , figure 7-38 , and figure 7-39 . 7.7.2.6 pcb stackup the minimum stackup for routing the ddr3 interface is a six-layer stack up as shown in table 7-27 . additional layers may be added to the pcb stackup to accommodate other circuitry, enhance si/emi performance, or to reduce the size of the pcb footprint. complete stackup specifications are provided in table 7-28 . table 7-27. six-layer pcb stackup suggestion layer type description 1 signal top routing mostly vertical 2 plane ground 3 plane split power plane 4 plane split power plane or internal routing 5 plane ground 6 signal bottom routing mostly horizontal 421 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-28. pcb stackup specifications no. parameter min typ max unit ps1 pcb routing/plane layers 6 ps2 signal routing layers 3 ps3 full ground reference layers under ddr3 routing region (1) 1 ps4 full 1.5-v power reference layers under the ddr3 routing region (1) 1 ps5 number of reference plane cuts allowed within ddr routing region (2) 0 ps6 number of layers between ddr3 routing layer and reference plane (3) 0 ps7 pcb routing feature size 4 mils ps8 pcb trace width, w 4 mils ps9 single-ended impedance, zo 50 75 ? ps10 impedance control (5) z-5 z z+5 ? (1) ground reference layers are preferred over power reference layers. be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (2) no traces should cross reference plane cuts within the ddr routing region. high-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and emi radiation. (3) reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (4) an 18-mil pad assumes via channel is the most economical bga escape. a 20-mil pad may be used if additional layers are available for power routing. an 18-mil pad is required for minimum layer count escape. (5) z is the nominal singled-ended impedance selected for the pcb specified by ps9. 7.7.2.7 placement figure 7-40 shows the required placement for the processor as well as the ddr3 devices. the dimensions for this figure are defined in table 7-29 . the placement does not restrict the side of the pcb on which the devices are mounted. the ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. for a 16-bit ddr memory system, the high-word ddr3 devices are omitted from the placement. figure 7-40. placement specifications 422 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-29. placement specifications ddr3 no. parameter min max unit kod31 x1 500 mils kod32 x2 600 mils kod33 x3 600 mils kod34 y1 1800 mils kod35 y2 600 mils kod36 ddr3 keepout region (1) kod37 clearance from non-ddr3 signal to ddr3 keepout region (2) (3) 4 w (1) ddr3 keepout region to encompass entire ddr3 routing area. (2) non-ddr3 signals allowed within ddr3 keepout region provided they are separated from ddr3 routing layers by a ground plane. (3) if a device has more than one ddr controller, the signals from the other controller(s) are considered non-ddr3 and should be separated by this specification. 7.7.2.8 ddr3 keepout region the region of the pcb used for ddr3 circuitry must be isolated from other signals. the ddr3 keepout region is defined for this purpose and is shown in figure 7-41 . the size of this region varies with the placement and ddr routing. additional clearances required for the keepout region are shown in table 7- 29 . non-ddr3 signals should not be routed on the ddr signal layers within the ddr3 keepout region. non-ddr3 signals may be routed in the region, provided they are routed on layers separated from the ddr signal layers by a ground layer. no breaks should be allowed in the reference ground layers in this region. in addition, the 1.5-v ddr3 power plane should cover the entire keepout region. also note that the two signals from the ddr3 controller should be separated from each other by the specification in table 7- 29 (see kod37 ). figure 7-41. ddr3 keepout region 423 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2.9 bulk bypass capacitors bulk bypass capacitors are required for moderate speed bypassing of the ddr3 and other circuitry. table 7-30 contains the minimum numbers and capacitance required for the bulk bypass capacitors. note that this table only covers the bypass needs of the ddr3 controllers and ddr3 devices. additional bulk bypass capacitance may be needed for other circuitry. table 7-30. bulk bypass capacitors no. parameter min max unit 1 vdds_ddr x bulk bypass capacitor count (1) 1 devices 2 vdds_ddr x bulk bypass total capacitance 22 f (1) these devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high- speed (hs) bypass capacitors and ddr3 signal routing. 7.7.2.10 high-speed bypass capacitors high-speed (hs) bypass capacitors are critcal for proper ddr3 interface operation. it is particularly important to minimize the parasitic series inductance of the hs bypass capacitors, processor/ddr power, and processor/ddr ground connections. table 7-31 contains the specification for the hs bypass capacitors as well as for the power connections on the pcb. generally speaking, it is good to: 1. fit as many hs bypass capacitors as possible. 2. minimize the distance from the bypass cap to the pins/balls being bypassed. 3. use the smallest physical sized capacitors possible with the highest capacitance readily available. 4. connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible. 5. minimize via sharing. note the limites on via sharing shown in table 7-31 . table 7-31. high-speed bypass capacitors no. parameter min typ max unit 1 hs bypass capacitor package size (1) 0201 0402 10 mils 2 distance, hs bypass capacitor to processor being bypassed (2) (3) (4) 400 mils 3 processor hs bypass capacitor count per vdds_ddrx rail (12) see table 7-3 and (11) devices 4 processor hs bypass capacitor total capacitance per vdds_ddrx rail (12) see table 7-3 and (11) f 5 number of connection vias for each device power/ground ball (5) vias 6 trace length from device power/ground ball to connection via (2) 35 70 mils 7 distance, hs bypass capacitor to ddr device being bypassed (6) 150 mils 8 ddr3 device hs bypass capacitor count (7) 12 devices 9 ddr3 device hs bypass capacitor total capacitance (7) 0.85 f 10 number of connection vias for each hs capacitor (8) (9) 2 vias 11 trace length from bypass capacitor connect to connection via (2) (9) 35 100 mils 12 number of connection vias for each ddr3 device power/ground ball (10) 1 vias 13 trace length from ddr3 device power/ground ball to connection via (2) (8) 35 60 mils (1) lxw, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor. (2) closer/shorter is better. (3) measured from the nearest processor power/ground ball to the center of the capacitor package. (4) three of these capacitors should be located underneath the processor, between the cluster of ddr_1v5 balls and ground balls, between the ddr interfaces on the package. (5) see the via channel ? escape for the processor package. (6) measured from the ddr3 device power/ground ball to the center of the capacitor package. (7) per ddr3 device. (8) an additional hs bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. no sharing of vias is permitted on the same side of the board. 424 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated (9) an hs bypass capacitor may share a via with a ddr device mounted on the same side of the pcb. a wide trace should be used for the connection and the length from the capacitor pad to the ddr device pad should be less than 150 mils. (10) up to a total of two pairs of ddr power/ground balls may share a via. (11) the capacitor recommendations in this data manual reflect only the needs of this processor. please see the memory vendor ? s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself. (12) for more information, see section 7.3 , core power domains . 7.7.2.10.1 return current bypass capacitors use additional bypass capacitors if the return current reference plane changes due to ddr3 signals hopping from one signal layer to another. the bypass capacitor here provides a path for the return current to hop planes along with the signal. as many of these return current bypass capacitors should be used as possible. because these are returns for signal current, the signal via size may be used for these capacitors. 7.7.2.11 net classes table 7-32 lists the clock net classes for the ddr3 interface. table 7-33 lists the signal net classes, and associated clock net classes, for signals in the ddr3 interface. these net classes are used for the termination and routing rules that follow. table 7-32. clock net class definitions clock net class processor pin names ck ddrx_ck/ddrx_nck dqs0 ddrx_dqs0 / ddrx_dqsn0 dqs1 ddrx_dqs1 / ddrx_dqsn1 dqs2 (1) ddrx_dqs2 / ddrx_dqsn2 dqs3 (1) ddrx_dqs3 / ddrx_dqsn3 (1) only used on 32-bit wide ddr3 memory systems. table 7-33. signal net class definitions signal net class associated clock net class processor pin names addr_ctrl ck ddr x _ba[2:0], ddr x _a[14:0], ddr x _csn j , ddr x _casn, ddr x _rasn, ddr x _wen, ddr x _cke, ddr x _odt i dq0 dqs0 ddr x _d[7:0], ddr x _dqm0 dq1 dqs1 ddr x _d[15:8], ddr x _dqm1 dq2 (1) dqs2 ddr x _d[23:16], ddr x _dqm2 dq3 (1) dqs3 ddr x _d[31:24], ddr x _dqm3 (1) only used on 32-bit wide ddr3 memory systems. 7.7.2.12 ddr3 signal termination signal terminators are required for the ck and addr_ctrl net classes. the data lines are terminated by odt and, thus, the pcb traces should be unterminated. detailed termination specifications are covered in the routing rules in the following sections. 7.7.2.13 vref_ddr routing ddrx_vref0 (vref) is used as a reference by the input buffers of the ddr3 memories as well as the processor. vref is intended to be half the ddr3 power supply voltage and is typically generated with the ddr3 vdds and vtt power supply. it should be routed as a nominal 20-mil wide trace with 0.1 f bypass capacitors near each device connection. narrowing of vref is allowed to accommodate routing congestion. 425 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2.14 vtt like vref, the nominal value of the vtt supply is half the ddr3 supply voltage. unlike vref, vtt is expected to source and sink current, specifically the termination current for the addr_ctrl net class thevinen terminators. vtt is needed at the end of the address bus and it should be routed as a power sub-plane. vtt should be bypassed near the terminator resistors. 7.7.2.15 ck and addr_ctrl topologies and routing definition the ck and addr_ctrl net classes are routed similarly and are length matched to minimize skew between them. ck is a bit more complicated because it runs at a higher transition rate and is differential. the following subsections show the topology and routing for various ddr3 configurations for ck and addr_ctrl. the figures in the following subsections define the terms for the routing specification detailed in table 7-34 . 7.7.2.15.1 four ddr3 devices four ddr3 devices are supported on the ddr emif consisting of four x8 ddr3 devices arranged as one bank (cs). these four devices may be mounted on a single side of the pcb, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and parts on the backside of the pcb. 7.7.2.15.1.1 ck and addr_ctrl topologies, four ddr3 devices figure 7-42 shows the topology of the ck net classes and figure 7-43 shows the topology for the corresponding addr_ctrl net classes. figure 7-42. ck topology for four x8 ddr3 devices as- as+ as- as+ as- as+ a1 a2 processor differential clock output buffer ddr differential ck input buffers routed as differential pair a3 a4 a3 at rcp clock parallel terminator a1 a2 a3 a4 a3 at as- as+ rcp cac ddr_1v5 0.1 f + C + C + C + C + C sprs906_pcb_ddr3_06 426 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-43. addr_ctrl topology for four x8 ddr3 devices 7.7.2.15.1.2 ck and addr_ctrl routing, four ddr3 devices figure 7-44 shows the ck routing for four ddr3 devices placed on the same side of the pcb. figure 7-45 shows the corresponding addr_ctrl routing. figure 7-44. ck routing for four single-side ddr3 devices a1 a2 processor address and control output buffer ddr address and control input buffers a3 a4 a3 at vtt address and control terminator rtt as as as as sprs906_pcb_ddr3_07 as+ as- = rcprcp cac ddr_1v5 0.1 f a1 a2 a3 a4 a3 a2 a3 a4 a3 a1 at at sprs906_pcb_ddr3_08 427 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-45. addr_ctrl routing for four single-side ddr3 devices to save pcb space, the four ddr3 memories may be mounted as two mirrored pairs at a cost of increased routing and assembly complexity. figure 7-46 and figure 7-47 show the routing for ck and addr_ctrl, respectively, for four ddr3 devices mirrored in a two-pair configuration. figure 7-46. ck routing for four mirrored ddr3 devices as = rtt a1 a2 a3 a4 a3 at vtt sprs906_pcb_ddr3_09 as+ as- = rcprcp cac ddr_1v5 0.1 f a1 a2 a3 a4 a2 a3 a4 a1 at at a3 a3 sprs906_pcb_ddr3_10 428 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-47. addr_ctrl routing for four mirrored ddr3 devices 7.7.2.15.2 two ddr3 devices two ddr3 devices are supported on the ddr emif consisting of two x8 ddr3 devices arranged as one bank (cs), 16 bits wide, or two x16 ddr3 devices arranged as one bank (cs), 32 bits wide. these two devices may be mounted on a single side of the pcb, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the pcb. 7.7.2.15.2.1 ck and addr_ctrl topologies, two ddr3 devices figure 7-48 shows the topology of the ck net classes and figure 7-49 shows the topology for the corresponding addr_ctrl net classes. figure 7-48. ck topology for two ddr3 devices as = rtt a1 a2 a3 a4 at vtt a3 sprs906_pcb_ddr3_11 as- as+ a1 a2 processor differential clock output buffer ddr differential ck input buffers routed as differential pair a3 at rcp clock parallel terminator a1 a2 a3 at as- as+ rcp cac ddr_1v5 0.1 f + C + C + C sprs906_pcb_ddr3_12 429 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-49. addr_ctrl topology for two ddr3 devices 7.7.2.15.2.2 ck and addr_ctrl routing, two ddr3 devices figure 7-50 shows the ck routing for two ddr3 devices placed on the same side of the pcb. figure 7-51 shows the corresponding addr_ctrl routing. figure 7-50. ck routing for two single-side ddr3 devices as+ as- = rcprcp cac ddr_1v5 0.1 f a1 a2 a3 at a2 a3 at a1 sprs906_pcb_ddr3_14 a1 a2 processor address and control output buffer ddr address and control input buffers a3 at vtt address and control terminator rtt as as sprs906_pcb_ddr3_13 430 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-51. addr_ctrl routing for two single-side ddr3 devices to save pcb space, the two ddr3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. figure 7-52 and figure 7-53 show the routing for ck and addr_ctrl, respectively, for two ddr3 devices mirrored in a single-pair configuration. figure 7-52. ck routing for two mirrored ddr3 devices as = rtt a1 a2 a3 at vtt sprs906_pcb_ddr3_15 as+ as- = rcprcp cac ddr_1v5 0.1 f a1 a2 a3 at a2 a3 at a1 sprs906_pcb_ddr3_16 431 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-53. addr_ctrl routing for two mirrored ddr3 devices 7.7.2.15.3 one ddr3 device a single ddr3 device is supported on the ddr emif consisting of one x16 ddr3 device arranged as one bank (cs), 16 bits wide. 7.7.2.15.3.1 ck and addr_ctrl topologies, one ddr3 device figure 7-54 shows the topology of the ck net classes and figure 7-55 shows the topology for the corresponding addr_ctrl net classes. figure 7-54. ck topology for one ddr3 device a1 a2 processor differential clock output buffer ddr differential ck input buffer routed as differential pair at rcp clock parallel terminator a1 a2 at as- as+ rcp cac ddr_1v5 0.1 f + C + C sprs906_pcb_ddr3_18 as = rtt a1 a2 a3 at vtt sprs906_pcb_ddr3_17 432 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-55. addr_ctrl topology for one ddr3 device 7.7.2.15.3.2 ck and addr/ctrl routing, one ddr3 device figure 7-56 shows the ck routing for one ddr3 device placed on the same side of the pcb. figure 7-57 shows the corresponding addr_ctrl routing. figure 7-56. ck routing for one ddr3 device a1 a2 processor address and control output buffer ddr address and control input buffers at vtt address and control terminator rtt as sprs906_pcb_ddr3_19 as+ as- = rcprcp cac ddr_1v5 0.1 f a1 a2 at a2 at a1 sprs906_pcb_ddr3_20 433 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated figure 7-57. addr_ctrl routing for one ddr3 device 7.7.2.16 data topologies and routing definition no matter the number of ddr3 devices used, the data line topology is always point to point, so its definition is simple. care should be taken to minimize layer transitions during routing. if a layer transition is necessary, it is better to transition to a layer using the same reference plane. if this cannot be accommodated, ensure there are nearby ground vias to allow the return currents to transition between reference planes if both reference planes are ground or vdds_ddr. ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes if one of the reference planes is ground. the goal is to minimize the size of the return current loops. 7.7.2.16.1 dqs and dq/dm topologies, any number of allowed ddr3 devices dqs lines are point-to-point differential, and dq/dm lines are point-to-point singled ended. figure 7-58 and figure 7-59 show these topologies. figure 7-58. dqs topology figure 7-59. dq/dm topology dn processor dq and dm io buffer ddrdq and dm io buffer n = 0, 1, 2, 3 sprs906_pcb_ddr3_23 as = rtt a1 a2 at vtt sprs906_pcb_ddr3_21 processor dqs io buffer ddrdqs io buffer routed differentially n = 0, 1, 2, 3 dqsn- dqsn+ sprs906_pcb_ddr3_22 434 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated 7.7.2.16.2 dqs and dq/dm routing, any number of allowed ddr3 devices figure 7-60 and figure 7-61 show the dqs and dq/dm routing. figure 7-60. dqs routing with any number of allowed ddr3 devices figure 7-61. dq/dm routing with any number of allowed ddr3 devices 7.7.2.17 routing specification 7.7.2.17.1 ck and addr_ctrl routing specification skew within the ck and addr_ctrl net classes directly reduces setup and hold margin and, thus, this skew must be controlled. the only way to practically match lengths on a pcb is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. a metric to establish this maximum length is manhattan distance. the manhattan distance between two points on a pcb is the length between the points when connecting them only with horizontal or vertical segments. a reasonable trace route length is to within a percentage of its manhattan distance. caclm is defined as clock address control longest manhattan distance. dqsn+ dqsn- n = 0, 1, 2, 3 routed differentially dqs sprs906_pcb_ddr3_24 dn n = 0, 1, 2, 3 dq and dm sprs906_pcb_ddr3_25 435 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated given the clock and address pin locations on the processor and the ddr3 memories, the maximum possible manhattan distance can be determined given the placement. figure 7-62 and figure 7-63 show this distance for four loads and two loads, respectively. it is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. caclm is determined similarly for other address bus configurations; that is, it is based on the longest net of the ck/addr_ctrl net class. for ck and addr_ctrl routing, these specifications are contained in table 7-34 . a. it is very likely that the longest ck/addr_ctrl manhattan distance will be for address input 8 (a8) on the ddr3 memories. caclm is based on the longest manhattan distance due to the device placement. verify the net class that satisfies this criteria and use as the baseline for ck/addr_ctrl skew matching and length control. the length of shorter ck/addr_ctrl stubs as well as the length of the terminator stub are not included in this length calculation. non-included lengths are grayed out in the figure. assuming a8 is the longest, calm = caclmy + caclmx + 300 mils. the extra 300 mils allows for routing down lower than the ddr3 memories and returning up to reach a8. figure 7-62. caclm for four address loads on one side of pcb as = rtt a1 a2 a3 a4 a3 at vtt a8 (a) a8 (a) a8 (a) a8 (a) a8 (a) caclmx caclmy sprs906_pcb_ddr3_26 436 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated a. it is very likely that the longest ck/addr_ctrl manhattan distance will be for address input 8 (a8) on the ddr3 memories. caclm is based on the longest manhattan distance due to the device placement. verify the net class that satisfies this criteria and use as the baseline for ck/addr_ctrl skew matching and length control. the length of shorter ck/addr_ctrl stubs as well as the length of the terminator stub are not included in this length calculation. non-included lengths are grayed out in the figure. assuming a8 is the longest, calm = caclmy + caclmx + 300 mils. the extra 300 mils allows for routing down lower than the ddr3 memories and returning up to reach a8. figure 7-63. caclm for two address loads on one side of pcb table 7-34. ck and addr_ctrl routing specification (2) (3) no. parameter min typ max unit cars31 a1+a2 length 500 (1) ps cars32 a1+a2 skew 29 ps cars33 a3 length 125 ps cars34 a3 skew (4) 6 ps cars35 a3 skew (5) 6 ps cars36 a4 length 125 ps cars37 a4 skew 6 ps cars38 as length 5 17 (1) ps cars39 as skew 1.3 14 (1) ps cars310 as+/as- length 5 12 ps cars311 as+/as- skew 1 ps cars312 at length (6) 75 ps cars313 at skew (7) 14 ps cars314 at skew (8) 1 ps cars315 ck/addr_ctrl trace length 1020 ps cars316 vias per trace 3 (1) vias cars317 via count difference 1 (15) vias cars318 center-to-center ck to other ddr3 trace spacing (9) 4w cars319 center-to-center addr_ctrl to other ddr3 trace spacing (9) (10) 4w cars320 center-to-center addr_ctrl to other addr_ctrl trace spacing (9) 3w as = rtt a1 a2 a3 at vtt a8 (a) a8 (a) a8 (a) caclmx caclmy sprs906_pcb_ddr3_27 437 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated table 7-34. ck and addr_ctrl routing specification (2) (3) (continued) no. parameter min typ max unit cars321 ck center-to-center spacing (11) (12) cars322 ck spacing to other net (9) 4w cars323 rcp (13) zo-1 zo zo+1 cars324 rtt (13) (14) zo-5 zo zo+5 (1) max value is based upon conservative signal integrity approach. this value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation. (2) the use of vias should be minimized. (3) additional bypass capacitors are required when using the ddr_1v5 plane as the reference plane to allow the return current to jump between the ddr_1v5 plane and the ground plane when the net class switches layers at a via. (4) non-mirrored configuration (all ddr3 memories on same side of pcb). (5) mirrored configuration (one ddr3 device on top of the board and one ddr3 device on the bottom). (6) while this length can be increased for convenience, its length should be minimized. (7) addr_ctrl net class only (not ck net class). minimizing this skew is recommended, but not required. (8) ck net class only. (9) center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length. (10) the addr_ctrl net class of the other ddr emif is considered other ddr3 trace spacing . (11) ck spacing set to ensure proper differential impedance. (12) the most important thing to do is control the impedance so inadvertent impedance mismatches are not created. generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, zo. (13) source termination (series resistor at driver) is specifically not allowed. (14) termination values should be uniform across the net class. (15) via count difference may increase by 1 only if accurate 3-d modeling of the signal flight times ? including accurately modeled signal propagation through vias ? has been applied to ensure all segment skew maximums are not exceeded. 7.7.2.17.2 dqs and dq routing specification skew within the dqs and dq/dm net classes directly reduces setup and hold margin and thus this skew must be controlled. the only way to practically match lengths on a pcb is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. as with ck and addr_ctrl, a reasonable trace route length is to within a percentage of its manhattan distance. dqlmn is defined as dq longest manhattan distance n, where n is the byte number. for a 32-bit interface, there are four dqlms, dqlm0-dqlm3. likewise, for a 16-bit interface, there are two dqlms, dqlm0-dqlm1. note it is not required, nor is it recommended, to match the lengths across all bytes. length matching is only required within each byte. given the dqs and dq/dm pin locations on the processor and the ddr3 memories, the maximum possible manhattan distance can be determined given the placement. figure 7-64 shows this distance for four loads. it is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. for dqs and dq/dm routing, these specifications are contained in table 7-35 . 438 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 applications, implementation, and layout copyright ? 2016 ? 2018, texas instruments incorporated there are four dqlms, one for each byte (32-bit interface). each dqlm is the longest manhattan distance of the byte; therefore: dqlm0 = dqlmx0 + dqlmy0 dqlm1 = dqlmx1 + dqlmy1 dqlm2 = dqlmx2 + dqlmy2 dqlm3 = dqlmx3 + dqlmy3 figure 7-64. dqlm for any number of allowed ddr3 devices table 7-35. data routing specification (2) no. parameter min typ max unit drs31 db0 length 340 ps drs32 db1 length 340 ps drs33 db2 length 340 ps drs34 db3 length 340 ps drs35 dbn skew (3) 5 ps drs36 dqsn+ to dqsn- skew 1 ps drs37 dqsn to dbn skew (3) (4) 5 (10) ps drs38 vias per trace 2 (1) vias drs39 via count difference 0 (10) vias drs310 center-to-center dbn to other ddr3 trace spacing (6) 4 w (5) drs311 center-to-center dbn to other dbn trace spacing (7) 3 w (5) drs312 dqsn center-to-center spacing (8) (9) drs313 dqsn center-to-center spacing to other net 4 w (5) (1) max value is based upon conservative signal integrity approach. this value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation. (2) external termination disallowed. data termination should use built-in odt functionality. (3) length matching is only done within a byte. length matching across bytes is neither required nor recommended. (4) each dqs pair is length matched to its associated byte. (5) center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length. (6) other ddr3 trace spacing means other ddr3 net classes not within the byte. (7) this applies to spacing within the net classes of a byte. (8) dqs pair spacing is set to ensure proper differential impedance. (9) the most important thing to do is control the impedance so inadvertent impedance mismatches are not created. generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, zo. (10) via count difference may increase by 1 only if accurate 3-d modeling of the signal flight times ? including accurately modeled signal propagation through vias ? has been applied to ensure dbn skew and dqsn to dbn skew maximums are not exceeded. dqlmx3 dqlmy0 dqlmy3 dqlmy2 db3 dqlmx2 db2 3 2 1 dq[23:31]/dm3/dqs3 0 dq[16:23]/dm2/dqs2 dqlmx1 db1 db0 dqlmx0 dq[8:15]/dm1/dqs1 dq[0:7]/dm0/dqs0 dqlmy1 db0 - db3 represent data bytes 0 - 3. sprs906_pcb_ddr3_28 439 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 device and documentation support copyright ? 2016 ? 2018, texas instruments incorporated 8 device and documentation support ti offers an extensive line of development tools, including methods to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules as listed below. 8.1 device nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all microprocessors (mpus) and support tools. each device has one of three prefixes: x, p, or null (no prefix) (for example, dra71x). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmdx) through fully qualified production devices and tools (tmds). device development evolutionary flow: x experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. p prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null production version of the silicon die that is fully qualified. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully-qualified development-support product. x and p devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." production devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (x or p) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. for orderable part numbers of dra71x devices in the cbd package type, see the package option addendum of this document, the ti website ( www.ti.com ), or contact your ti sales representative. for additional description of the device nomenclature markings on the die, see the silicon errata (literature number sprz426). 440 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 device and documentation support copyright ? 2016 ? 2018, texas instruments incorporated 8.1.1 standard package symbolization figure 8-1. printed device reference note some devices may have a cosmetic circular marking visible on the top of the device package which results from the production test process. in addition, some devices may also show a color variation in the package substrate which results from the substrate manufacturer. these differences are cosmetic only with no reliability impact. 8.1.2 device naming convention table 8-1. nomenclature description field parameter field description value description a device evolution stage (1) x prototype p preproduction (production test flow, no reliability data) blank production bbbbbb base production part number dra710 j6entry ultra low tier dra712 j6entry low tier dra714 j6entry mid tier dra716 j6entry high tier dra718 j6entry super high tier r device revision blank sr 1.0 a sr 2.0 b sr 2.1 z device speed i indicates the speed grade for each of the cores in the device. for more information see table 3-1 , device comparison table . g e other sprs906_pack_01 jacinto abbbbbbrzypppq1 xxxxxxx pin one indicator o g1 yyy zzz 441 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 device and documentation support copyright ? 2016 ? 2018, texas instruments incorporated table 8-1. nomenclature description (continued) field parameter field description value description y device type g general purpose (prototype and production) e emulation (e) devices s high-security device, secure boot supported d high security prototype devices with ti development keys (d) yn letter followed by number indicates hs device with customer key ppp package designator cbd cbd s-pbga-n538 (17mm 17mm) package q1 automotive designator blank not meeting automotive qualification q1 meeting q100 equal requirements, with exceptions as specified in dm. xxxxxxx lot trace code yyy production code, for ti use only zzz production code, for ti use only o pin one designator g1 ecat ? green package designator (1) to designate the stages in the product development cycle, ti assigns prefixes to the part numbers. these prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices. prototype devices are shipped against the following disclaimer: ? this product is still under development and is intended for internal evaluation purposes. ? notwithstanding any provision to the contrary, ti makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device. (2) applies to device max junction temperature. note blank in the symbol or part number is collapsed so there are no gaps between characters. 8.2 tools and software the following products support development for dra71x platforms: development tools dra71x clock tree tool is interactive clock tree configuration software that allows the user to visualize the device clock tree, interact with clock tree elements and view the effect on prcm registers, interact with the prcm registers and view the effect on the device clock tree, and view a trace of all the device registers affected by the user interaction with the clock tree. dra71x register descriptor tool is an interactive device register configuration tool that allows users to visualize the register state on power-on reset, and then customize the configuration of the device for the specific use-case. dra71x pad configuration tool is an interactive pad-configuration tool that allows the user to visualize the device pad configuration state on power-on reset and then customize the configuration of the pads for the specific use-case and identify the device register settings associated to that configuration. for a complete listing of development-support tools for the processor platform, visit the texas instruments website at www.ti.com . for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. 8.3 documentation support the following documents describe the dra71x devices. trm dra72x (sr2.0, sr1.0) and dra71x (sr2.1, sr2.0) soc for automotive infotainment technical reference manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the dra71x family of devices. 442 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 device and documentation support copyright ? 2016 ? 2018, texas instruments incorporated errata dra72x (sr2.0, sr1.0) and dra71x (sr2.1, sr2.0) soc for automotive infotainment silicon errata describes known advisories, limitations, and cautions on silicon and provides workarounds. 8.4 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8-2. related links parts product folder sample & buy technical documents tools & software support & community dra710 click here click here click here click here click here dra712 click here click here click here click here click here dra714 click here click here click here click here click here dra716 click here click here click here click here click here dra718 click here click here click here click here click here 8.5 receiving notification of documentation updates to receive notification of documentation updates ? including silicon errata ? go to the product folder for your device on www.ti.com . in the upper right-hand corner, click the "alert me" button. this registers you to receive a weekly digest of product information that has changed (if any). for change details, check the revision history of any revised document. 8.6 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti embedded processors wiki texas instruments embedded processors wiki. established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.7 trademarks icepick is a trademark of texas instruments inc. cortex is a registered trademark of arm limited. neon, isa, coresight are trademarks of arm limited. arm, cortex, thumb are registered trademarks of arm limited. arm is a registered trademark of arm ltd. neon is a trademark of arm ltd.. hdq is a trademark of benchmarq. hdmi is a trademark of hdmi licensing, llc. powervr is a registered trademark of imagination technologies limited. powervr is a registered trademark of imagination technologies ltd. jtag is a registered trademark of jtag technologies, inc.. 1-wire is a registered trademark of maxim integrated. mipi is a registered trademark of mobile industry processor interface (mipi) alliance. mmc is a trademark of multimediacard association. pci express is a registered trademark of pci-sig. sd is a registered trademark of toshiba corporation. vivante is a registered trademark of vivante corporation. neon, are trademarks of ~arm ltd.. is a registered trademark of ~sgi. all other trademarks are the property of their respective owners. 443 dra71 www.ti.com sprs960e ? june 2016 ? revised july 2018 submit documentation feedback product folder links: dra71 device and documentation support copyright ? 2016 ? 2018, texas instruments incorporated 8.8 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.9 export control notice recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the u.s., eu, and other export administration regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by u.s. or other applicable laws, without obtaining prior authorization from u.s. department of commerce and other competent government authorities to the extent required by those laws. 8.10 glossary ti glossary this glossary lists and explains terms, acronyms, and definitions. 444 dra71 sprs960e ? june 2016 ? revised july 2018 www.ti.com submit documentation feedback product folder links: dra71 mechanical packaging and orderable information copyright ? 2016 ? 2018, texas instruments incorporated 9 mechanical packaging and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 9.1 mechanical data the device package has been specially engineered with a technology called via channel. the via channel array technology allows larger than normal pcb via sizes, reduces the number of pcb signal layers required in a pcb design with this package, and will substantially reduce pcb costs compared to a full array 0.65mm pitch package. package option addendum www.ti.com 24-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dra710begcbdq1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra710begcbdq1 jacinto 784 784 cbd g1 dra710begcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra710begcbdq1 jacinto 784 784 cbd g1 dra712begcbdq1 active fcbga cbd 538 1 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra712begcbdq1 jacinto 784 784 cbd g1 dra714begcbdq1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra714begcbdq1 jacinto 784 784 cbd g1 dra714begcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra714begcbdq1 jacinto 784 784 cbd g1 dra716bggcbdq1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra716bggcbdq1 jacinto 784 784 cbd g1 dra716bggcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra716bggcbdq1 jacinto 784 784 cbd g1 dra716bhgcbdq1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra716bhgcbdq1 jacinto 784 784 cbd g1 dra716bhgcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra716bhgcbdq1 jacinto 784 784 cbd g1 package option addendum www.ti.com 24-aug-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DRA718BIGCBDQ1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 DRA718BIGCBDQ1 jacinto 784 784 cbd g1 dra718bigcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 DRA718BIGCBDQ1 jacinto 784 784 cbd g1 dra718bjgcbdq1 active fcbga cbd 538 90 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra718bjgcbdq1 jacinto 784 784 cbd g1 dra718bjgcbdrq1 active fcbga cbd 538 750 green (rohs & no sb/br) cu osp | call ti level-3-260c-168 hr -40 to 125 dra718bjgcbdq1 jacinto 784 784 cbd g1 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. package option addendum www.ti.com 24-aug-2018 addendum-page 3 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. www.ti.com package outline c 1.298 max typ 0.36 0.26 15.6 typ 15.6 typ 0.65 typ 0.65 typ 538 x 0.47 0.37 (0.378) a 17.1 16.9 b 17.1 16.9 (0.7) typ ( 14) (0.7) typ 4x (r ) 1 fcbga - 1.298 mm max height cbd0538a ball grid array 4222967/a 04/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. dimension is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and seating plane are defined by the spherical crowns of the solder balls. ball a1 corner seating plane ball typ 0.1 c note 4 a c e g j l n r u w aa ac ae 1 2 3 0.15 c a b 0.08 c symm symm 4 note 3 5 6 7 8 9 10 11 12 13 14 15 16 17 19 21 23 25 18 20 22 24 b d f h k m p t v y ab ad scale 0.800 www.ti.com example board layout 538 x ( ) 0.35 (0.65) typ (0.65) typ ( ) metal 0.35 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.35 0.05 min fcbga - 1.298 mm max height cbd0538a ball grid array 4222967/a 04/2016 notes: (continued) 5. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number spru811 (www.ti.com/lit/spru811). symm symm land pattern example scale:6x 1 a b c d e f g h j k l m n p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 r t u v w y aa ab ac ad ae non-solder mask defined (preferred) solder mask details not to scale solder mask defined www.ti.com example stencil design (0.65) typ (0.65) typ 538 x ( ) 0.35 fcbga - 1.298 mm max height cbd0538a ball grid array 4222967/a 04/2016 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. solder paste example based on 0.15 mm thick stencil scale:6x symm symm 1 a b c d e f g h j k l m n p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 r t u v w y aa ab ac ad ae important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated |
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